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43 #ifndef __ARCH_ARM_MISCREGS_HH__
44 #define __ARCH_ARM_MISCREGS_HH__
48 #include "base/bitunion.hh"
49 #include "base/compiler.hh"
76 MISCREG_CPSR = 0, // 0
78 MISCREG_SPSR_FIQ, // 2
79 MISCREG_SPSR_IRQ, // 3
80 MISCREG_SPSR_SVC, // 4
81 MISCREG_SPSR_MON, // 5
82 MISCREG_SPSR_ABT, // 6
83 MISCREG_SPSR_HYP, // 7
84 MISCREG_SPSR_UND, // 8
93 MISCREG_CPSR_MODE, // 15
95 MISCREG_FPSCR_EXC, // 17
96 MISCREG_FPSCR_QC, // 18
97 MISCREG_LOCKADDR, // 19
98 MISCREG_LOCKFLAG, // 20
99 MISCREG_PRRR_MAIR0, // 21
100 MISCREG_PRRR_MAIR0_NS, // 22
101 MISCREG_PRRR_MAIR0_S, // 23
102 MISCREG_NMRR_MAIR1, // 24
103 MISCREG_NMRR_MAIR1_NS, // 25
104 MISCREG_NMRR_MAIR1_S, // 26
105 MISCREG_PMXEVTYPER_PMCCFILTR, // 27
106 MISCREG_SCTLR_RST, // 28
107 MISCREG_SEV_MAILBOX, // 29
109 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
110 MISCREG_DBGDIDR, // 30
111 MISCREG_DBGDSCRint, // 31
112 MISCREG_DBGDCCINT, // 32
113 MISCREG_DBGDTRTXint, // 33
114 MISCREG_DBGDTRRXint, // 34
115 MISCREG_DBGWFAR, // 35
116 MISCREG_DBGVCR, // 36
117 MISCREG_DBGDTRRXext, // 37
118 MISCREG_DBGDSCRext, // 38
119 MISCREG_DBGDTRTXext, // 39
120 MISCREG_DBGOSECCR, // 40
121 MISCREG_DBGBVR0, // 41
122 MISCREG_DBGBVR1, // 42
123 MISCREG_DBGBVR2, // 43
124 MISCREG_DBGBVR3, // 44
125 MISCREG_DBGBVR4, // 45
126 MISCREG_DBGBVR5, // 46
127 MISCREG_DBGBCR0, // 47
128 MISCREG_DBGBCR1, // 48
129 MISCREG_DBGBCR2, // 49
130 MISCREG_DBGBCR3, // 50
131 MISCREG_DBGBCR4, // 51
132 MISCREG_DBGBCR5, // 52
133 MISCREG_DBGWVR0, // 53
134 MISCREG_DBGWVR1, // 54
135 MISCREG_DBGWVR2, // 55
136 MISCREG_DBGWVR3, // 56
137 MISCREG_DBGWCR0, // 57
138 MISCREG_DBGWCR1, // 58
139 MISCREG_DBGWCR2, // 59
140 MISCREG_DBGWCR3, // 60
141 MISCREG_DBGDRAR, // 61
142 MISCREG_DBGBXVR4, // 62
143 MISCREG_DBGBXVR5, // 63
144 MISCREG_DBGOSLAR, // 64
145 MISCREG_DBGOSLSR, // 65
146 MISCREG_DBGOSDLR, // 66
147 MISCREG_DBGPRCR, // 67
148 MISCREG_DBGDSAR, // 68
149 MISCREG_DBGCLAIMSET, // 69
150 MISCREG_DBGCLAIMCLR, // 70
151 MISCREG_DBGAUTHSTATUS, // 71
152 MISCREG_DBGDEVID2, // 72
153 MISCREG_DBGDEVID1, // 73
154 MISCREG_DBGDEVID0, // 74
157 MISCREG_TEEHBR, // 77
161 // AArch32 CP15 registers (system control)
167 MISCREG_REVIDR, // 85
168 MISCREG_ID_PFR0, // 86
169 MISCREG_ID_PFR1, // 87
170 MISCREG_ID_DFR0, // 88
171 MISCREG_ID_AFR0, // 89
172 MISCREG_ID_MMFR0, // 90
173 MISCREG_ID_MMFR1, // 91
174 MISCREG_ID_MMFR2, // 92
175 MISCREG_ID_MMFR3, // 93
176 MISCREG_ID_ISAR0, // 94
177 MISCREG_ID_ISAR1, // 95
178 MISCREG_ID_ISAR2, // 96
179 MISCREG_ID_ISAR3, // 97
180 MISCREG_ID_ISAR4, // 98
181 MISCREG_ID_ISAR5, // 99
182 MISCREG_CCSIDR, // 100
183 MISCREG_CLIDR, // 101
185 MISCREG_CSSELR, // 103
186 MISCREG_CSSELR_NS, // 104
187 MISCREG_CSSELR_S, // 105
188 MISCREG_VPIDR, // 106
189 MISCREG_VMPIDR, // 107
190 MISCREG_SCTLR, // 108
191 MISCREG_SCTLR_NS, // 109
192 MISCREG_SCTLR_S, // 110
193 MISCREG_ACTLR, // 111
194 MISCREG_ACTLR_NS, // 112
195 MISCREG_ACTLR_S, // 113
196 MISCREG_CPACR, // 114
199 MISCREG_NSACR, // 117
200 MISCREG_HSCTLR, // 118
201 MISCREG_HACTLR, // 119
204 MISCREG_HCPTR, // 122
207 MISCREG_TTBR0, // 125
208 MISCREG_TTBR0_NS, // 126
209 MISCREG_TTBR0_S, // 127
210 MISCREG_TTBR1, // 128
211 MISCREG_TTBR1_NS, // 129
212 MISCREG_TTBR1_S, // 130
213 MISCREG_TTBCR, // 131
214 MISCREG_TTBCR_NS, // 132
215 MISCREG_TTBCR_S, // 133
219 MISCREG_DACR_NS, // 137
220 MISCREG_DACR_S, // 138
222 MISCREG_DFSR_NS, // 140
223 MISCREG_DFSR_S, // 141
225 MISCREG_IFSR_NS, // 143
226 MISCREG_IFSR_S, // 144
227 MISCREG_ADFSR, // 145
228 MISCREG_ADFSR_NS, // 146
229 MISCREG_ADFSR_S, // 147
230 MISCREG_AIFSR, // 148
231 MISCREG_AIFSR_NS, // 149
232 MISCREG_AIFSR_S, // 150
233 MISCREG_HADFSR, // 151
234 MISCREG_HAIFSR, // 152
237 MISCREG_DFAR_NS, // 155
238 MISCREG_DFAR_S, // 156
240 MISCREG_IFAR_NS, // 158
241 MISCREG_IFAR_S, // 159
242 MISCREG_HDFAR, // 160
243 MISCREG_HIFAR, // 161
244 MISCREG_HPFAR, // 162
245 MISCREG_ICIALLUIS, // 163
246 MISCREG_BPIALLIS, // 164
248 MISCREG_PAR_NS, // 166
249 MISCREG_PAR_S, // 167
250 MISCREG_ICIALLU, // 168
251 MISCREG_ICIMVAU, // 169
252 MISCREG_CP15ISB, // 170
253 MISCREG_BPIALL, // 171
254 MISCREG_BPIMVA, // 172
255 MISCREG_DCIMVAC, // 173
256 MISCREG_DCISW, // 174
257 MISCREG_ATS1CPR, // 175
258 MISCREG_ATS1CPW, // 176
259 MISCREG_ATS1CUR, // 177
260 MISCREG_ATS1CUW, // 178
261 MISCREG_ATS12NSOPR, // 179
262 MISCREG_ATS12NSOPW, // 180
263 MISCREG_ATS12NSOUR, // 181
264 MISCREG_ATS12NSOUW, // 182
265 MISCREG_DCCMVAC, // 183
266 MISCREG_DCCSW, // 184
267 MISCREG_CP15DSB, // 185
268 MISCREG_CP15DMB, // 186
269 MISCREG_DCCMVAU, // 187
270 MISCREG_DCCIMVAC, // 188
271 MISCREG_DCCISW, // 189
272 MISCREG_ATS1HR, // 190
273 MISCREG_ATS1HW, // 191
274 MISCREG_TLBIALLIS, // 192
275 MISCREG_TLBIMVAIS, // 193
276 MISCREG_TLBIASIDIS, // 194
277 MISCREG_TLBIMVAAIS, // 195
278 MISCREG_TLBIMVALIS, // 196
279 MISCREG_TLBIMVAALIS, // 197
280 MISCREG_ITLBIALL, // 198
281 MISCREG_ITLBIMVA, // 199
282 MISCREG_ITLBIASID, // 200
283 MISCREG_DTLBIALL, // 201
284 MISCREG_DTLBIMVA, // 202
285 MISCREG_DTLBIASID, // 203
286 MISCREG_TLBIALL, // 204
287 MISCREG_TLBIMVA, // 205
288 MISCREG_TLBIASID, // 206
289 MISCREG_TLBIMVAA, // 207
290 MISCREG_TLBIMVAL, // 208
291 MISCREG_TLBIMVAAL, // 209
292 MISCREG_TLBIIPAS2IS, // 210
293 MISCREG_TLBIIPAS2LIS, // 211
294 MISCREG_TLBIALLHIS, // 212
295 MISCREG_TLBIMVAHIS, // 213
296 MISCREG_TLBIALLNSNHIS, // 214
297 MISCREG_TLBIMVALHIS, // 215
298 MISCREG_TLBIIPAS2, // 216
299 MISCREG_TLBIIPAS2L, // 217
300 MISCREG_TLBIALLH, // 218
301 MISCREG_TLBIMVAH, // 219
302 MISCREG_TLBIALLNSNH, // 220
303 MISCREG_TLBIMVALH, // 221
305 MISCREG_PMCNTENSET, // 223
306 MISCREG_PMCNTENCLR, // 224
307 MISCREG_PMOVSR, // 225
308 MISCREG_PMSWINC, // 226
309 MISCREG_PMSELR, // 227
310 MISCREG_PMCEID0, // 228
311 MISCREG_PMCEID1, // 229
312 MISCREG_PMCCNTR, // 230
313 MISCREG_PMXEVTYPER, // 231
314 MISCREG_PMCCFILTR, // 232
315 MISCREG_PMXEVCNTR, // 233
316 MISCREG_PMUSERENR, // 234
317 MISCREG_PMINTENSET, // 235
318 MISCREG_PMINTENCLR, // 236
319 MISCREG_PMOVSSET, // 237
320 MISCREG_L2CTLR, // 238
321 MISCREG_L2ECTLR, // 239
323 MISCREG_PRRR_NS, // 241
324 MISCREG_PRRR_S, // 242
325 MISCREG_MAIR0, // 243
326 MISCREG_MAIR0_NS, // 244
327 MISCREG_MAIR0_S, // 245
329 MISCREG_NMRR_NS, // 247
330 MISCREG_NMRR_S, // 248
331 MISCREG_MAIR1, // 249
332 MISCREG_MAIR1_NS, // 250
333 MISCREG_MAIR1_S, // 251
334 MISCREG_AMAIR0, // 252
335 MISCREG_AMAIR0_NS, // 253
336 MISCREG_AMAIR0_S, // 254
337 MISCREG_AMAIR1, // 255
338 MISCREG_AMAIR1_NS, // 256
339 MISCREG_AMAIR1_S, // 257
340 MISCREG_HMAIR0, // 258
341 MISCREG_HMAIR1, // 259
342 MISCREG_HAMAIR0, // 260
343 MISCREG_HAMAIR1, // 261
345 MISCREG_VBAR_NS, // 263
346 MISCREG_VBAR_S, // 264
347 MISCREG_MVBAR, // 265
350 MISCREG_HVBAR, // 268
351 MISCREG_FCSEIDR, // 269
352 MISCREG_CONTEXTIDR, // 270
353 MISCREG_CONTEXTIDR_NS, // 271
354 MISCREG_CONTEXTIDR_S, // 272
355 MISCREG_TPIDRURW, // 273
356 MISCREG_TPIDRURW_NS, // 274
357 MISCREG_TPIDRURW_S, // 275
358 MISCREG_TPIDRURO, // 276
359 MISCREG_TPIDRURO_NS, // 277
360 MISCREG_TPIDRURO_S, // 278
361 MISCREG_TPIDRPRW, // 279
362 MISCREG_TPIDRPRW_NS, // 280
363 MISCREG_TPIDRPRW_S, // 281
364 MISCREG_HTPIDR, // 282
365 MISCREG_CNTFRQ, // 283
366 MISCREG_CNTKCTL, // 284
367 MISCREG_CNTP_TVAL, // 285
368 MISCREG_CNTP_TVAL_NS, // 286
369 MISCREG_CNTP_TVAL_S, // 287
370 MISCREG_CNTP_CTL, // 288
371 MISCREG_CNTP_CTL_NS, // 289
372 MISCREG_CNTP_CTL_S, // 290
373 MISCREG_CNTV_TVAL, // 291
374 MISCREG_CNTV_CTL, // 292
375 MISCREG_CNTHCTL, // 293
376 MISCREG_CNTHP_TVAL, // 294
377 MISCREG_CNTHP_CTL, // 295
378 MISCREG_IL1DATA0, // 296
379 MISCREG_IL1DATA1, // 297
380 MISCREG_IL1DATA2, // 298
381 MISCREG_IL1DATA3, // 299
382 MISCREG_DL1DATA0, // 300
383 MISCREG_DL1DATA1, // 301
384 MISCREG_DL1DATA2, // 302
385 MISCREG_DL1DATA3, // 303
386 MISCREG_DL1DATA4, // 304
387 MISCREG_RAMINDEX, // 305
388 MISCREG_L2ACTLR, // 306
390 MISCREG_HTTBR, // 308
391 MISCREG_VTTBR, // 309
392 MISCREG_CNTPCT, // 310
393 MISCREG_CNTVCT, // 311
394 MISCREG_CNTP_CVAL, // 312
395 MISCREG_CNTP_CVAL_NS, // 313
396 MISCREG_CNTP_CVAL_S, // 314
397 MISCREG_CNTV_CVAL, // 315
398 MISCREG_CNTVOFF, // 316
399 MISCREG_CNTHP_CVAL, // 317
400 MISCREG_CPUMERRSR, // 318
401 MISCREG_L2MERRSR, // 319
403 // AArch64 registers (Op0=2)
404 MISCREG_MDCCINT_EL1, // 320
405 MISCREG_OSDTRRX_EL1, // 321
406 MISCREG_MDSCR_EL1, // 322
407 MISCREG_OSDTRTX_EL1, // 323
408 MISCREG_OSECCR_EL1, // 324
409 MISCREG_DBGBVR0_EL1, // 325
410 MISCREG_DBGBVR1_EL1, // 326
411 MISCREG_DBGBVR2_EL1, // 327
412 MISCREG_DBGBVR3_EL1, // 328
413 MISCREG_DBGBVR4_EL1, // 329
414 MISCREG_DBGBVR5_EL1, // 330
415 MISCREG_DBGBCR0_EL1, // 331
416 MISCREG_DBGBCR1_EL1, // 332
417 MISCREG_DBGBCR2_EL1, // 333
418 MISCREG_DBGBCR3_EL1, // 334
419 MISCREG_DBGBCR4_EL1, // 335
420 MISCREG_DBGBCR5_EL1, // 336
421 MISCREG_DBGWVR0_EL1, // 337
422 MISCREG_DBGWVR1_EL1, // 338
423 MISCREG_DBGWVR2_EL1, // 339
424 MISCREG_DBGWVR3_EL1, // 340
425 MISCREG_DBGWCR0_EL1, // 341
426 MISCREG_DBGWCR1_EL1, // 342
427 MISCREG_DBGWCR2_EL1, // 343
428 MISCREG_DBGWCR3_EL1, // 344
429 MISCREG_MDCCSR_EL0, // 345
430 MISCREG_MDDTR_EL0, // 346
431 MISCREG_MDDTRTX_EL0, // 347
432 MISCREG_MDDTRRX_EL0, // 348
433 MISCREG_DBGVCR32_EL2, // 349
434 MISCREG_MDRAR_EL1, // 350
435 MISCREG_OSLAR_EL1, // 351
436 MISCREG_OSLSR_EL1, // 352
437 MISCREG_OSDLR_EL1, // 353
438 MISCREG_DBGPRCR_EL1, // 354
439 MISCREG_DBGCLAIMSET_EL1, // 355
440 MISCREG_DBGCLAIMCLR_EL1, // 356
441 MISCREG_DBGAUTHSTATUS_EL1, // 357
442 MISCREG_TEECR32_EL1, // 358
443 MISCREG_TEEHBR32_EL1, // 359
445 // AArch64 registers (Op0=1,3)
446 MISCREG_MIDR_EL1, // 360
447 MISCREG_MPIDR_EL1, // 361
448 MISCREG_REVIDR_EL1, // 362
449 MISCREG_ID_PFR0_EL1, // 363
450 MISCREG_ID_PFR1_EL1, // 364
451 MISCREG_ID_DFR0_EL1, // 365
452 MISCREG_ID_AFR0_EL1, // 366
453 MISCREG_ID_MMFR0_EL1, // 367
454 MISCREG_ID_MMFR1_EL1, // 368
455 MISCREG_ID_MMFR2_EL1, // 369
456 MISCREG_ID_MMFR3_EL1, // 370
457 MISCREG_ID_ISAR0_EL1, // 371
458 MISCREG_ID_ISAR1_EL1, // 372
459 MISCREG_ID_ISAR2_EL1, // 373
460 MISCREG_ID_ISAR3_EL1, // 374
461 MISCREG_ID_ISAR4_EL1, // 375
462 MISCREG_ID_ISAR5_EL1, // 376
463 MISCREG_MVFR0_EL1, // 377
464 MISCREG_MVFR1_EL1, // 378
465 MISCREG_MVFR2_EL1, // 379
466 MISCREG_ID_AA64PFR0_EL1, // 380
467 MISCREG_ID_AA64PFR1_EL1, // 381
468 MISCREG_ID_AA64DFR0_EL1, // 382
469 MISCREG_ID_AA64DFR1_EL1, // 383
470 MISCREG_ID_AA64AFR0_EL1, // 384
471 MISCREG_ID_AA64AFR1_EL1, // 385
472 MISCREG_ID_AA64ISAR0_EL1, // 386
473 MISCREG_ID_AA64ISAR1_EL1, // 387
474 MISCREG_ID_AA64MMFR0_EL1, // 388
475 MISCREG_ID_AA64MMFR1_EL1, // 389
476 MISCREG_CCSIDR_EL1, // 390
477 MISCREG_CLIDR_EL1, // 391
478 MISCREG_AIDR_EL1, // 392
479 MISCREG_CSSELR_EL1, // 393
480 MISCREG_CTR_EL0, // 394
481 MISCREG_DCZID_EL0, // 395
482 MISCREG_VPIDR_EL2, // 396
483 MISCREG_VMPIDR_EL2, // 397
484 MISCREG_SCTLR_EL1, // 398
485 MISCREG_ACTLR_EL1, // 399
486 MISCREG_CPACR_EL1, // 400
487 MISCREG_SCTLR_EL2, // 401
488 MISCREG_ACTLR_EL2, // 402
489 MISCREG_HCR_EL2, // 403
490 MISCREG_MDCR_EL2, // 404
491 MISCREG_CPTR_EL2, // 405
492 MISCREG_HSTR_EL2, // 406
493 MISCREG_HACR_EL2, // 407
494 MISCREG_SCTLR_EL3, // 408
495 MISCREG_ACTLR_EL3, // 409
496 MISCREG_SCR_EL3, // 410
497 MISCREG_SDER32_EL3, // 411
498 MISCREG_CPTR_EL3, // 412
499 MISCREG_MDCR_EL3, // 413
500 MISCREG_TTBR0_EL1, // 414
501 MISCREG_TTBR1_EL1, // 415
502 MISCREG_TCR_EL1, // 416
503 MISCREG_TTBR0_EL2, // 417
504 MISCREG_TCR_EL2, // 418
505 MISCREG_VTTBR_EL2, // 419
506 MISCREG_VTCR_EL2, // 420
507 MISCREG_TTBR0_EL3, // 421
508 MISCREG_TCR_EL3, // 422
509 MISCREG_DACR32_EL2, // 423
510 MISCREG_SPSR_EL1, // 424
511 MISCREG_ELR_EL1, // 425
512 MISCREG_SP_EL0, // 426
513 MISCREG_SPSEL, // 427
514 MISCREG_CURRENTEL, // 428
519 MISCREG_DSPSR_EL0, // 433
520 MISCREG_DLR_EL0, // 434
521 MISCREG_SPSR_EL2, // 435
522 MISCREG_ELR_EL2, // 436
523 MISCREG_SP_EL1, // 437
524 MISCREG_SPSR_IRQ_AA64, // 438
525 MISCREG_SPSR_ABT_AA64, // 439
526 MISCREG_SPSR_UND_AA64, // 440
527 MISCREG_SPSR_FIQ_AA64, // 441
528 MISCREG_SPSR_EL3, // 442
529 MISCREG_ELR_EL3, // 443
530 MISCREG_SP_EL2, // 444
531 MISCREG_AFSR0_EL1, // 445
532 MISCREG_AFSR1_EL1, // 446
533 MISCREG_ESR_EL1, // 447
534 MISCREG_IFSR32_EL2, // 448
535 MISCREG_AFSR0_EL2, // 449
536 MISCREG_AFSR1_EL2, // 450
537 MISCREG_ESR_EL2, // 451
538 MISCREG_FPEXC32_EL2, // 452
539 MISCREG_AFSR0_EL3, // 453
540 MISCREG_AFSR1_EL3, // 454
541 MISCREG_ESR_EL3, // 455
542 MISCREG_FAR_EL1, // 456
543 MISCREG_FAR_EL2, // 457
544 MISCREG_HPFAR_EL2, // 458
545 MISCREG_FAR_EL3, // 459
546 MISCREG_IC_IALLUIS, // 460
547 MISCREG_PAR_EL1, // 461
548 MISCREG_IC_IALLU, // 462
549 MISCREG_DC_IVAC_Xt, // 463
550 MISCREG_DC_ISW_Xt, // 464
551 MISCREG_AT_S1E1R_Xt, // 465
552 MISCREG_AT_S1E1W_Xt, // 466
553 MISCREG_AT_S1E0R_Xt, // 467
554 MISCREG_AT_S1E0W_Xt, // 468
555 MISCREG_DC_CSW_Xt, // 469
556 MISCREG_DC_CISW_Xt, // 470
557 MISCREG_DC_ZVA_Xt, // 471
558 MISCREG_IC_IVAU_Xt, // 472
559 MISCREG_DC_CVAC_Xt, // 473
560 MISCREG_DC_CVAU_Xt, // 474
561 MISCREG_DC_CIVAC_Xt, // 475
562 MISCREG_AT_S1E2R_Xt, // 476
563 MISCREG_AT_S1E2W_Xt, // 477
564 MISCREG_AT_S12E1R_Xt, // 478
565 MISCREG_AT_S12E1W_Xt, // 479
566 MISCREG_AT_S12E0R_Xt, // 480
567 MISCREG_AT_S12E0W_Xt, // 481
568 MISCREG_AT_S1E3R_Xt, // 482
569 MISCREG_AT_S1E3W_Xt, // 483
570 MISCREG_TLBI_VMALLE1IS, // 484
571 MISCREG_TLBI_VAE1IS_Xt, // 485
572 MISCREG_TLBI_ASIDE1IS_Xt, // 486
573 MISCREG_TLBI_VAAE1IS_Xt, // 487
574 MISCREG_TLBI_VALE1IS_Xt, // 488
575 MISCREG_TLBI_VAALE1IS_Xt, // 489
576 MISCREG_TLBI_VMALLE1, // 490
577 MISCREG_TLBI_VAE1_Xt, // 491
578 MISCREG_TLBI_ASIDE1_Xt, // 492
579 MISCREG_TLBI_VAAE1_Xt, // 493
580 MISCREG_TLBI_VALE1_Xt, // 494
581 MISCREG_TLBI_VAALE1_Xt, // 495
582 MISCREG_TLBI_IPAS2E1IS_Xt, // 496
583 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497
584 MISCREG_TLBI_ALLE2IS, // 498
585 MISCREG_TLBI_VAE2IS_Xt, // 499
586 MISCREG_TLBI_ALLE1IS, // 500
587 MISCREG_TLBI_VALE2IS_Xt, // 501
588 MISCREG_TLBI_VMALLS12E1IS, // 502
589 MISCREG_TLBI_IPAS2E1_Xt, // 503
590 MISCREG_TLBI_IPAS2LE1_Xt, // 504
591 MISCREG_TLBI_ALLE2, // 505
592 MISCREG_TLBI_VAE2_Xt, // 506
593 MISCREG_TLBI_ALLE1, // 507
594 MISCREG_TLBI_VALE2_Xt, // 508
595 MISCREG_TLBI_VMALLS12E1, // 509
596 MISCREG_TLBI_ALLE3IS, // 510
597 MISCREG_TLBI_VAE3IS_Xt, // 511
598 MISCREG_TLBI_VALE3IS_Xt, // 512
599 MISCREG_TLBI_ALLE3, // 513
600 MISCREG_TLBI_VAE3_Xt, // 514
601 MISCREG_TLBI_VALE3_Xt, // 515
602 MISCREG_PMINTENSET_EL1, // 516
603 MISCREG_PMINTENCLR_EL1, // 517
604 MISCREG_PMCR_EL0, // 518
605 MISCREG_PMCNTENSET_EL0, // 519
606 MISCREG_PMCNTENCLR_EL0, // 520
607 MISCREG_PMOVSCLR_EL0, // 521
608 MISCREG_PMSWINC_EL0, // 522
609 MISCREG_PMSELR_EL0, // 523
610 MISCREG_PMCEID0_EL0, // 524
611 MISCREG_PMCEID1_EL0, // 525
612 MISCREG_PMCCNTR_EL0, // 526
613 MISCREG_PMXEVTYPER_EL0, // 527
614 MISCREG_PMCCFILTR_EL0, // 528
615 MISCREG_PMXEVCNTR_EL0, // 529
616 MISCREG_PMUSERENR_EL0, // 530
617 MISCREG_PMOVSSET_EL0, // 531
618 MISCREG_MAIR_EL1, // 532
619 MISCREG_AMAIR_EL1, // 533
620 MISCREG_MAIR_EL2, // 534
621 MISCREG_AMAIR_EL2, // 535
622 MISCREG_MAIR_EL3, // 536
623 MISCREG_AMAIR_EL3, // 537
624 MISCREG_L2CTLR_EL1, // 538
625 MISCREG_L2ECTLR_EL1, // 539
626 MISCREG_VBAR_EL1, // 540
627 MISCREG_RVBAR_EL1, // 541
628 MISCREG_ISR_EL1, // 542
629 MISCREG_VBAR_EL2, // 543
630 MISCREG_RVBAR_EL2, // 544
631 MISCREG_VBAR_EL3, // 545
632 MISCREG_RVBAR_EL3, // 546
633 MISCREG_RMR_EL3, // 547
634 MISCREG_CONTEXTIDR_EL1, // 548
635 MISCREG_TPIDR_EL1, // 549
636 MISCREG_TPIDR_EL0, // 550
637 MISCREG_TPIDRRO_EL0, // 551
638 MISCREG_TPIDR_EL2, // 552
639 MISCREG_TPIDR_EL3, // 553
640 MISCREG_CNTKCTL_EL1, // 554
641 MISCREG_CNTFRQ_EL0, // 555
642 MISCREG_CNTPCT_EL0, // 556
643 MISCREG_CNTVCT_EL0, // 557
644 MISCREG_CNTP_TVAL_EL0, // 558
645 MISCREG_CNTP_CTL_EL0, // 559
646 MISCREG_CNTP_CVAL_EL0, // 560
647 MISCREG_CNTV_TVAL_EL0, // 561
648 MISCREG_CNTV_CTL_EL0, // 562
649 MISCREG_CNTV_CVAL_EL0, // 563
650 MISCREG_PMEVCNTR0_EL0, // 564
651 MISCREG_PMEVCNTR1_EL0, // 565
652 MISCREG_PMEVCNTR2_EL0, // 566
653 MISCREG_PMEVCNTR3_EL0, // 567
654 MISCREG_PMEVCNTR4_EL0, // 568
655 MISCREG_PMEVCNTR5_EL0, // 569
656 MISCREG_PMEVTYPER0_EL0, // 570
657 MISCREG_PMEVTYPER1_EL0, // 571
658 MISCREG_PMEVTYPER2_EL0, // 572
659 MISCREG_PMEVTYPER3_EL0, // 573
660 MISCREG_PMEVTYPER4_EL0, // 574
661 MISCREG_PMEVTYPER5_EL0, // 575
662 MISCREG_CNTVOFF_EL2, // 576
663 MISCREG_CNTHCTL_EL2, // 577
664 MISCREG_CNTHP_TVAL_EL2, // 578
665 MISCREG_CNTHP_CTL_EL2, // 579
666 MISCREG_CNTHP_CVAL_EL2, // 580
667 MISCREG_CNTPS_TVAL_EL1, // 581
668 MISCREG_CNTPS_CTL_EL1, // 582
669 MISCREG_CNTPS_CVAL_EL1, // 583
670 MISCREG_IL1DATA0_EL1, // 584
671 MISCREG_IL1DATA1_EL1, // 585
672 MISCREG_IL1DATA2_EL1, // 586
673 MISCREG_IL1DATA3_EL1, // 587
674 MISCREG_DL1DATA0_EL1, // 588
675 MISCREG_DL1DATA1_EL1, // 589
676 MISCREG_DL1DATA2_EL1, // 590
677 MISCREG_DL1DATA3_EL1, // 591
678 MISCREG_DL1DATA4_EL1, // 592
679 MISCREG_L2ACTLR_EL1, // 593
680 MISCREG_CPUACTLR_EL1, // 594
681 MISCREG_CPUECTLR_EL1, // 595
682 MISCREG_CPUMERRSR_EL1, // 596
683 MISCREG_L2MERRSR_EL1, // 597
684 MISCREG_CBAR_EL1, // 598
689 MISCREG_CP14_UNIMPL, // 601
690 MISCREG_CP15_UNIMPL, // 602
691 MISCREG_A64_UNIMPL, // 603
692 MISCREG_UNKNOWN, // 604
699 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
700 // tells whether the instruction should raise a
702 MISCREG_MUTEX, // True if the register corresponds to a pair of
703 // mutually exclusive registers
704 MISCREG_BANKED, // True if the register is banked between the two
705 // security states, and this is the parent node of the
706 // two banked registers
707 MISCREG_BANKED_CHILD, // The entry is one of the child registers that
708 // forms a banked set of regs (along with the
711 // Access permissions
717 // Privileged modes other than hypervisor or monitor
725 // Monitor mode, SCR.NS == 0
728 // Monitor mode, SCR.NS == 1
735 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
737 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
738 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
739 unsigned crm, unsigned opc2);
740 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
741 unsigned crn, unsigned crm,
743 // Whether a particular AArch64 system register is -always- read only.
744 bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
746 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
747 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
748 unsigned crm, unsigned opc2);
750 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
751 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
754 const char * const miscRegName[] = {
784 "pmxevtyper_pmccfiltr",
788 // AArch32 CP14 registers
840 // AArch32 CP15 registers
1082 // AArch64 registers (Op0=2)
1120 "dbgauthstatus_el1",
1124 // AArch64 registers (Op0=1,3)
1261 "tlbi_ipas2e1is_xt",
1262 "tlbi_ipas2le1is_xt",
1267 "tlbi_vmalls12e1is",
1374 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1375 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1378 Bitfield<31, 30> nz;
1382 Bitfield<26, 25> it1;
1384 Bitfield<23, 22> res0_23_22;
1385 Bitfield<21> ss; // AArch64
1386 Bitfield<20> il; // AArch64
1387 Bitfield<19, 16> ge;
1388 Bitfield<15, 10> it2;
1389 Bitfield<9> d; // AArch64
1394 Bitfield<9, 6> daif; // AArch64
1396 Bitfield<4> width; // AArch64
1397 Bitfield<3, 2> el; // AArch64
1398 Bitfield<4, 0> mode;
1399 Bitfield<0> sp; // AArch64
1402 // This mask selects bits of the CPSR that actually go in the CondCodes
1403 // integer register to allow renaming.
1404 static const uint32_t CondCodesMask = 0xF00F0000;
1405 static const uint32_t CpsrMaskQ = 0x08000000;
1415 Bitfield<4, 0> hpmn;
1426 Bitfield<10> tfp; // AArch64
1460 Bitfield<33> id; // AArch64
1461 Bitfield<32> cd; // AArch64
1462 Bitfield<31> rw; // AArch64
1463 Bitfield<30> trvm; // AArch64
1464 Bitfield<29> hcd; // AArch64
1465 Bitfield<28> tdz; // AArch64
1474 Bitfield<21> tacr; // AArch64
1484 Bitfield<11, 10> bsu;
1487 Bitfield<8> vse; // AArch64
1499 Bitfield<20> nstrcdis;
1501 Bitfield<15> nsasedis;
1502 Bitfield<14> nsd32dis;
1522 Bitfield<11> st; // AArch64
1523 Bitfield<10> rw; // AArch64
1527 Bitfield<7> smd; // AArch64
1538 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
1539 Bitfield<29> afe; // Access flag enable (AArch32 only)
1540 Bitfield<28> tre; // TEX remap enable (AArch32 only)
1541 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
1542 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
1543 // DC CVAC and IC IVAU instructions
1544 // (AArch64 SCTLR_EL1 only)
1545 Bitfield<25> ee; // Exception Endianness
1546 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
1547 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
1548 // (AArch64 SCTLR_EL1 only)
1549 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
1550 Bitfield<22> u; // Alignment (dropped in ARMv7)
1551 Bitfield<21> fi; // Fast interrupts configuration enable
1553 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
1555 Bitfield<19> dz; // Divide by Zero fault enable
1556 // (dropped in ARMv7)
1557 Bitfield<19> wxn; // Write permission implies XN
1558 Bitfield<18> ntwe; // Not trap WFE
1559 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1560 Bitfield<18> rao2; // Read as one
1561 Bitfield<16> ntwi; // Not trap WFI
1562 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1563 Bitfield<16> rao3; // Read as one
1564 Bitfield<15> uct; // Enable EL0 access to CTR_EL0
1565 // (AArch64 SCTLR_EL1 only)
1566 Bitfield<14> rr; // Round Robin select (ARMv7 only)
1567 Bitfield<14> dze; // Enable EL0 access to DC ZVA
1568 // (AArch64 SCTLR_EL1 only)
1569 Bitfield<13> v; // Vectors bit (AArch32 only)
1570 Bitfield<12> i; // Instruction cache enable
1571 Bitfield<11> z; // Branch prediction enable (ARMv7 only)
1572 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
1573 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
1574 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
1575 Bitfield<8> sed; // SETEND disable
1576 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1577 Bitfield<7> b; // Endianness support (dropped in ARMv7)
1578 Bitfield<7> itd; // IT disable
1579 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1580 Bitfield<6, 3> rao4; // Read as one
1581 Bitfield<6> thee; // ThumbEE enable
1582 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1583 Bitfield<5> cp15ben; // CP15 barrier enable
1584 // (AArch32 and AArch64 SCTLR_EL1 only)
1585 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
1586 // (AArch64 SCTLR_EL1 only)
1587 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
1588 Bitfield<2> c; // Cache enable
1589 Bitfield<1> a; // Alignment check enable
1590 Bitfield<0> m; // MMU enable
1599 Bitfield<11, 10> cp5;
1600 Bitfield<13, 12> cp6;
1601 Bitfield<15, 14> cp7;
1602 Bitfield<17, 16> cp8;
1603 Bitfield<19, 18> cp9;
1604 Bitfield<21, 20> cp10;
1605 Bitfield<21, 20> fpen; // AArch64
1606 Bitfield<23, 22> cp11;
1607 Bitfield<25, 24> cp12;
1608 Bitfield<27, 26> cp13;
1609 Bitfield<29, 28> rsvd;
1610 Bitfield<28> tta; // AArch64
1611 Bitfield<30> d32dis;
1612 Bitfield<31> asedis;
1616 Bitfield<3, 0> fsLow;
1617 Bitfield<5, 0> status; // LPAE
1618 Bitfield<7, 4> domain;
1620 Bitfield<10> fsHigh;
1623 Bitfield<13> cm; // LPAE
1639 Bitfield<18, 16> len;
1640 Bitfield<21, 20> stride;
1641 Bitfield<23, 22> rMode;
1652 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1653 // integer register to allow renaming.
1654 static const uint32_t FpCondCodesMask = 0xF0000000;
1655 // This mask selects the cumulative FP exception flags of the FPSCR.
1656 static const uint32_t FpscrExcMask = 0x0000009F;
1657 // This mask selects the cumulative saturation flag of the FPSCR.
1658 static const uint32_t FpscrQcMask = 0x08000000;
1663 Bitfield<29, 0> subArchDefined;
1667 Bitfield<3, 0> advSimdRegisters;
1668 Bitfield<7, 4> singlePrecision;
1669 Bitfield<11, 8> doublePrecision;
1670 Bitfield<15, 12> vfpExceptionTrapping;
1671 Bitfield<19, 16> divide;
1672 Bitfield<23, 20> squareRoot;
1673 Bitfield<27, 24> shortVectors;
1674 Bitfield<31, 28> roundingModes;
1678 Bitfield<3, 0> flushToZero;
1679 Bitfield<7, 4> defaultNaN;
1680 Bitfield<11, 8> advSimdLoadStore;
1681 Bitfield<15, 12> advSimdInteger;
1682 Bitfield<19, 16> advSimdSinglePrecision;
1683 Bitfield<23, 20> advSimdHalfPrecision;
1684 Bitfield<27, 24> vfpHalfPrecision;
1685 Bitfield<31, 28> raz;
1689 // Short-descriptor translation table format
1693 // Long-descriptor translation table format
1694 Bitfield<5, 0> t0sz;
1696 Bitfield<9, 8> irgn0;
1697 Bitfield<11, 10> orgn0;
1698 Bitfield<13, 12> sh0;
1700 Bitfield<21, 16> t1sz;
1703 Bitfield<25, 24> irgn1;
1704 Bitfield<27, 26> orgn1;
1705 Bitfield<29, 28> sh1;
1707 Bitfield<34, 32> ips;
1713 // TCR_EL2/3 (AArch64)
1714 Bitfield<18, 16> ps;
1719 Bitfield<2, 0> t0sz;
1720 Bitfield<9, 8> irgn0;
1721 Bitfield<11, 10> orgn0;
1722 Bitfield<13, 12> sh0;
1726 Bitfield<3, 0> t0sz;
1729 Bitfield<9, 8> irgn0;
1730 Bitfield<11, 10> orgn0;
1731 Bitfield<13, 12> sh0;
1740 Bitfield<11,10> tr5;
1741 Bitfield<13,12> tr6;
1742 Bitfield<15,14> tr7;
1763 Bitfield<11,10> ir5;
1764 Bitfield<13,12> ir6;
1765 Bitfield<15,14> ir7;
1766 Bitfield<17,16> or0;
1767 Bitfield<19,18> or1;
1768 Bitfield<21,20> or2;
1769 Bitfield<23,22> or3;
1770 Bitfield<25,24> or4;
1771 Bitfield<27,26> or5;
1772 Bitfield<29,28> or6;
1773 Bitfield<31,30> or7;
1776 BitUnion32(CONTEXTIDR)
1778 Bitfield<31,8> procid;
1779 EndBitUnion(CONTEXTIDR)
1782 Bitfield<2,0> sataRAMLatency;
1783 Bitfield<4,3> reserved_4_3;
1784 Bitfield<5> dataRAMSetup;
1785 Bitfield<8,6> tagRAMLatency;
1786 Bitfield<9> tagRAMSetup;
1787 Bitfield<11,10> dataRAMSlice;
1788 Bitfield<12> tagRAMSlice;
1789 Bitfield<20,13> reserved_20_13;
1790 Bitfield<21> eccandParityEnable;
1791 Bitfield<22> reserved_22;
1792 Bitfield<23> interptCtrlPresent;
1793 Bitfield<25,24> numCPUs;
1794 Bitfield<30,26> reserved_30_26;
1795 Bitfield<31> l2rstDISABLE_monitor;
1799 Bitfield<3,0> iCacheLineSize;
1800 Bitfield<13,4> raz_13_4;
1801 Bitfield<15,14> l1IndexPolicy;
1802 Bitfield<19,16> dCacheLineSize;
1803 Bitfield<23,20> erg;
1804 Bitfield<27,24> cwg;
1805 Bitfield<28> raz_28;
1806 Bitfield<31,29> format;
1815 Bitfield<63, 56> attr;
1816 Bitfield<39, 12> pa;
1824 Bitfield<31, 26> ec;
1826 Bitfield<15, 0> imm16;
1832 Bitfield<13, 12> res1_13_12_el2;
1834 Bitfield<9, 0> res1_9_0_el2;
1838 // Checks read access permissions to coproc. registers
1839 bool canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1842 // Checks write access permissions to coproc. registers
1843 bool canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1846 // Checks read access permissions to AArch64 system registers
1847 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1850 // Checks write access permissions to AArch64 system registers
1851 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1854 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1855 // for MCR/MRC instructions
1857 flattenMiscRegNsBanked(int reg, ThreadContext *tc);
1859 // Flattens a misc reg index using the specified security state. This is
1860 // used for opperations (eg address translations) where the security
1861 // state of the register access may differ from the current state of the
1864 flattenMiscRegNsBanked(int reg, ThreadContext *tc, bool ns);
1866 // Takes a misc reg index and returns the root reg if its one of a set of
1869 preUnflattenMiscReg();
1872 unflattenMiscReg(int reg);
1876 #endif // __ARCH_ARM_MISCREGS_HH__