src/arch/arm/miscregs.hh

   1 /*
   2  * Copyright (c) 2010-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_MISCREGS_HH__
  42 #define __ARCH_ARM_MISCREGS_HH__
  43
  44 #include <bitset>
  45 #include <tuple>
  46
  47 #include "arch/arm/miscregs_types.hh"
  48 #include "base/compiler.hh"
  49
  50 class ThreadContext;
  51
  52
  53 namespace ArmISA
  54 {
  55     enum MiscRegIndex {
  56         MISCREG_CPSR = 0,
  57         MISCREG_SPSR,
  58         MISCREG_SPSR_FIQ,
  59         MISCREG_SPSR_IRQ,
  60         MISCREG_SPSR_SVC,
  61         MISCREG_SPSR_MON,
  62         MISCREG_SPSR_ABT,
  63         MISCREG_SPSR_HYP,
  64         MISCREG_SPSR_UND,
  65         MISCREG_ELR_HYP,
  66         MISCREG_FPSID,
  67         MISCREG_FPSCR,
  68         MISCREG_MVFR1,
  69         MISCREG_MVFR0,
  70         MISCREG_FPEXC,
  71
  72         // Helper registers
  73         MISCREG_CPSR_MODE,
  74         MISCREG_CPSR_Q,
  75         MISCREG_FPSCR_EXC,
  76         MISCREG_FPSCR_QC,
  77         MISCREG_LOCKADDR,
  78         MISCREG_LOCKFLAG,
  79         MISCREG_PRRR_MAIR0,
  80         MISCREG_PRRR_MAIR0_NS,
  81         MISCREG_PRRR_MAIR0_S,
  82         MISCREG_NMRR_MAIR1,
  83         MISCREG_NMRR_MAIR1_NS,
  84         MISCREG_NMRR_MAIR1_S,
  85         MISCREG_PMXEVTYPER_PMCCFILTR,
  86         MISCREG_SCTLR_RST,
  87         MISCREG_SEV_MAILBOX,
  88
  89         // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
  90         MISCREG_DBGDIDR,
  91         MISCREG_DBGDSCRint,
  92         MISCREG_DBGDCCINT,
  93         MISCREG_DBGDTRTXint,
  94         MISCREG_DBGDTRRXint,
  95         MISCREG_DBGWFAR,
  96         MISCREG_DBGVCR,
  97         MISCREG_DBGDTRRXext,
  98         MISCREG_DBGDSCRext,
  99         MISCREG_DBGDTRTXext,
 100         MISCREG_DBGOSECCR,
 101         MISCREG_DBGBVR0,
 102         MISCREG_DBGBVR1,
 103         MISCREG_DBGBVR2,
 104         MISCREG_DBGBVR3,
 105         MISCREG_DBGBVR4,
 106         MISCREG_DBGBVR5,
 107         MISCREG_DBGBCR0,
 108         MISCREG_DBGBCR1,
 109         MISCREG_DBGBCR2,
 110         MISCREG_DBGBCR3,
 111         MISCREG_DBGBCR4,
 112         MISCREG_DBGBCR5,
 113         MISCREG_DBGWVR0,
 114         MISCREG_DBGWVR1,
 115         MISCREG_DBGWVR2,
 116         MISCREG_DBGWVR3,
 117         MISCREG_DBGWCR0,
 118         MISCREG_DBGWCR1,
 119         MISCREG_DBGWCR2,
 120         MISCREG_DBGWCR3,
 121         MISCREG_DBGDRAR,
 122         MISCREG_DBGBXVR4,
 123         MISCREG_DBGBXVR5,
 124         MISCREG_DBGOSLAR,
 125         MISCREG_DBGOSLSR,
 126         MISCREG_DBGOSDLR,
 127         MISCREG_DBGPRCR,
 128         MISCREG_DBGDSAR,
 129         MISCREG_DBGCLAIMSET,
 130         MISCREG_DBGCLAIMCLR,
 131         MISCREG_DBGAUTHSTATUS,
 132         MISCREG_DBGDEVID2,
 133         MISCREG_DBGDEVID1,
 134         MISCREG_DBGDEVID0,
 135         MISCREG_TEECR,  // not in ARM DDI 0487A.b+
 136         MISCREG_JIDR,
 137         MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
 138         MISCREG_JOSCR,
 139         MISCREG_JMCR,
 140
 141         // AArch32 CP15 registers (system control)
 142         MISCREG_MIDR,
 143         MISCREG_CTR,
 144         MISCREG_TCMTR,
 145         MISCREG_TLBTR,
 146         MISCREG_MPIDR,
 147         MISCREG_REVIDR,
 148         MISCREG_ID_PFR0,
 149         MISCREG_ID_PFR1,
 150         MISCREG_ID_DFR0,
 151         MISCREG_ID_AFR0,
 152         MISCREG_ID_MMFR0,
 153         MISCREG_ID_MMFR1,
 154         MISCREG_ID_MMFR2,
 155         MISCREG_ID_MMFR3,
 156         MISCREG_ID_ISAR0,
 157         MISCREG_ID_ISAR1,
 158         MISCREG_ID_ISAR2,
 159         MISCREG_ID_ISAR3,
 160         MISCREG_ID_ISAR4,
 161         MISCREG_ID_ISAR5,
 162         MISCREG_CCSIDR,
 163         MISCREG_CLIDR,
 164         MISCREG_AIDR,
 165         MISCREG_CSSELR,
 166         MISCREG_CSSELR_NS,
 167         MISCREG_CSSELR_S,
 168         MISCREG_VPIDR,
 169         MISCREG_VMPIDR,
 170         MISCREG_SCTLR,
 171         MISCREG_SCTLR_NS,
 172         MISCREG_SCTLR_S,
 173         MISCREG_ACTLR,
 174         MISCREG_ACTLR_NS,
 175         MISCREG_ACTLR_S,
 176         MISCREG_CPACR,
 177         MISCREG_SCR,
 178         MISCREG_SDER,
 179         MISCREG_NSACR,
 180         MISCREG_HSCTLR,
 181         MISCREG_HACTLR,
 182         MISCREG_HCR,
 183         MISCREG_HCR2,
 184         MISCREG_HDCR,
 185         MISCREG_HCPTR,
 186         MISCREG_HSTR,
 187         MISCREG_HACR,
 188         MISCREG_TTBR0,
 189         MISCREG_TTBR0_NS,
 190         MISCREG_TTBR0_S,
 191         MISCREG_TTBR1,
 192         MISCREG_TTBR1_NS,
 193         MISCREG_TTBR1_S,
 194         MISCREG_TTBCR,
 195         MISCREG_TTBCR_NS,
 196         MISCREG_TTBCR_S,
 197         MISCREG_HTCR,
 198         MISCREG_VTCR,
 199         MISCREG_DACR,
 200         MISCREG_DACR_NS,
 201         MISCREG_DACR_S,
 202         MISCREG_DFSR,
 203         MISCREG_DFSR_NS,
 204         MISCREG_DFSR_S,
 205         MISCREG_IFSR,
 206         MISCREG_IFSR_NS,
 207         MISCREG_IFSR_S,
 208         MISCREG_ADFSR,
 209         MISCREG_ADFSR_NS,
 210         MISCREG_ADFSR_S,
 211         MISCREG_AIFSR,
 212         MISCREG_AIFSR_NS,
 213         MISCREG_AIFSR_S,
 214         MISCREG_HADFSR,
 215         MISCREG_HAIFSR,
 216         MISCREG_HSR,
 217         MISCREG_DFAR,
 218         MISCREG_DFAR_NS,
 219         MISCREG_DFAR_S,
 220         MISCREG_IFAR,
 221         MISCREG_IFAR_NS,
 222         MISCREG_IFAR_S,
 223         MISCREG_HDFAR,
 224         MISCREG_HIFAR,
 225         MISCREG_HPFAR,
 226         MISCREG_ICIALLUIS,
 227         MISCREG_BPIALLIS,
 228         MISCREG_PAR,
 229         MISCREG_PAR_NS,
 230         MISCREG_PAR_S,
 231         MISCREG_ICIALLU,
 232         MISCREG_ICIMVAU,
 233         MISCREG_CP15ISB,
 234         MISCREG_BPIALL,
 235         MISCREG_BPIMVA,
 236         MISCREG_DCIMVAC,
 237         MISCREG_DCISW,
 238         MISCREG_ATS1CPR,
 239         MISCREG_ATS1CPW,
 240         MISCREG_ATS1CUR,
 241         MISCREG_ATS1CUW,
 242         MISCREG_ATS12NSOPR,
 243         MISCREG_ATS12NSOPW,
 244         MISCREG_ATS12NSOUR,
 245         MISCREG_ATS12NSOUW,
 246         MISCREG_DCCMVAC,
 247         MISCREG_DCCSW,
 248         MISCREG_CP15DSB,
 249         MISCREG_CP15DMB,
 250         MISCREG_DCCMVAU,
 251         MISCREG_DCCIMVAC,
 252         MISCREG_DCCISW,
 253         MISCREG_ATS1HR,
 254         MISCREG_ATS1HW,
 255         MISCREG_TLBIALLIS,
 256         MISCREG_TLBIMVAIS,
 257         MISCREG_TLBIASIDIS,
 258         MISCREG_TLBIMVAAIS,
 259         MISCREG_TLBIMVALIS,
 260         MISCREG_TLBIMVAALIS,
 261         MISCREG_ITLBIALL,
 262         MISCREG_ITLBIMVA,
 263         MISCREG_ITLBIASID,
 264         MISCREG_DTLBIALL,
 265         MISCREG_DTLBIMVA,
 266         MISCREG_DTLBIASID,
 267         MISCREG_TLBIALL,
 268         MISCREG_TLBIMVA,
 269         MISCREG_TLBIASID,
 270         MISCREG_TLBIMVAA,
 271         MISCREG_TLBIMVAL,
 272         MISCREG_TLBIMVAAL,
 273         MISCREG_TLBIIPAS2IS,
 274         MISCREG_TLBIIPAS2LIS,
 275         MISCREG_TLBIALLHIS,
 276         MISCREG_TLBIMVAHIS,
 277         MISCREG_TLBIALLNSNHIS,
 278         MISCREG_TLBIMVALHIS,
 279         MISCREG_TLBIIPAS2,
 280         MISCREG_TLBIIPAS2L,
 281         MISCREG_TLBIALLH,
 282         MISCREG_TLBIMVAH,
 283         MISCREG_TLBIALLNSNH,
 284         MISCREG_TLBIMVALH,
 285         MISCREG_PMCR,
 286         MISCREG_PMCNTENSET,
 287         MISCREG_PMCNTENCLR,
 288         MISCREG_PMOVSR,
 289         MISCREG_PMSWINC,
 290         MISCREG_PMSELR,
 291         MISCREG_PMCEID0,
 292         MISCREG_PMCEID1,
 293         MISCREG_PMCCNTR,
 294         MISCREG_PMXEVTYPER,
 295         MISCREG_PMCCFILTR,
 296         MISCREG_PMXEVCNTR,
 297         MISCREG_PMUSERENR,
 298         MISCREG_PMINTENSET,
 299         MISCREG_PMINTENCLR,
 300         MISCREG_PMOVSSET,
 301         MISCREG_L2CTLR,
 302         MISCREG_L2ECTLR,
 303         MISCREG_PRRR,
 304         MISCREG_PRRR_NS,
 305         MISCREG_PRRR_S,
 306         MISCREG_MAIR0,
 307         MISCREG_MAIR0_NS,
 308         MISCREG_MAIR0_S,
 309         MISCREG_NMRR,
 310         MISCREG_NMRR_NS,
 311         MISCREG_NMRR_S,
 312         MISCREG_MAIR1,
 313         MISCREG_MAIR1_NS,
 314         MISCREG_MAIR1_S,
 315         MISCREG_AMAIR0,
 316         MISCREG_AMAIR0_NS,
 317         MISCREG_AMAIR0_S,
 318         MISCREG_AMAIR1,
 319         MISCREG_AMAIR1_NS,
 320         MISCREG_AMAIR1_S,
 321         MISCREG_HMAIR0,
 322         MISCREG_HMAIR1,
 323         MISCREG_HAMAIR0,
 324         MISCREG_HAMAIR1,
 325         MISCREG_VBAR,
 326         MISCREG_VBAR_NS,
 327         MISCREG_VBAR_S,
 328         MISCREG_MVBAR,
 329         MISCREG_RMR,
 330         MISCREG_ISR,
 331         MISCREG_HVBAR,
 332         MISCREG_FCSEIDR,
 333         MISCREG_CONTEXTIDR,
 334         MISCREG_CONTEXTIDR_NS,
 335         MISCREG_CONTEXTIDR_S,
 336         MISCREG_TPIDRURW,
 337         MISCREG_TPIDRURW_NS,
 338         MISCREG_TPIDRURW_S,
 339         MISCREG_TPIDRURO,
 340         MISCREG_TPIDRURO_NS,
 341         MISCREG_TPIDRURO_S,
 342         MISCREG_TPIDRPRW,
 343         MISCREG_TPIDRPRW_NS,
 344         MISCREG_TPIDRPRW_S,
 345         MISCREG_HTPIDR,
 346         MISCREG_CNTFRQ,
 347         MISCREG_CNTKCTL,
 348         MISCREG_CNTP_TVAL,
 349         MISCREG_CNTP_TVAL_NS,
 350         MISCREG_CNTP_TVAL_S,
 351         MISCREG_CNTP_CTL,
 352         MISCREG_CNTP_CTL_NS,
 353         MISCREG_CNTP_CTL_S,
 354         MISCREG_CNTV_TVAL,
 355         MISCREG_CNTV_CTL,
 356         MISCREG_CNTHCTL,
 357         MISCREG_CNTHP_TVAL,
 358         MISCREG_CNTHP_CTL,
 359         MISCREG_IL1DATA0,
 360         MISCREG_IL1DATA1,
 361         MISCREG_IL1DATA2,
 362         MISCREG_IL1DATA3,
 363         MISCREG_DL1DATA0,
 364         MISCREG_DL1DATA1,
 365         MISCREG_DL1DATA2,
 366         MISCREG_DL1DATA3,
 367         MISCREG_DL1DATA4,
 368         MISCREG_RAMINDEX,
 369         MISCREG_L2ACTLR,
 370         MISCREG_CBAR,
 371         MISCREG_HTTBR,
 372         MISCREG_VTTBR,
 373         MISCREG_CNTPCT,
 374         MISCREG_CNTVCT,
 375         MISCREG_CNTP_CVAL,
 376         MISCREG_CNTP_CVAL_NS,
 377         MISCREG_CNTP_CVAL_S,
 378         MISCREG_CNTV_CVAL,
 379         MISCREG_CNTVOFF,
 380         MISCREG_CNTHP_CVAL,
 381         MISCREG_CPUMERRSR,
 382         MISCREG_L2MERRSR,
 383
 384         // AArch64 registers (Op0=2)
 385         MISCREG_MDCCINT_EL1,
 386         MISCREG_OSDTRRX_EL1,
 387         MISCREG_MDSCR_EL1,
 388         MISCREG_OSDTRTX_EL1,
 389         MISCREG_OSECCR_EL1,
 390         MISCREG_DBGBVR0_EL1,
 391         MISCREG_DBGBVR1_EL1,
 392         MISCREG_DBGBVR2_EL1,
 393         MISCREG_DBGBVR3_EL1,
 394         MISCREG_DBGBVR4_EL1,
 395         MISCREG_DBGBVR5_EL1,
 396         MISCREG_DBGBCR0_EL1,
 397         MISCREG_DBGBCR1_EL1,
 398         MISCREG_DBGBCR2_EL1,
 399         MISCREG_DBGBCR3_EL1,
 400         MISCREG_DBGBCR4_EL1,
 401         MISCREG_DBGBCR5_EL1,
 402         MISCREG_DBGWVR0_EL1,
 403         MISCREG_DBGWVR1_EL1,
 404         MISCREG_DBGWVR2_EL1,
 405         MISCREG_DBGWVR3_EL1,
 406         MISCREG_DBGWCR0_EL1,
 407         MISCREG_DBGWCR1_EL1,
 408         MISCREG_DBGWCR2_EL1,
 409         MISCREG_DBGWCR3_EL1,
 410         MISCREG_MDCCSR_EL0,
 411         MISCREG_MDDTR_EL0,
 412         MISCREG_MDDTRTX_EL0,
 413         MISCREG_MDDTRRX_EL0,
 414         MISCREG_DBGVCR32_EL2,
 415         MISCREG_MDRAR_EL1,
 416         MISCREG_OSLAR_EL1,
 417         MISCREG_OSLSR_EL1,
 418         MISCREG_OSDLR_EL1,
 419         MISCREG_DBGPRCR_EL1,
 420         MISCREG_DBGCLAIMSET_EL1,
 421         MISCREG_DBGCLAIMCLR_EL1,
 422         MISCREG_DBGAUTHSTATUS_EL1,
 423         MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
 424         MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
 425
 426         // AArch64 registers (Op0=1,3)
 427         MISCREG_MIDR_EL1,
 428         MISCREG_MPIDR_EL1,
 429         MISCREG_REVIDR_EL1,
 430         MISCREG_ID_PFR0_EL1,
 431         MISCREG_ID_PFR1_EL1,
 432         MISCREG_ID_DFR0_EL1,
 433         MISCREG_ID_AFR0_EL1,
 434         MISCREG_ID_MMFR0_EL1,
 435         MISCREG_ID_MMFR1_EL1,
 436         MISCREG_ID_MMFR2_EL1,
 437         MISCREG_ID_MMFR3_EL1,
 438         MISCREG_ID_ISAR0_EL1,
 439         MISCREG_ID_ISAR1_EL1,
 440         MISCREG_ID_ISAR2_EL1,
 441         MISCREG_ID_ISAR3_EL1,
 442         MISCREG_ID_ISAR4_EL1,
 443         MISCREG_ID_ISAR5_EL1,
 444         MISCREG_MVFR0_EL1,
 445         MISCREG_MVFR1_EL1,
 446         MISCREG_MVFR2_EL1,
 447         MISCREG_ID_AA64PFR0_EL1,
 448         MISCREG_ID_AA64PFR1_EL1,
 449         MISCREG_ID_AA64DFR0_EL1,
 450         MISCREG_ID_AA64DFR1_EL1,
 451         MISCREG_ID_AA64AFR0_EL1,
 452         MISCREG_ID_AA64AFR1_EL1,
 453         MISCREG_ID_AA64ISAR0_EL1,
 454         MISCREG_ID_AA64ISAR1_EL1,
 455         MISCREG_ID_AA64MMFR0_EL1,
 456         MISCREG_ID_AA64MMFR1_EL1,
 457         MISCREG_CCSIDR_EL1,
 458         MISCREG_CLIDR_EL1,
 459         MISCREG_AIDR_EL1,
 460         MISCREG_CSSELR_EL1,
 461         MISCREG_CTR_EL0,
 462         MISCREG_DCZID_EL0,
 463         MISCREG_VPIDR_EL2,
 464         MISCREG_VMPIDR_EL2,
 465         MISCREG_SCTLR_EL1,
 466         MISCREG_ACTLR_EL1,
 467         MISCREG_CPACR_EL1,
 468         MISCREG_SCTLR_EL2,
 469         MISCREG_ACTLR_EL2,
 470         MISCREG_HCR_EL2,
 471         MISCREG_MDCR_EL2,
 472         MISCREG_CPTR_EL2,
 473         MISCREG_HSTR_EL2,
 474         MISCREG_HACR_EL2,
 475         MISCREG_SCTLR_EL3,
 476         MISCREG_ACTLR_EL3,
 477         MISCREG_SCR_EL3,
 478         MISCREG_SDER32_EL3,
 479         MISCREG_CPTR_EL3,
 480         MISCREG_MDCR_EL3,
 481         MISCREG_TTBR0_EL1,
 482         MISCREG_TTBR1_EL1,
 483         MISCREG_TCR_EL1,
 484         MISCREG_TTBR0_EL2,
 485         MISCREG_TCR_EL2,
 486         MISCREG_VTTBR_EL2,
 487         MISCREG_VTCR_EL2,
 488         MISCREG_TTBR0_EL3,
 489         MISCREG_TCR_EL3,
 490         MISCREG_DACR32_EL2,
 491         MISCREG_SPSR_EL1,
 492         MISCREG_ELR_EL1,
 493         MISCREG_SP_EL0,
 494         MISCREG_SPSEL,
 495         MISCREG_CURRENTEL,
 496         MISCREG_NZCV,
 497         MISCREG_DAIF,
 498         MISCREG_FPCR,
 499         MISCREG_FPSR,
 500         MISCREG_DSPSR_EL0,
 501         MISCREG_DLR_EL0,
 502         MISCREG_SPSR_EL2,
 503         MISCREG_ELR_EL2,
 504         MISCREG_SP_EL1,
 505         MISCREG_SPSR_IRQ_AA64,
 506         MISCREG_SPSR_ABT_AA64,
 507         MISCREG_SPSR_UND_AA64,
 508         MISCREG_SPSR_FIQ_AA64,
 509         MISCREG_SPSR_EL3,
 510         MISCREG_ELR_EL3,
 511         MISCREG_SP_EL2,
 512         MISCREG_AFSR0_EL1,
 513         MISCREG_AFSR1_EL1,
 514         MISCREG_ESR_EL1,
 515         MISCREG_IFSR32_EL2,
 516         MISCREG_AFSR0_EL2,
 517         MISCREG_AFSR1_EL2,
 518         MISCREG_ESR_EL2,
 519         MISCREG_FPEXC32_EL2,
 520         MISCREG_AFSR0_EL3,
 521         MISCREG_AFSR1_EL3,
 522         MISCREG_ESR_EL3,
 523         MISCREG_FAR_EL1,
 524         MISCREG_FAR_EL2,
 525         MISCREG_HPFAR_EL2,
 526         MISCREG_FAR_EL3,
 527         MISCREG_IC_IALLUIS,
 528         MISCREG_PAR_EL1,
 529         MISCREG_IC_IALLU,
 530         MISCREG_DC_IVAC_Xt,
 531         MISCREG_DC_ISW_Xt,
 532         MISCREG_AT_S1E1R_Xt,
 533         MISCREG_AT_S1E1W_Xt,
 534         MISCREG_AT_S1E0R_Xt,
 535         MISCREG_AT_S1E0W_Xt,
 536         MISCREG_DC_CSW_Xt,
 537         MISCREG_DC_CISW_Xt,
 538         MISCREG_DC_ZVA_Xt,
 539         MISCREG_IC_IVAU_Xt,
 540         MISCREG_DC_CVAC_Xt,
 541         MISCREG_DC_CVAU_Xt,
 542         MISCREG_DC_CIVAC_Xt,
 543         MISCREG_AT_S1E2R_Xt,
 544         MISCREG_AT_S1E2W_Xt,
 545         MISCREG_AT_S12E1R_Xt,
 546         MISCREG_AT_S12E1W_Xt,
 547         MISCREG_AT_S12E0R_Xt,
 548         MISCREG_AT_S12E0W_Xt,
 549         MISCREG_AT_S1E3R_Xt,
 550         MISCREG_AT_S1E3W_Xt,
 551         MISCREG_TLBI_VMALLE1IS,
 552         MISCREG_TLBI_VAE1IS_Xt,
 553         MISCREG_TLBI_ASIDE1IS_Xt,
 554         MISCREG_TLBI_VAAE1IS_Xt,
 555         MISCREG_TLBI_VALE1IS_Xt,
 556         MISCREG_TLBI_VAALE1IS_Xt,
 557         MISCREG_TLBI_VMALLE1,
 558         MISCREG_TLBI_VAE1_Xt,
 559         MISCREG_TLBI_ASIDE1_Xt,
 560         MISCREG_TLBI_VAAE1_Xt,
 561         MISCREG_TLBI_VALE1_Xt,
 562         MISCREG_TLBI_VAALE1_Xt,
 563         MISCREG_TLBI_IPAS2E1IS_Xt,
 564         MISCREG_TLBI_IPAS2LE1IS_Xt,
 565         MISCREG_TLBI_ALLE2IS,
 566         MISCREG_TLBI_VAE2IS_Xt,
 567         MISCREG_TLBI_ALLE1IS,
 568         MISCREG_TLBI_VALE2IS_Xt,
 569         MISCREG_TLBI_VMALLS12E1IS,
 570         MISCREG_TLBI_IPAS2E1_Xt,
 571         MISCREG_TLBI_IPAS2LE1_Xt,
 572         MISCREG_TLBI_ALLE2,
 573         MISCREG_TLBI_VAE2_Xt,
 574         MISCREG_TLBI_ALLE1,
 575         MISCREG_TLBI_VALE2_Xt,
 576         MISCREG_TLBI_VMALLS12E1,
 577         MISCREG_TLBI_ALLE3IS,
 578         MISCREG_TLBI_VAE3IS_Xt,
 579         MISCREG_TLBI_VALE3IS_Xt,
 580         MISCREG_TLBI_ALLE3,
 581         MISCREG_TLBI_VAE3_Xt,
 582         MISCREG_TLBI_VALE3_Xt,
 583         MISCREG_PMINTENSET_EL1,
 584         MISCREG_PMINTENCLR_EL1,
 585         MISCREG_PMCR_EL0,
 586         MISCREG_PMCNTENSET_EL0,
 587         MISCREG_PMCNTENCLR_EL0,
 588         MISCREG_PMOVSCLR_EL0,
 589         MISCREG_PMSWINC_EL0,
 590         MISCREG_PMSELR_EL0,
 591         MISCREG_PMCEID0_EL0,
 592         MISCREG_PMCEID1_EL0,
 593         MISCREG_PMCCNTR_EL0,
 594         MISCREG_PMXEVTYPER_EL0,
 595         MISCREG_PMCCFILTR_EL0,
 596         MISCREG_PMXEVCNTR_EL0,
 597         MISCREG_PMUSERENR_EL0,
 598         MISCREG_PMOVSSET_EL0,
 599         MISCREG_MAIR_EL1,
 600         MISCREG_AMAIR_EL1,
 601         MISCREG_MAIR_EL2,
 602         MISCREG_AMAIR_EL2,
 603         MISCREG_MAIR_EL3,
 604         MISCREG_AMAIR_EL3,
 605         MISCREG_L2CTLR_EL1,
 606         MISCREG_L2ECTLR_EL1,
 607         MISCREG_VBAR_EL1,
 608         MISCREG_RVBAR_EL1,
 609         MISCREG_ISR_EL1,
 610         MISCREG_VBAR_EL2,
 611         MISCREG_RVBAR_EL2,
 612         MISCREG_VBAR_EL3,
 613         MISCREG_RVBAR_EL3,
 614         MISCREG_RMR_EL3,
 615         MISCREG_CONTEXTIDR_EL1,
 616         MISCREG_TPIDR_EL1,
 617         MISCREG_TPIDR_EL0,
 618         MISCREG_TPIDRRO_EL0,
 619         MISCREG_TPIDR_EL2,
 620         MISCREG_TPIDR_EL3,
 621         MISCREG_CNTKCTL_EL1,
 622         MISCREG_CNTFRQ_EL0,
 623         MISCREG_CNTPCT_EL0,
 624         MISCREG_CNTVCT_EL0,
 625         MISCREG_CNTP_TVAL_EL0,
 626         MISCREG_CNTP_CTL_EL0,
 627         MISCREG_CNTP_CVAL_EL0,
 628         MISCREG_CNTV_TVAL_EL0,
 629         MISCREG_CNTV_CTL_EL0,
 630         MISCREG_CNTV_CVAL_EL0,
 631         MISCREG_PMEVCNTR0_EL0,
 632         MISCREG_PMEVCNTR1_EL0,
 633         MISCREG_PMEVCNTR2_EL0,
 634         MISCREG_PMEVCNTR3_EL0,
 635         MISCREG_PMEVCNTR4_EL0,
 636         MISCREG_PMEVCNTR5_EL0,
 637         MISCREG_PMEVTYPER0_EL0,
 638         MISCREG_PMEVTYPER1_EL0,
 639         MISCREG_PMEVTYPER2_EL0,
 640         MISCREG_PMEVTYPER3_EL0,
 641         MISCREG_PMEVTYPER4_EL0,
 642         MISCREG_PMEVTYPER5_EL0,
 643         MISCREG_CNTVOFF_EL2,
 644         MISCREG_CNTHCTL_EL2,
 645         MISCREG_CNTHP_TVAL_EL2,
 646         MISCREG_CNTHP_CTL_EL2,
 647         MISCREG_CNTHP_CVAL_EL2,
 648         MISCREG_CNTPS_TVAL_EL1,
 649         MISCREG_CNTPS_CTL_EL1,
 650         MISCREG_CNTPS_CVAL_EL1,
 651         MISCREG_IL1DATA0_EL1,
 652         MISCREG_IL1DATA1_EL1,
 653         MISCREG_IL1DATA2_EL1,
 654         MISCREG_IL1DATA3_EL1,
 655         MISCREG_DL1DATA0_EL1,
 656         MISCREG_DL1DATA1_EL1,
 657         MISCREG_DL1DATA2_EL1,
 658         MISCREG_DL1DATA3_EL1,
 659         MISCREG_DL1DATA4_EL1,
 660         MISCREG_L2ACTLR_EL1,
 661         MISCREG_CPUACTLR_EL1,
 662         MISCREG_CPUECTLR_EL1,
 663         MISCREG_CPUMERRSR_EL1,
 664         MISCREG_L2MERRSR_EL1,
 665         MISCREG_CBAR_EL1,
 666         MISCREG_CONTEXTIDR_EL2,
 667
 668         // Introduced in ARMv8.1
 669         MISCREG_TTBR1_EL2,
 670         MISCREG_CNTHV_CTL_EL2,
 671         MISCREG_CNTHV_CVAL_EL2,
 672         MISCREG_CNTHV_TVAL_EL2,
 673
 674         MISCREG_ID_AA64MMFR2_EL1,
 675
 676         //PAuth Key Regsiters
 677         MISCREG_APDAKeyHi_EL1,
 678         MISCREG_APDAKeyLo_EL1,
 679         MISCREG_APDBKeyHi_EL1,
 680         MISCREG_APDBKeyLo_EL1,
 681         MISCREG_APGAKeyHi_EL1,
 682         MISCREG_APGAKeyLo_EL1,
 683         MISCREG_APIAKeyHi_EL1,
 684         MISCREG_APIAKeyLo_EL1,
 685         MISCREG_APIBKeyHi_EL1,
 686         MISCREG_APIBKeyLo_EL1,
 687
 688         // GICv3, CPU interface
 689         MISCREG_ICC_PMR_EL1,
 690         MISCREG_ICC_IAR0_EL1,
 691         MISCREG_ICC_EOIR0_EL1,
 692         MISCREG_ICC_HPPIR0_EL1,
 693         MISCREG_ICC_BPR0_EL1,
 694         MISCREG_ICC_AP0R0_EL1,
 695         MISCREG_ICC_AP0R1_EL1,
 696         MISCREG_ICC_AP0R2_EL1,
 697         MISCREG_ICC_AP0R3_EL1,
 698         MISCREG_ICC_AP1R0_EL1,
 699         MISCREG_ICC_AP1R0_EL1_NS,
 700         MISCREG_ICC_AP1R0_EL1_S,
 701         MISCREG_ICC_AP1R1_EL1,
 702         MISCREG_ICC_AP1R1_EL1_NS,
 703         MISCREG_ICC_AP1R1_EL1_S,
 704         MISCREG_ICC_AP1R2_EL1,
 705         MISCREG_ICC_AP1R2_EL1_NS,
 706         MISCREG_ICC_AP1R2_EL1_S,
 707         MISCREG_ICC_AP1R3_EL1,
 708         MISCREG_ICC_AP1R3_EL1_NS,
 709         MISCREG_ICC_AP1R3_EL1_S,
 710         MISCREG_ICC_DIR_EL1,
 711         MISCREG_ICC_RPR_EL1,
 712         MISCREG_ICC_SGI1R_EL1,
 713         MISCREG_ICC_ASGI1R_EL1,
 714         MISCREG_ICC_SGI0R_EL1,
 715         MISCREG_ICC_IAR1_EL1,
 716         MISCREG_ICC_EOIR1_EL1,
 717         MISCREG_ICC_HPPIR1_EL1,
 718         MISCREG_ICC_BPR1_EL1,
 719         MISCREG_ICC_BPR1_EL1_NS,
 720         MISCREG_ICC_BPR1_EL1_S,
 721         MISCREG_ICC_CTLR_EL1,
 722         MISCREG_ICC_CTLR_EL1_NS,
 723         MISCREG_ICC_CTLR_EL1_S,
 724         MISCREG_ICC_SRE_EL1,
 725         MISCREG_ICC_SRE_EL1_NS,
 726         MISCREG_ICC_SRE_EL1_S,
 727         MISCREG_ICC_IGRPEN0_EL1,
 728         MISCREG_ICC_IGRPEN1_EL1,
 729         MISCREG_ICC_IGRPEN1_EL1_NS,
 730         MISCREG_ICC_IGRPEN1_EL1_S,
 731         MISCREG_ICC_SRE_EL2,
 732         MISCREG_ICC_CTLR_EL3,
 733         MISCREG_ICC_SRE_EL3,
 734         MISCREG_ICC_IGRPEN1_EL3,
 735
 736         // GICv3, CPU interface, virtualization
 737         MISCREG_ICH_AP0R0_EL2,
 738         MISCREG_ICH_AP0R1_EL2,
 739         MISCREG_ICH_AP0R2_EL2,
 740         MISCREG_ICH_AP0R3_EL2,
 741         MISCREG_ICH_AP1R0_EL2,
 742         MISCREG_ICH_AP1R1_EL2,
 743         MISCREG_ICH_AP1R2_EL2,
 744         MISCREG_ICH_AP1R3_EL2,
 745         MISCREG_ICH_HCR_EL2,
 746         MISCREG_ICH_VTR_EL2,
 747         MISCREG_ICH_MISR_EL2,
 748         MISCREG_ICH_EISR_EL2,
 749         MISCREG_ICH_ELRSR_EL2,
 750         MISCREG_ICH_VMCR_EL2,
 751         MISCREG_ICH_LR0_EL2,
 752         MISCREG_ICH_LR1_EL2,
 753         MISCREG_ICH_LR2_EL2,
 754         MISCREG_ICH_LR3_EL2,
 755         MISCREG_ICH_LR4_EL2,
 756         MISCREG_ICH_LR5_EL2,
 757         MISCREG_ICH_LR6_EL2,
 758         MISCREG_ICH_LR7_EL2,
 759         MISCREG_ICH_LR8_EL2,
 760         MISCREG_ICH_LR9_EL2,
 761         MISCREG_ICH_LR10_EL2,
 762         MISCREG_ICH_LR11_EL2,
 763         MISCREG_ICH_LR12_EL2,
 764         MISCREG_ICH_LR13_EL2,
 765         MISCREG_ICH_LR14_EL2,
 766         MISCREG_ICH_LR15_EL2,
 767
 768         MISCREG_ICV_PMR_EL1,
 769         MISCREG_ICV_IAR0_EL1,
 770         MISCREG_ICV_EOIR0_EL1,
 771         MISCREG_ICV_HPPIR0_EL1,
 772         MISCREG_ICV_BPR0_EL1,
 773         MISCREG_ICV_AP0R0_EL1,
 774         MISCREG_ICV_AP0R1_EL1,
 775         MISCREG_ICV_AP0R2_EL1,
 776         MISCREG_ICV_AP0R3_EL1,
 777         MISCREG_ICV_AP1R0_EL1,
 778         MISCREG_ICV_AP1R0_EL1_NS,
 779         MISCREG_ICV_AP1R0_EL1_S,
 780         MISCREG_ICV_AP1R1_EL1,
 781         MISCREG_ICV_AP1R1_EL1_NS,
 782         MISCREG_ICV_AP1R1_EL1_S,
 783         MISCREG_ICV_AP1R2_EL1,
 784         MISCREG_ICV_AP1R2_EL1_NS,
 785         MISCREG_ICV_AP1R2_EL1_S,
 786         MISCREG_ICV_AP1R3_EL1,
 787         MISCREG_ICV_AP1R3_EL1_NS,
 788         MISCREG_ICV_AP1R3_EL1_S,
 789         MISCREG_ICV_DIR_EL1,
 790         MISCREG_ICV_RPR_EL1,
 791         MISCREG_ICV_SGI1R_EL1,
 792         MISCREG_ICV_ASGI1R_EL1,
 793         MISCREG_ICV_SGI0R_EL1,
 794         MISCREG_ICV_IAR1_EL1,
 795         MISCREG_ICV_EOIR1_EL1,
 796         MISCREG_ICV_HPPIR1_EL1,
 797         MISCREG_ICV_BPR1_EL1,
 798         MISCREG_ICV_BPR1_EL1_NS,
 799         MISCREG_ICV_BPR1_EL1_S,
 800         MISCREG_ICV_CTLR_EL1,
 801         MISCREG_ICV_CTLR_EL1_NS,
 802         MISCREG_ICV_CTLR_EL1_S,
 803         MISCREG_ICV_SRE_EL1,
 804         MISCREG_ICV_SRE_EL1_NS,
 805         MISCREG_ICV_SRE_EL1_S,
 806         MISCREG_ICV_IGRPEN0_EL1,
 807         MISCREG_ICV_IGRPEN1_EL1,
 808         MISCREG_ICV_IGRPEN1_EL1_NS,
 809         MISCREG_ICV_IGRPEN1_EL1_S,
 810
 811         MISCREG_ICC_AP0R0,
 812         MISCREG_ICC_AP0R1,
 813         MISCREG_ICC_AP0R2,
 814         MISCREG_ICC_AP0R3,
 815         MISCREG_ICC_AP1R0,
 816         MISCREG_ICC_AP1R0_NS,
 817         MISCREG_ICC_AP1R0_S,
 818         MISCREG_ICC_AP1R1,
 819         MISCREG_ICC_AP1R1_NS,
 820         MISCREG_ICC_AP1R1_S,
 821         MISCREG_ICC_AP1R2,
 822         MISCREG_ICC_AP1R2_NS,
 823         MISCREG_ICC_AP1R2_S,
 824         MISCREG_ICC_AP1R3,
 825         MISCREG_ICC_AP1R3_NS,
 826         MISCREG_ICC_AP1R3_S,
 827         MISCREG_ICC_ASGI1R,
 828         MISCREG_ICC_BPR0,
 829         MISCREG_ICC_BPR1,
 830         MISCREG_ICC_BPR1_NS,
 831         MISCREG_ICC_BPR1_S,
 832         MISCREG_ICC_CTLR,
 833         MISCREG_ICC_CTLR_NS,
 834         MISCREG_ICC_CTLR_S,
 835         MISCREG_ICC_DIR,
 836         MISCREG_ICC_EOIR0,
 837         MISCREG_ICC_EOIR1,
 838         MISCREG_ICC_HPPIR0,
 839         MISCREG_ICC_HPPIR1,
 840         MISCREG_ICC_HSRE,
 841         MISCREG_ICC_IAR0,
 842         MISCREG_ICC_IAR1,
 843         MISCREG_ICC_IGRPEN0,
 844         MISCREG_ICC_IGRPEN1,
 845         MISCREG_ICC_IGRPEN1_NS,
 846         MISCREG_ICC_IGRPEN1_S,
 847         MISCREG_ICC_MCTLR,
 848         MISCREG_ICC_MGRPEN1,
 849         MISCREG_ICC_MSRE,
 850         MISCREG_ICC_PMR,
 851         MISCREG_ICC_RPR,
 852         MISCREG_ICC_SGI0R,
 853         MISCREG_ICC_SGI1R,
 854         MISCREG_ICC_SRE,
 855         MISCREG_ICC_SRE_NS,
 856         MISCREG_ICC_SRE_S,
 857
 858         MISCREG_ICH_AP0R0,
 859         MISCREG_ICH_AP0R1,
 860         MISCREG_ICH_AP0R2,
 861         MISCREG_ICH_AP0R3,
 862         MISCREG_ICH_AP1R0,
 863         MISCREG_ICH_AP1R1,
 864         MISCREG_ICH_AP1R2,
 865         MISCREG_ICH_AP1R3,
 866         MISCREG_ICH_HCR,
 867         MISCREG_ICH_VTR,
 868         MISCREG_ICH_MISR,
 869         MISCREG_ICH_EISR,
 870         MISCREG_ICH_ELRSR,
 871         MISCREG_ICH_VMCR,
 872         MISCREG_ICH_LR0,
 873         MISCREG_ICH_LR1,
 874         MISCREG_ICH_LR2,
 875         MISCREG_ICH_LR3,
 876         MISCREG_ICH_LR4,
 877         MISCREG_ICH_LR5,
 878         MISCREG_ICH_LR6,
 879         MISCREG_ICH_LR7,
 880         MISCREG_ICH_LR8,
 881         MISCREG_ICH_LR9,
 882         MISCREG_ICH_LR10,
 883         MISCREG_ICH_LR11,
 884         MISCREG_ICH_LR12,
 885         MISCREG_ICH_LR13,
 886         MISCREG_ICH_LR14,
 887         MISCREG_ICH_LR15,
 888         MISCREG_ICH_LRC0,
 889         MISCREG_ICH_LRC1,
 890         MISCREG_ICH_LRC2,
 891         MISCREG_ICH_LRC3,
 892         MISCREG_ICH_LRC4,
 893         MISCREG_ICH_LRC5,
 894         MISCREG_ICH_LRC6,
 895         MISCREG_ICH_LRC7,
 896         MISCREG_ICH_LRC8,
 897         MISCREG_ICH_LRC9,
 898         MISCREG_ICH_LRC10,
 899         MISCREG_ICH_LRC11,
 900         MISCREG_ICH_LRC12,
 901         MISCREG_ICH_LRC13,
 902         MISCREG_ICH_LRC14,
 903         MISCREG_ICH_LRC15,
 904
 905         // SVE
 906         MISCREG_ID_AA64ZFR0_EL1,
 907         MISCREG_ZCR_EL3,
 908         MISCREG_ZCR_EL2,
 909         MISCREG_ZCR_EL12,
 910         MISCREG_ZCR_EL1,
 911
 912         // NUM_PHYS_MISCREGS specifies the number of actual physical
 913         // registers, not considering the following pseudo-registers
 914         // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
 915         // Checkpointing should use this physical index when
 916         // saving/restoring register values.
 917         NUM_PHYS_MISCREGS,
 918
 919         // Dummy registers
 920         MISCREG_NOP,
 921         MISCREG_RAZ,
 922         MISCREG_CP14_UNIMPL,
 923         MISCREG_CP15_UNIMPL,
 924         MISCREG_UNKNOWN,
 925
 926         // Implementation defined register: this represent
 927         // a pool of unimplemented registers whose access can throw
 928         // either UNDEFINED or hypervisor trap exception.
 929         MISCREG_IMPDEF_UNIMPL,
 930
 931         // RAS extension (unimplemented)
 932         MISCREG_ERRIDR_EL1,
 933         MISCREG_ERRSELR_EL1,
 934         MISCREG_ERXFR_EL1,
 935         MISCREG_ERXCTLR_EL1,
 936         MISCREG_ERXSTATUS_EL1,
 937         MISCREG_ERXADDR_EL1,
 938         MISCREG_ERXMISC0_EL1,
 939         MISCREG_ERXMISC1_EL1,
 940         MISCREG_DISR_EL1,
 941         MISCREG_VSESR_EL2,
 942         MISCREG_VDISR_EL2,
 943
 944         // PSTATE
 945         MISCREG_PAN,
 946
 947         // Total number of Misc Registers: Physical + Dummy
 948         NUM_MISCREGS
 949     };
 950
 951     enum MiscRegInfo {
 952         MISCREG_IMPLEMENTED,
 953         MISCREG_UNVERIFIABLE,   // Does the value change on every read (e.g. a
 954                                 // arch generic counter)
 955         MISCREG_WARN_NOT_FAIL,  // If MISCREG_IMPLEMENTED is deasserted, it
 956                                 // tells whether the instruction should raise a
 957                                 // warning or fail
 958         MISCREG_MUTEX,  // True if the register corresponds to a pair of
 959                         // mutually exclusive registers
 960         MISCREG_BANKED,  // True if the register is banked between the two
 961                          // security states, and this is the parent node of the
 962                          // two banked registers
 963         MISCREG_BANKED64, // True if the register is banked between the two
 964                           // security states, and this is the parent node of
 965                           // the two banked registers. Used in AA64 only.
 966         MISCREG_BANKED_CHILD, // The entry is one of the child registers that
 967                               // forms a banked set of regs (along with the
 968                               // other child regs)
 969
 970         // Access permissions
 971         // User mode
 972         MISCREG_USR_NS_RD,
 973         MISCREG_USR_NS_WR,
 974         MISCREG_USR_S_RD,
 975         MISCREG_USR_S_WR,
 976         // Privileged modes other than hypervisor or monitor
 977         MISCREG_PRI_NS_RD,
 978         MISCREG_PRI_NS_WR,
 979         MISCREG_PRI_S_RD,
 980         MISCREG_PRI_S_WR,
 981         // Hypervisor mode
 982         MISCREG_HYP_RD,
 983         MISCREG_HYP_WR,
 984         // Hypervisor mode, HCR_EL2.E2H == 1
 985         MISCREG_HYP_E2H_RD,
 986         MISCREG_HYP_E2H_WR,
 987         // Monitor mode, SCR.NS == 0
 988         MISCREG_MON_NS0_RD,
 989         MISCREG_MON_NS0_WR,
 990         // Monitor mode, SCR.NS == 1
 991         MISCREG_MON_NS1_RD,
 992         MISCREG_MON_NS1_WR,
 993         // Monitor mode, HCR_EL2.E2H == 1
 994         MISCREG_MON_E2H_RD,
 995         MISCREG_MON_E2H_WR,
 996
 997         NUM_MISCREG_INFOS
 998     };
 999
1000     extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
1001
1002     // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
1003     MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
1004                                unsigned crm, unsigned opc2);
1005     MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
1006                                      unsigned crn, unsigned crm,
1007                                      unsigned op2);
1008     // Whether a particular AArch64 system register is -always- read only.
1009     bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
1010
1011     // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
1012     MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
1013                                unsigned crm, unsigned opc2);
1014
1015     // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
1016     MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
1017
1018
1019     const char * const miscRegName[] = {
1020         "cpsr",
1021         "spsr",
1022         "spsr_fiq",
1023         "spsr_irq",
1024         "spsr_svc",
1025         "spsr_mon",
1026         "spsr_abt",
1027         "spsr_hyp",
1028         "spsr_und",
1029         "elr_hyp",
1030         "fpsid",
1031         "fpscr",
1032         "mvfr1",
1033         "mvfr0",
1034         "fpexc",
1035
1036         // Helper registers
1037         "cpsr_mode",
1038         "cpsr_q",
1039         "fpscr_exc",
1040         "fpscr_qc",
1041         "lockaddr",
1042         "lockflag",
1043         "prrr_mair0",
1044         "prrr_mair0_ns",
1045         "prrr_mair0_s",
1046         "nmrr_mair1",
1047         "nmrr_mair1_ns",
1048         "nmrr_mair1_s",
1049         "pmxevtyper_pmccfiltr",
1050         "sctlr_rst",
1051         "sev_mailbox",
1052
1053         // AArch32 CP14 registers
1054         "dbgdidr",
1055         "dbgdscrint",
1056         "dbgdccint",
1057         "dbgdtrtxint",
1058         "dbgdtrrxint",
1059         "dbgwfar",
1060         "dbgvcr",
1061         "dbgdtrrxext",
1062         "dbgdscrext",
1063         "dbgdtrtxext",
1064         "dbgoseccr",
1065         "dbgbvr0",
1066         "dbgbvr1",
1067         "dbgbvr2",
1068         "dbgbvr3",
1069         "dbgbvr4",
1070         "dbgbvr5",
1071         "dbgbcr0",
1072         "dbgbcr1",
1073         "dbgbcr2",
1074         "dbgbcr3",
1075         "dbgbcr4",
1076         "dbgbcr5",
1077         "dbgwvr0",
1078         "dbgwvr1",
1079         "dbgwvr2",
1080         "dbgwvr3",
1081         "dbgwcr0",
1082         "dbgwcr1",
1083         "dbgwcr2",
1084         "dbgwcr3",
1085         "dbgdrar",
1086         "dbgbxvr4",
1087         "dbgbxvr5",
1088         "dbgoslar",
1089         "dbgoslsr",
1090         "dbgosdlr",
1091         "dbgprcr",
1092         "dbgdsar",
1093         "dbgclaimset",
1094         "dbgclaimclr",
1095         "dbgauthstatus",
1096         "dbgdevid2",
1097         "dbgdevid1",
1098         "dbgdevid0",
1099         "teecr",
1100         "jidr",
1101         "teehbr",
1102         "joscr",
1103         "jmcr",
1104
1105         // AArch32 CP15 registers
1106         "midr",
1107         "ctr",
1108         "tcmtr",
1109         "tlbtr",
1110         "mpidr",
1111         "revidr",
1112         "id_pfr0",
1113         "id_pfr1",
1114         "id_dfr0",
1115         "id_afr0",
1116         "id_mmfr0",
1117         "id_mmfr1",
1118         "id_mmfr2",
1119         "id_mmfr3",
1120         "id_isar0",
1121         "id_isar1",
1122         "id_isar2",
1123         "id_isar3",
1124         "id_isar4",
1125         "id_isar5",
1126         "ccsidr",
1127         "clidr",
1128         "aidr",
1129         "csselr",
1130         "csselr_ns",
1131         "csselr_s",
1132         "vpidr",
1133         "vmpidr",
1134         "sctlr",
1135         "sctlr_ns",
1136         "sctlr_s",
1137         "actlr",
1138         "actlr_ns",
1139         "actlr_s",
1140         "cpacr",
1141         "scr",
1142         "sder",
1143         "nsacr",
1144         "hsctlr",
1145         "hactlr",
1146         "hcr",
1147         "hcr2",
1148         "hdcr",
1149         "hcptr",
1150         "hstr",
1151         "hacr",
1152         "ttbr0",
1153         "ttbr0_ns",
1154         "ttbr0_s",
1155         "ttbr1",
1156         "ttbr1_ns",
1157         "ttbr1_s",
1158         "ttbcr",
1159         "ttbcr_ns",
1160         "ttbcr_s",
1161         "htcr",
1162         "vtcr",
1163         "dacr",
1164         "dacr_ns",
1165         "dacr_s",
1166         "dfsr",
1167         "dfsr_ns",
1168         "dfsr_s",
1169         "ifsr",
1170         "ifsr_ns",
1171         "ifsr_s",
1172         "adfsr",
1173         "adfsr_ns",
1174         "adfsr_s",
1175         "aifsr",
1176         "aifsr_ns",
1177         "aifsr_s",
1178         "hadfsr",
1179         "haifsr",
1180         "hsr",
1181         "dfar",
1182         "dfar_ns",
1183         "dfar_s",
1184         "ifar",
1185         "ifar_ns",
1186         "ifar_s",
1187         "hdfar",
1188         "hifar",
1189         "hpfar",
1190         "icialluis",
1191         "bpiallis",
1192         "par",
1193         "par_ns",
1194         "par_s",
1195         "iciallu",
1196         "icimvau",
1197         "cp15isb",
1198         "bpiall",
1199         "bpimva",
1200         "dcimvac",
1201         "dcisw",
1202         "ats1cpr",
1203         "ats1cpw",
1204         "ats1cur",
1205         "ats1cuw",
1206         "ats12nsopr",
1207         "ats12nsopw",
1208         "ats12nsour",
1209         "ats12nsouw",
1210         "dccmvac",
1211         "dccsw",
1212         "cp15dsb",
1213         "cp15dmb",
1214         "dccmvau",
1215         "dccimvac",
1216         "dccisw",
1217         "ats1hr",
1218         "ats1hw",
1219         "tlbiallis",
1220         "tlbimvais",
1221         "tlbiasidis",
1222         "tlbimvaais",
1223         "tlbimvalis",
1224         "tlbimvaalis",
1225         "itlbiall",
1226         "itlbimva",
1227         "itlbiasid",
1228         "dtlbiall",
1229         "dtlbimva",
1230         "dtlbiasid",
1231         "tlbiall",
1232         "tlbimva",
1233         "tlbiasid",
1234         "tlbimvaa",
1235         "tlbimval",
1236         "tlbimvaal",
1237         "tlbiipas2is",
1238         "tlbiipas2lis",
1239         "tlbiallhis",
1240         "tlbimvahis",
1241         "tlbiallnsnhis",
1242         "tlbimvalhis",
1243         "tlbiipas2",
1244         "tlbiipas2l",
1245         "tlbiallh",
1246         "tlbimvah",
1247         "tlbiallnsnh",
1248         "tlbimvalh",
1249         "pmcr",
1250         "pmcntenset",
1251         "pmcntenclr",
1252         "pmovsr",
1253         "pmswinc",
1254         "pmselr",
1255         "pmceid0",
1256         "pmceid1",
1257         "pmccntr",
1258         "pmxevtyper",
1259         "pmccfiltr",
1260         "pmxevcntr",
1261         "pmuserenr",
1262         "pmintenset",
1263         "pmintenclr",
1264         "pmovsset",
1265         "l2ctlr",
1266         "l2ectlr",
1267         "prrr",
1268         "prrr_ns",
1269         "prrr_s",
1270         "mair0",
1271         "mair0_ns",
1272         "mair0_s",
1273         "nmrr",
1274         "nmrr_ns",
1275         "nmrr_s",
1276         "mair1",
1277         "mair1_ns",
1278         "mair1_s",
1279         "amair0",
1280         "amair0_ns",
1281         "amair0_s",
1282         "amair1",
1283         "amair1_ns",
1284         "amair1_s",
1285         "hmair0",
1286         "hmair1",
1287         "hamair0",
1288         "hamair1",
1289         "vbar",
1290         "vbar_ns",
1291         "vbar_s",
1292         "mvbar",
1293         "rmr",
1294         "isr",
1295         "hvbar",
1296         "fcseidr",
1297         "contextidr",
1298         "contextidr_ns",
1299         "contextidr_s",
1300         "tpidrurw",
1301         "tpidrurw_ns",
1302         "tpidrurw_s",
1303         "tpidruro",
1304         "tpidruro_ns",
1305         "tpidruro_s",
1306         "tpidrprw",
1307         "tpidrprw_ns",
1308         "tpidrprw_s",
1309         "htpidr",
1310         "cntfrq",
1311         "cntkctl",
1312         "cntp_tval",
1313         "cntp_tval_ns",
1314         "cntp_tval_s",
1315         "cntp_ctl",
1316         "cntp_ctl_ns",
1317         "cntp_ctl_s",
1318         "cntv_tval",
1319         "cntv_ctl",
1320         "cnthctl",
1321         "cnthp_tval",
1322         "cnthp_ctl",
1323         "il1data0",
1324         "il1data1",
1325         "il1data2",
1326         "il1data3",
1327         "dl1data0",
1328         "dl1data1",
1329         "dl1data2",
1330         "dl1data3",
1331         "dl1data4",
1332         "ramindex",
1333         "l2actlr",
1334         "cbar",
1335         "httbr",
1336         "vttbr",
1337         "cntpct",
1338         "cntvct",
1339         "cntp_cval",
1340         "cntp_cval_ns",
1341         "cntp_cval_s",
1342         "cntv_cval",
1343         "cntvoff",
1344         "cnthp_cval",
1345         "cpumerrsr",
1346         "l2merrsr",
1347
1348         // AArch64 registers (Op0=2)
1349         "mdccint_el1",
1350         "osdtrrx_el1",
1351         "mdscr_el1",
1352         "osdtrtx_el1",
1353         "oseccr_el1",
1354         "dbgbvr0_el1",
1355         "dbgbvr1_el1",
1356         "dbgbvr2_el1",
1357         "dbgbvr3_el1",
1358         "dbgbvr4_el1",
1359         "dbgbvr5_el1",
1360         "dbgbcr0_el1",
1361         "dbgbcr1_el1",
1362         "dbgbcr2_el1",
1363         "dbgbcr3_el1",
1364         "dbgbcr4_el1",
1365         "dbgbcr5_el1",
1366         "dbgwvr0_el1",
1367         "dbgwvr1_el1",
1368         "dbgwvr2_el1",
1369         "dbgwvr3_el1",
1370         "dbgwcr0_el1",
1371         "dbgwcr1_el1",
1372         "dbgwcr2_el1",
1373         "dbgwcr3_el1",
1374         "mdccsr_el0",
1375         "mddtr_el0",
1376         "mddtrtx_el0",
1377         "mddtrrx_el0",
1378         "dbgvcr32_el2",
1379         "mdrar_el1",
1380         "oslar_el1",
1381         "oslsr_el1",
1382         "osdlr_el1",
1383         "dbgprcr_el1",
1384         "dbgclaimset_el1",
1385         "dbgclaimclr_el1",
1386         "dbgauthstatus_el1",
1387         "teecr32_el1",
1388         "teehbr32_el1",
1389
1390         // AArch64 registers (Op0=1,3)
1391         "midr_el1",
1392         "mpidr_el1",
1393         "revidr_el1",
1394         "id_pfr0_el1",
1395         "id_pfr1_el1",
1396         "id_dfr0_el1",
1397         "id_afr0_el1",
1398         "id_mmfr0_el1",
1399         "id_mmfr1_el1",
1400         "id_mmfr2_el1",
1401         "id_mmfr3_el1",
1402         "id_isar0_el1",
1403         "id_isar1_el1",
1404         "id_isar2_el1",
1405         "id_isar3_el1",
1406         "id_isar4_el1",
1407         "id_isar5_el1",
1408         "mvfr0_el1",
1409         "mvfr1_el1",
1410         "mvfr2_el1",
1411         "id_aa64pfr0_el1",
1412         "id_aa64pfr1_el1",
1413         "id_aa64dfr0_el1",
1414         "id_aa64dfr1_el1",
1415         "id_aa64afr0_el1",
1416         "id_aa64afr1_el1",
1417         "id_aa64isar0_el1",
1418         "id_aa64isar1_el1",
1419         "id_aa64mmfr0_el1",
1420         "id_aa64mmfr1_el1",
1421         "ccsidr_el1",
1422         "clidr_el1",
1423         "aidr_el1",
1424         "csselr_el1",
1425         "ctr_el0",
1426         "dczid_el0",
1427         "vpidr_el2",
1428         "vmpidr_el2",
1429         "sctlr_el1",
1430         "actlr_el1",
1431         "cpacr_el1",
1432         "sctlr_el2",
1433         "actlr_el2",
1434         "hcr_el2",
1435         "mdcr_el2",
1436         "cptr_el2",
1437         "hstr_el2",
1438         "hacr_el2",
1439         "sctlr_el3",
1440         "actlr_el3",
1441         "scr_el3",
1442         "sder32_el3",
1443         "cptr_el3",
1444         "mdcr_el3",
1445         "ttbr0_el1",
1446         "ttbr1_el1",
1447         "tcr_el1",
1448         "ttbr0_el2",
1449         "tcr_el2",
1450         "vttbr_el2",
1451         "vtcr_el2",
1452         "ttbr0_el3",
1453         "tcr_el3",
1454         "dacr32_el2",
1455         "spsr_el1",
1456         "elr_el1",
1457         "sp_el0",
1458         "spsel",
1459         "currentel",
1460         "nzcv",
1461         "daif",
1462         "fpcr",
1463         "fpsr",
1464         "dspsr_el0",
1465         "dlr_el0",
1466         "spsr_el2",
1467         "elr_el2",
1468         "sp_el1",
1469         "spsr_irq_aa64",
1470         "spsr_abt_aa64",
1471         "spsr_und_aa64",
1472         "spsr_fiq_aa64",
1473         "spsr_el3",
1474         "elr_el3",
1475         "sp_el2",
1476         "afsr0_el1",
1477         "afsr1_el1",
1478         "esr_el1",
1479         "ifsr32_el2",
1480         "afsr0_el2",
1481         "afsr1_el2",
1482         "esr_el2",
1483         "fpexc32_el2",
1484         "afsr0_el3",
1485         "afsr1_el3",
1486         "esr_el3",
1487         "far_el1",
1488         "far_el2",
1489         "hpfar_el2",
1490         "far_el3",
1491         "ic_ialluis",
1492         "par_el1",
1493         "ic_iallu",
1494         "dc_ivac_xt",
1495         "dc_isw_xt",
1496         "at_s1e1r_xt",
1497         "at_s1e1w_xt",
1498         "at_s1e0r_xt",
1499         "at_s1e0w_xt",
1500         "dc_csw_xt",
1501         "dc_cisw_xt",
1502         "dc_zva_xt",
1503         "ic_ivau_xt",
1504         "dc_cvac_xt",
1505         "dc_cvau_xt",
1506         "dc_civac_xt",
1507         "at_s1e2r_xt",
1508         "at_s1e2w_xt",
1509         "at_s12e1r_xt",
1510         "at_s12e1w_xt",
1511         "at_s12e0r_xt",
1512         "at_s12e0w_xt",
1513         "at_s1e3r_xt",
1514         "at_s1e3w_xt",
1515         "tlbi_vmalle1is",
1516         "tlbi_vae1is_xt",
1517         "tlbi_aside1is_xt",
1518         "tlbi_vaae1is_xt",
1519         "tlbi_vale1is_xt",
1520         "tlbi_vaale1is_xt",
1521         "tlbi_vmalle1",
1522         "tlbi_vae1_xt",
1523         "tlbi_aside1_xt",
1524         "tlbi_vaae1_xt",
1525         "tlbi_vale1_xt",
1526         "tlbi_vaale1_xt",
1527         "tlbi_ipas2e1is_xt",
1528         "tlbi_ipas2le1is_xt",
1529         "tlbi_alle2is",
1530         "tlbi_vae2is_xt",
1531         "tlbi_alle1is",
1532         "tlbi_vale2is_xt",
1533         "tlbi_vmalls12e1is",
1534         "tlbi_ipas2e1_xt",
1535         "tlbi_ipas2le1_xt",
1536         "tlbi_alle2",
1537         "tlbi_vae2_xt",
1538         "tlbi_alle1",
1539         "tlbi_vale2_xt",
1540         "tlbi_vmalls12e1",
1541         "tlbi_alle3is",
1542         "tlbi_vae3is_xt",
1543         "tlbi_vale3is_xt",
1544         "tlbi_alle3",
1545         "tlbi_vae3_xt",
1546         "tlbi_vale3_xt",
1547         "pmintenset_el1",
1548         "pmintenclr_el1",
1549         "pmcr_el0",
1550         "pmcntenset_el0",
1551         "pmcntenclr_el0",
1552         "pmovsclr_el0",
1553         "pmswinc_el0",
1554         "pmselr_el0",
1555         "pmceid0_el0",
1556         "pmceid1_el0",
1557         "pmccntr_el0",
1558         "pmxevtyper_el0",
1559         "pmccfiltr_el0",
1560         "pmxevcntr_el0",
1561         "pmuserenr_el0",
1562         "pmovsset_el0",
1563         "mair_el1",
1564         "amair_el1",
1565         "mair_el2",
1566         "amair_el2",
1567         "mair_el3",
1568         "amair_el3",
1569         "l2ctlr_el1",
1570         "l2ectlr_el1",
1571         "vbar_el1",
1572         "rvbar_el1",
1573         "isr_el1",
1574         "vbar_el2",
1575         "rvbar_el2",
1576         "vbar_el3",
1577         "rvbar_el3",
1578         "rmr_el3",
1579         "contextidr_el1",
1580         "tpidr_el1",
1581         "tpidr_el0",
1582         "tpidrro_el0",
1583         "tpidr_el2",
1584         "tpidr_el3",
1585         "cntkctl_el1",
1586         "cntfrq_el0",
1587         "cntpct_el0",
1588         "cntvct_el0",
1589         "cntp_tval_el0",
1590         "cntp_ctl_el0",
1591         "cntp_cval_el0",
1592         "cntv_tval_el0",
1593         "cntv_ctl_el0",
1594         "cntv_cval_el0",
1595         "pmevcntr0_el0",
1596         "pmevcntr1_el0",
1597         "pmevcntr2_el0",
1598         "pmevcntr3_el0",
1599         "pmevcntr4_el0",
1600         "pmevcntr5_el0",
1601         "pmevtyper0_el0",
1602         "pmevtyper1_el0",
1603         "pmevtyper2_el0",
1604         "pmevtyper3_el0",
1605         "pmevtyper4_el0",
1606         "pmevtyper5_el0",
1607         "cntvoff_el2",
1608         "cnthctl_el2",
1609         "cnthp_tval_el2",
1610         "cnthp_ctl_el2",
1611         "cnthp_cval_el2",
1612         "cntps_tval_el1",
1613         "cntps_ctl_el1",
1614         "cntps_cval_el1",
1615         "il1data0_el1",
1616         "il1data1_el1",
1617         "il1data2_el1",
1618         "il1data3_el1",
1619         "dl1data0_el1",
1620         "dl1data1_el1",
1621         "dl1data2_el1",
1622         "dl1data3_el1",
1623         "dl1data4_el1",
1624         "l2actlr_el1",
1625         "cpuactlr_el1",
1626         "cpuectlr_el1",
1627         "cpumerrsr_el1",
1628         "l2merrsr_el1",
1629         "cbar_el1",
1630         "contextidr_el2",
1631
1632         "ttbr1_el2",
1633         "cnthv_ctl_el2",
1634         "cnthv_cval_el2",
1635         "cnthv_tval_el2",
1636         "id_aa64mmfr2_el1",
1637
1638         "apdakeyhi_el1",
1639         "apdakeylo_el1",
1640         "apdbkeyhi_el1",
1641         "apdbkeylo_el1",
1642         "apgakeyhi_el1",
1643         "apgakeylo_el1",
1644         "apiakeyhi_el1",
1645         "apiakeylo_el1",
1646         "apibkeyhi_el1",
1647         "apibkeylo_el1",
1648         // GICv3, CPU interface
1649         "icc_pmr_el1",
1650         "icc_iar0_el1",
1651         "icc_eoir0_el1",
1652         "icc_hppir0_el1",
1653         "icc_bpr0_el1",
1654         "icc_ap0r0_el1",
1655         "icc_ap0r1_el1",
1656         "icc_ap0r2_el1",
1657         "icc_ap0r3_el1",
1658         "icc_ap1r0_el1",
1659         "icc_ap1r0_el1_ns",
1660         "icc_ap1r0_el1_s",
1661         "icc_ap1r1_el1",
1662         "icc_ap1r1_el1_ns",
1663         "icc_ap1r1_el1_s",
1664         "icc_ap1r2_el1",
1665         "icc_ap1r2_el1_ns",
1666         "icc_ap1r2_el1_s",
1667         "icc_ap1r3_el1",
1668         "icc_ap1r3_el1_ns",
1669         "icc_ap1r3_el1_s",
1670         "icc_dir_el1",
1671         "icc_rpr_el1",
1672         "icc_sgi1r_el1",
1673         "icc_asgi1r_el1",
1674         "icc_sgi0r_el1",
1675         "icc_iar1_el1",
1676         "icc_eoir1_el1",
1677         "icc_hppir1_el1",
1678         "icc_bpr1_el1",
1679         "icc_bpr1_el1_ns",
1680         "icc_bpr1_el1_s",
1681         "icc_ctlr_el1",
1682         "icc_ctlr_el1_ns",
1683         "icc_ctlr_el1_s",
1684         "icc_sre_el1",
1685         "icc_sre_el1_ns",
1686         "icc_sre_el1_s",
1687         "icc_igrpen0_el1",
1688         "icc_igrpen1_el1",
1689         "icc_igrpen1_el1_ns",
1690         "icc_igrpen1_el1_s",
1691         "icc_sre_el2",
1692         "icc_ctlr_el3",
1693         "icc_sre_el3",
1694         "icc_igrpen1_el3",
1695
1696         // GICv3, CPU interface, virtualization
1697         "ich_ap0r0_el2",
1698         "ich_ap0r1_el2",
1699         "ich_ap0r2_el2",
1700         "ich_ap0r3_el2",
1701         "ich_ap1r0_el2",
1702         "ich_ap1r1_el2",
1703         "ich_ap1r2_el2",
1704         "ich_ap1r3_el2",
1705         "ich_hcr_el2",
1706         "ich_vtr_el2",
1707         "ich_misr_el2",
1708         "ich_eisr_el2",
1709         "ich_elrsr_el2",
1710         "ich_vmcr_el2",
1711         "ich_lr0_el2",
1712         "ich_lr1_el2",
1713         "ich_lr2_el2",
1714         "ich_lr3_el2",
1715         "ich_lr4_el2",
1716         "ich_lr5_el2",
1717         "ich_lr6_el2",
1718         "ich_lr7_el2",
1719         "ich_lr8_el2",
1720         "ich_lr9_el2",
1721         "ich_lr10_el2",
1722         "ich_lr11_el2",
1723         "ich_lr12_el2",
1724         "ich_lr13_el2",
1725         "ich_lr14_el2",
1726         "ich_lr15_el2",
1727
1728         "icv_pmr_el1",
1729         "icv_iar0_el1",
1730         "icv_eoir0_el1",
1731         "icv_hppir0_el1",
1732         "icv_bpr0_el1",
1733         "icv_ap0r0_el1",
1734         "icv_ap0r1_el1",
1735         "icv_ap0r2_el1",
1736         "icv_ap0r3_el1",
1737         "icv_ap1r0_el1",
1738         "icv_ap1r0_el1_ns",
1739         "icv_ap1r0_el1_s",
1740         "icv_ap1r1_el1",
1741         "icv_ap1r1_el1_ns",
1742         "icv_ap1r1_el1_s",
1743         "icv_ap1r2_el1",
1744         "icv_ap1r2_el1_ns",
1745         "icv_ap1r2_el1_s",
1746         "icv_ap1r3_el1",
1747         "icv_ap1r3_el1_ns",
1748         "icv_ap1r3_el1_s",
1749         "icv_dir_el1",
1750         "icv_rpr_el1",
1751         "icv_sgi1r_el1",
1752         "icv_asgi1r_el1",
1753         "icv_sgi0r_el1",
1754         "icv_iar1_el1",
1755         "icv_eoir1_el1",
1756         "icv_hppir1_el1",
1757         "icv_bpr1_el1",
1758         "icv_bpr1_el1_ns",
1759         "icv_bpr1_el1_s",
1760         "icv_ctlr_el1",
1761         "icv_ctlr_el1_ns",
1762         "icv_ctlr_el1_s",
1763         "icv_sre_el1",
1764         "icv_sre_el1_ns",
1765         "icv_sre_el1_s",
1766         "icv_igrpen0_el1",
1767         "icv_igrpen1_el1",
1768         "icv_igrpen1_el1_ns",
1769         "icv_igrpen1_el1_s",
1770
1771         "icc_ap0r0",
1772         "icc_ap0r1",
1773         "icc_ap0r2",
1774         "icc_ap0r3",
1775         "icc_ap1r0",
1776         "icc_ap1r0_ns",
1777         "icc_ap1r0_s",
1778         "icc_ap1r1",
1779         "icc_ap1r1_ns",
1780         "icc_ap1r1_s",
1781         "icc_ap1r2",
1782         "icc_ap1r2_ns",
1783         "icc_ap1r2_s",
1784         "icc_ap1r3",
1785         "icc_ap1r3_ns",
1786         "icc_ap1r3_s",
1787         "icc_asgi1r",
1788         "icc_bpr0",
1789         "icc_bpr1",
1790         "icc_bpr1_ns",
1791         "icc_bpr1_s",
1792         "icc_ctlr",
1793         "icc_ctlr_ns",
1794         "icc_ctlr_s",
1795         "icc_dir",
1796         "icc_eoir0",
1797         "icc_eoir1",
1798         "icc_hppir0",
1799         "icc_hppir1",
1800         "icc_hsre",
1801         "icc_iar0",
1802         "icc_iar1",
1803         "icc_igrpen0",
1804         "icc_igrpen1",
1805         "icc_igrpen1_ns",
1806         "icc_igrpen1_s",
1807         "icc_mctlr",
1808         "icc_mgrpen1",
1809         "icc_msre",
1810         "icc_pmr",
1811         "icc_rpr",
1812         "icc_sgi0r",
1813         "icc_sgi1r",
1814         "icc_sre",
1815         "icc_sre_ns",
1816         "icc_sre_s",
1817
1818         "ich_ap0r0",
1819         "ich_ap0r1",
1820         "ich_ap0r2",
1821         "ich_ap0r3",
1822         "ich_ap1r0",
1823         "ich_ap1r1",
1824         "ich_ap1r2",
1825         "ich_ap1r3",
1826         "ich_hcr",
1827         "ich_vtr",
1828         "ich_misr",
1829         "ich_eisr",
1830         "ich_elrsr",
1831         "ich_vmcr",
1832         "ich_lr0",
1833         "ich_lr1",
1834         "ich_lr2",
1835         "ich_lr3",
1836         "ich_lr4",
1837         "ich_lr5",
1838         "ich_lr6",
1839         "ich_lr7",
1840         "ich_lr8",
1841         "ich_lr9",
1842         "ich_lr10",
1843         "ich_lr11",
1844         "ich_lr12",
1845         "ich_lr13",
1846         "ich_lr14",
1847         "ich_lr15",
1848         "ich_lrc0",
1849         "ich_lrc1",
1850         "ich_lrc2",
1851         "ich_lrc3",
1852         "ich_lrc4",
1853         "ich_lrc5",
1854         "ich_lrc6",
1855         "ich_lrc7",
1856         "ich_lrc8",
1857         "ich_lrc9",
1858         "ich_lrc10",
1859         "ich_lrc11",
1860         "ich_lrc12",
1861         "ich_lrc13",
1862         "ich_lrc14",
1863         "ich_lrc15",
1864
1865         "id_aa64zfr0_el1",
1866         "zcr_el3",
1867         "zcr_el2",
1868         "zcr_el12",
1869         "zcr_el1",
1870
1871         "num_phys_regs",
1872
1873         // Dummy registers
1874         "nop",
1875         "raz",
1876         "cp14_unimpl",
1877         "cp15_unimpl",
1878         "unknown",
1879         "impl_defined",
1880         "erridr_el1",
1881         "errselr_el1",
1882         "erxfr_el1",
1883         "erxctlr_el1",
1884         "erxstatus_el1",
1885         "erxaddr_el1",
1886         "erxmisc0_el1",
1887         "erxmisc1_el1",
1888         "disr_el1",
1889         "vsesr_el2",
1890         "vdisr_el2",
1891
1892         // PSTATE
1893         "pan",
1894     };
1895
1896     static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1897                   "The miscRegName array and NUM_MISCREGS are inconsistent.");
1898
1899     // This mask selects bits of the CPSR that actually go in the CondCodes
1900     // integer register to allow renaming.
1901     static const uint32_t CondCodesMask   = 0xF00F0000;
1902     static const uint32_t CpsrMaskQ       = 0x08000000;
1903
1904     // APSR (Application Program Status Register Mask). It is the user level
1905     // alias for the CPSR. The APSR is a subset of the CPSR. Although
1906     // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1907     // APSR:
1908     // Bit[9] returns the value of CPSR.E.
1909     // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1910     static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1911
1912     // CPSR (Current Program Status Register Mask).
1913     static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1914
1915     // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1916     // integer register to allow renaming.
1917     static const uint32_t FpCondCodesMask = 0xF0000000;
1918     // This mask selects the cumulative FP exception flags of the FPSCR.
1919     static const uint32_t FpscrExcMask = 0x0000009F;
1920     // This mask selects the cumulative saturation flag of the FPSCR.
1921     static const uint32_t FpscrQcMask = 0x08000000;
1922
1923     /**
1924      * Check for permission to read coprocessor registers.
1925      *
1926      * Checks whether an instruction at the current program mode has
1927      * permissions to read the coprocessor registers. This function
1928      * returns whether the check is undefined and if not whether the
1929      * read access is permitted.
1930      *
1931      * @param the misc reg indicating the coprocessor
1932      * @param the SCR
1933      * @param the CPSR
1934      * @return a tuple of booleans: can_read, undefined
1935      */
1936     std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1937                                            CPSR cpsr);
1938
1939     /**
1940      * Check for permission to write coprocessor registers.
1941      *
1942      * Checks whether an instruction at the current program mode has
1943      * permissions to write the coprocessor registers. This function
1944      * returns whether the check is undefined and if not whether the
1945      * write access is permitted.
1946      *
1947      * @param the misc reg indicating the coprocessor
1948      * @param the SCR
1949      * @param the CPSR
1950      * @return a tuple of booleans: can_write, undefined
1951      */
1952     std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1953                                              CPSR cpsr);
1954
1955     // Checks read access permissions to AArch64 system registers
1956     bool canReadAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1957                               ThreadContext *tc);
1958
1959     // Checks write access permissions to AArch64 system registers
1960     bool canWriteAArch64SysReg(MiscRegIndex reg, HCR hcr, SCR scr, CPSR cpsr,
1961                                ThreadContext *tc);
1962
1963     // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1964     // for MCR/MRC instructions
1965     int
1966     snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
1967
1968     // Flattens a misc reg index using the specified security state. This is
1969     // used for opperations (eg address translations) where the security
1970     // state of the register access may differ from the current state of the
1971     // processor
1972     int
1973     snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
1974
1975     int
1976     snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc);
1977
1978     // Takes a misc reg index and returns the root reg if its one of a set of
1979     // banked registers
1980     void
1981     preUnflattenMiscReg();
1982
1983     int
1984     unflattenMiscReg(int reg);
1985
1986 }
1987
1988 #endif // __ARCH_ARM_MISCREGS_HH__