src/arch/arm/miscregs.hh

   1 /*
   2  * Copyright (c) 2010-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  *          Giacomo Gabrielli
  42  */
  43 #ifndef __ARCH_ARM_MISCREGS_HH__
  44 #define __ARCH_ARM_MISCREGS_HH__
  45
  46 #include <bitset>
  47 #include <tuple>
  48
  49 #include "arch/arm/miscregs_types.hh"
  50 #include "base/compiler.hh"
  51
  52 class ThreadContext;
  53
  54
  55 namespace ArmISA
  56 {
  57     enum MiscRegIndex {
  58         MISCREG_CPSR = 0,
  59         MISCREG_SPSR,
  60         MISCREG_SPSR_FIQ,
  61         MISCREG_SPSR_IRQ,
  62         MISCREG_SPSR_SVC,
  63         MISCREG_SPSR_MON,
  64         MISCREG_SPSR_ABT,
  65         MISCREG_SPSR_HYP,
  66         MISCREG_SPSR_UND,
  67         MISCREG_ELR_HYP,
  68         MISCREG_FPSID,
  69         MISCREG_FPSCR,
  70         MISCREG_MVFR1,
  71         MISCREG_MVFR0,
  72         MISCREG_FPEXC,
  73
  74         // Helper registers
  75         MISCREG_CPSR_MODE,
  76         MISCREG_CPSR_Q,
  77         MISCREG_FPSCR_EXC,
  78         MISCREG_FPSCR_QC,
  79         MISCREG_LOCKADDR,
  80         MISCREG_LOCKFLAG,
  81         MISCREG_PRRR_MAIR0,
  82         MISCREG_PRRR_MAIR0_NS,
  83         MISCREG_PRRR_MAIR0_S,
  84         MISCREG_NMRR_MAIR1,
  85         MISCREG_NMRR_MAIR1_NS,
  86         MISCREG_NMRR_MAIR1_S,
  87         MISCREG_PMXEVTYPER_PMCCFILTR,
  88         MISCREG_SCTLR_RST,
  89         MISCREG_SEV_MAILBOX,
  90
  91         // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
  92         MISCREG_DBGDIDR,
  93         MISCREG_DBGDSCRint,
  94         MISCREG_DBGDCCINT,
  95         MISCREG_DBGDTRTXint,
  96         MISCREG_DBGDTRRXint,
  97         MISCREG_DBGWFAR,
  98         MISCREG_DBGVCR,
  99         MISCREG_DBGDTRRXext,
 100         MISCREG_DBGDSCRext,
 101         MISCREG_DBGDTRTXext,
 102         MISCREG_DBGOSECCR,
 103         MISCREG_DBGBVR0,
 104         MISCREG_DBGBVR1,
 105         MISCREG_DBGBVR2,
 106         MISCREG_DBGBVR3,
 107         MISCREG_DBGBVR4,
 108         MISCREG_DBGBVR5,
 109         MISCREG_DBGBCR0,
 110         MISCREG_DBGBCR1,
 111         MISCREG_DBGBCR2,
 112         MISCREG_DBGBCR3,
 113         MISCREG_DBGBCR4,
 114         MISCREG_DBGBCR5,
 115         MISCREG_DBGWVR0,
 116         MISCREG_DBGWVR1,
 117         MISCREG_DBGWVR2,
 118         MISCREG_DBGWVR3,
 119         MISCREG_DBGWCR0,
 120         MISCREG_DBGWCR1,
 121         MISCREG_DBGWCR2,
 122         MISCREG_DBGWCR3,
 123         MISCREG_DBGDRAR,
 124         MISCREG_DBGBXVR4,
 125         MISCREG_DBGBXVR5,
 126         MISCREG_DBGOSLAR,
 127         MISCREG_DBGOSLSR,
 128         MISCREG_DBGOSDLR,
 129         MISCREG_DBGPRCR,
 130         MISCREG_DBGDSAR,
 131         MISCREG_DBGCLAIMSET,
 132         MISCREG_DBGCLAIMCLR,
 133         MISCREG_DBGAUTHSTATUS,
 134         MISCREG_DBGDEVID2,
 135         MISCREG_DBGDEVID1,
 136         MISCREG_DBGDEVID0,
 137         MISCREG_TEECR,  // not in ARM DDI 0487A.b+
 138         MISCREG_JIDR,
 139         MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
 140         MISCREG_JOSCR,
 141         MISCREG_JMCR,
 142
 143         // AArch32 CP15 registers (system control)
 144         MISCREG_MIDR,
 145         MISCREG_CTR,
 146         MISCREG_TCMTR,
 147         MISCREG_TLBTR,
 148         MISCREG_MPIDR,
 149         MISCREG_REVIDR,
 150         MISCREG_ID_PFR0,
 151         MISCREG_ID_PFR1,
 152         MISCREG_ID_DFR0,
 153         MISCREG_ID_AFR0,
 154         MISCREG_ID_MMFR0,
 155         MISCREG_ID_MMFR1,
 156         MISCREG_ID_MMFR2,
 157         MISCREG_ID_MMFR3,
 158         MISCREG_ID_ISAR0,
 159         MISCREG_ID_ISAR1,
 160         MISCREG_ID_ISAR2,
 161         MISCREG_ID_ISAR3,
 162         MISCREG_ID_ISAR4,
 163         MISCREG_ID_ISAR5,
 164         MISCREG_CCSIDR,
 165         MISCREG_CLIDR,
 166         MISCREG_AIDR,
 167         MISCREG_CSSELR,
 168         MISCREG_CSSELR_NS,
 169         MISCREG_CSSELR_S,
 170         MISCREG_VPIDR,
 171         MISCREG_VMPIDR,
 172         MISCREG_SCTLR,
 173         MISCREG_SCTLR_NS,
 174         MISCREG_SCTLR_S,
 175         MISCREG_ACTLR,
 176         MISCREG_ACTLR_NS,
 177         MISCREG_ACTLR_S,
 178         MISCREG_CPACR,
 179         MISCREG_SCR,
 180         MISCREG_SDER,
 181         MISCREG_NSACR,
 182         MISCREG_HSCTLR,
 183         MISCREG_HACTLR,
 184         MISCREG_HCR,
 185         MISCREG_HCR2,
 186         MISCREG_HDCR,
 187         MISCREG_HCPTR,
 188         MISCREG_HSTR,
 189         MISCREG_HACR,
 190         MISCREG_TTBR0,
 191         MISCREG_TTBR0_NS,
 192         MISCREG_TTBR0_S,
 193         MISCREG_TTBR1,
 194         MISCREG_TTBR1_NS,
 195         MISCREG_TTBR1_S,
 196         MISCREG_TTBCR,
 197         MISCREG_TTBCR_NS,
 198         MISCREG_TTBCR_S,
 199         MISCREG_HTCR,
 200         MISCREG_VTCR,
 201         MISCREG_DACR,
 202         MISCREG_DACR_NS,
 203         MISCREG_DACR_S,
 204         MISCREG_DFSR,
 205         MISCREG_DFSR_NS,
 206         MISCREG_DFSR_S,
 207         MISCREG_IFSR,
 208         MISCREG_IFSR_NS,
 209         MISCREG_IFSR_S,
 210         MISCREG_ADFSR,
 211         MISCREG_ADFSR_NS,
 212         MISCREG_ADFSR_S,
 213         MISCREG_AIFSR,
 214         MISCREG_AIFSR_NS,
 215         MISCREG_AIFSR_S,
 216         MISCREG_HADFSR,
 217         MISCREG_HAIFSR,
 218         MISCREG_HSR,
 219         MISCREG_DFAR,
 220         MISCREG_DFAR_NS,
 221         MISCREG_DFAR_S,
 222         MISCREG_IFAR,
 223         MISCREG_IFAR_NS,
 224         MISCREG_IFAR_S,
 225         MISCREG_HDFAR,
 226         MISCREG_HIFAR,
 227         MISCREG_HPFAR,
 228         MISCREG_ICIALLUIS,
 229         MISCREG_BPIALLIS,
 230         MISCREG_PAR,
 231         MISCREG_PAR_NS,
 232         MISCREG_PAR_S,
 233         MISCREG_ICIALLU,
 234         MISCREG_ICIMVAU,
 235         MISCREG_CP15ISB,
 236         MISCREG_BPIALL,
 237         MISCREG_BPIMVA,
 238         MISCREG_DCIMVAC,
 239         MISCREG_DCISW,
 240         MISCREG_ATS1CPR,
 241         MISCREG_ATS1CPW,
 242         MISCREG_ATS1CUR,
 243         MISCREG_ATS1CUW,
 244         MISCREG_ATS12NSOPR,
 245         MISCREG_ATS12NSOPW,
 246         MISCREG_ATS12NSOUR,
 247         MISCREG_ATS12NSOUW,
 248         MISCREG_DCCMVAC,
 249         MISCREG_DCCSW,
 250         MISCREG_CP15DSB,
 251         MISCREG_CP15DMB,
 252         MISCREG_DCCMVAU,
 253         MISCREG_DCCIMVAC,
 254         MISCREG_DCCISW,
 255         MISCREG_ATS1HR,
 256         MISCREG_ATS1HW,
 257         MISCREG_TLBIALLIS,
 258         MISCREG_TLBIMVAIS,
 259         MISCREG_TLBIASIDIS,
 260         MISCREG_TLBIMVAAIS,
 261         MISCREG_TLBIMVALIS,
 262         MISCREG_TLBIMVAALIS,
 263         MISCREG_ITLBIALL,
 264         MISCREG_ITLBIMVA,
 265         MISCREG_ITLBIASID,
 266         MISCREG_DTLBIALL,
 267         MISCREG_DTLBIMVA,
 268         MISCREG_DTLBIASID,
 269         MISCREG_TLBIALL,
 270         MISCREG_TLBIMVA,
 271         MISCREG_TLBIASID,
 272         MISCREG_TLBIMVAA,
 273         MISCREG_TLBIMVAL,
 274         MISCREG_TLBIMVAAL,
 275         MISCREG_TLBIIPAS2IS,
 276         MISCREG_TLBIIPAS2LIS,
 277         MISCREG_TLBIALLHIS,
 278         MISCREG_TLBIMVAHIS,
 279         MISCREG_TLBIALLNSNHIS,
 280         MISCREG_TLBIMVALHIS,
 281         MISCREG_TLBIIPAS2,
 282         MISCREG_TLBIIPAS2L,
 283         MISCREG_TLBIALLH,
 284         MISCREG_TLBIMVAH,
 285         MISCREG_TLBIALLNSNH,
 286         MISCREG_TLBIMVALH,
 287         MISCREG_PMCR,
 288         MISCREG_PMCNTENSET,
 289         MISCREG_PMCNTENCLR,
 290         MISCREG_PMOVSR,
 291         MISCREG_PMSWINC,
 292         MISCREG_PMSELR,
 293         MISCREG_PMCEID0,
 294         MISCREG_PMCEID1,
 295         MISCREG_PMCCNTR,
 296         MISCREG_PMXEVTYPER,
 297         MISCREG_PMCCFILTR,
 298         MISCREG_PMXEVCNTR,
 299         MISCREG_PMUSERENR,
 300         MISCREG_PMINTENSET,
 301         MISCREG_PMINTENCLR,
 302         MISCREG_PMOVSSET,
 303         MISCREG_L2CTLR,
 304         MISCREG_L2ECTLR,
 305         MISCREG_PRRR,
 306         MISCREG_PRRR_NS,
 307         MISCREG_PRRR_S,
 308         MISCREG_MAIR0,
 309         MISCREG_MAIR0_NS,
 310         MISCREG_MAIR0_S,
 311         MISCREG_NMRR,
 312         MISCREG_NMRR_NS,
 313         MISCREG_NMRR_S,
 314         MISCREG_MAIR1,
 315         MISCREG_MAIR1_NS,
 316         MISCREG_MAIR1_S,
 317         MISCREG_AMAIR0,
 318         MISCREG_AMAIR0_NS,
 319         MISCREG_AMAIR0_S,
 320         MISCREG_AMAIR1,
 321         MISCREG_AMAIR1_NS,
 322         MISCREG_AMAIR1_S,
 323         MISCREG_HMAIR0,
 324         MISCREG_HMAIR1,
 325         MISCREG_HAMAIR0,
 326         MISCREG_HAMAIR1,
 327         MISCREG_VBAR,
 328         MISCREG_VBAR_NS,
 329         MISCREG_VBAR_S,
 330         MISCREG_MVBAR,
 331         MISCREG_RMR,
 332         MISCREG_ISR,
 333         MISCREG_HVBAR,
 334         MISCREG_FCSEIDR,
 335         MISCREG_CONTEXTIDR,
 336         MISCREG_CONTEXTIDR_NS,
 337         MISCREG_CONTEXTIDR_S,
 338         MISCREG_TPIDRURW,
 339         MISCREG_TPIDRURW_NS,
 340         MISCREG_TPIDRURW_S,
 341         MISCREG_TPIDRURO,
 342         MISCREG_TPIDRURO_NS,
 343         MISCREG_TPIDRURO_S,
 344         MISCREG_TPIDRPRW,
 345         MISCREG_TPIDRPRW_NS,
 346         MISCREG_TPIDRPRW_S,
 347         MISCREG_HTPIDR,
 348         MISCREG_CNTFRQ,
 349         MISCREG_CNTKCTL,
 350         MISCREG_CNTP_TVAL,
 351         MISCREG_CNTP_TVAL_NS,
 352         MISCREG_CNTP_TVAL_S,
 353         MISCREG_CNTP_CTL,
 354         MISCREG_CNTP_CTL_NS,
 355         MISCREG_CNTP_CTL_S,
 356         MISCREG_CNTV_TVAL,
 357         MISCREG_CNTV_CTL,
 358         MISCREG_CNTHCTL,
 359         MISCREG_CNTHP_TVAL,
 360         MISCREG_CNTHP_CTL,
 361         MISCREG_IL1DATA0,
 362         MISCREG_IL1DATA1,
 363         MISCREG_IL1DATA2,
 364         MISCREG_IL1DATA3,
 365         MISCREG_DL1DATA0,
 366         MISCREG_DL1DATA1,
 367         MISCREG_DL1DATA2,
 368         MISCREG_DL1DATA3,
 369         MISCREG_DL1DATA4,
 370         MISCREG_RAMINDEX,
 371         MISCREG_L2ACTLR,
 372         MISCREG_CBAR,
 373         MISCREG_HTTBR,
 374         MISCREG_VTTBR,
 375         MISCREG_CNTPCT,
 376         MISCREG_CNTVCT,
 377         MISCREG_CNTP_CVAL,
 378         MISCREG_CNTP_CVAL_NS,
 379         MISCREG_CNTP_CVAL_S,
 380         MISCREG_CNTV_CVAL,
 381         MISCREG_CNTVOFF,
 382         MISCREG_CNTHP_CVAL,
 383         MISCREG_CPUMERRSR,
 384         MISCREG_L2MERRSR,
 385
 386         // AArch64 registers (Op0=2)
 387         MISCREG_MDCCINT_EL1,
 388         MISCREG_OSDTRRX_EL1,
 389         MISCREG_MDSCR_EL1,
 390         MISCREG_OSDTRTX_EL1,
 391         MISCREG_OSECCR_EL1,
 392         MISCREG_DBGBVR0_EL1,
 393         MISCREG_DBGBVR1_EL1,
 394         MISCREG_DBGBVR2_EL1,
 395         MISCREG_DBGBVR3_EL1,
 396         MISCREG_DBGBVR4_EL1,
 397         MISCREG_DBGBVR5_EL1,
 398         MISCREG_DBGBCR0_EL1,
 399         MISCREG_DBGBCR1_EL1,
 400         MISCREG_DBGBCR2_EL1,
 401         MISCREG_DBGBCR3_EL1,
 402         MISCREG_DBGBCR4_EL1,
 403         MISCREG_DBGBCR5_EL1,
 404         MISCREG_DBGWVR0_EL1,
 405         MISCREG_DBGWVR1_EL1,
 406         MISCREG_DBGWVR2_EL1,
 407         MISCREG_DBGWVR3_EL1,
 408         MISCREG_DBGWCR0_EL1,
 409         MISCREG_DBGWCR1_EL1,
 410         MISCREG_DBGWCR2_EL1,
 411         MISCREG_DBGWCR3_EL1,
 412         MISCREG_MDCCSR_EL0,
 413         MISCREG_MDDTR_EL0,
 414         MISCREG_MDDTRTX_EL0,
 415         MISCREG_MDDTRRX_EL0,
 416         MISCREG_DBGVCR32_EL2,
 417         MISCREG_MDRAR_EL1,
 418         MISCREG_OSLAR_EL1,
 419         MISCREG_OSLSR_EL1,
 420         MISCREG_OSDLR_EL1,
 421         MISCREG_DBGPRCR_EL1,
 422         MISCREG_DBGCLAIMSET_EL1,
 423         MISCREG_DBGCLAIMCLR_EL1,
 424         MISCREG_DBGAUTHSTATUS_EL1,
 425         MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
 426         MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
 427
 428         // AArch64 registers (Op0=1,3)
 429         MISCREG_MIDR_EL1,
 430         MISCREG_MPIDR_EL1,
 431         MISCREG_REVIDR_EL1,
 432         MISCREG_ID_PFR0_EL1,
 433         MISCREG_ID_PFR1_EL1,
 434         MISCREG_ID_DFR0_EL1,
 435         MISCREG_ID_AFR0_EL1,
 436         MISCREG_ID_MMFR0_EL1,
 437         MISCREG_ID_MMFR1_EL1,
 438         MISCREG_ID_MMFR2_EL1,
 439         MISCREG_ID_MMFR3_EL1,
 440         MISCREG_ID_ISAR0_EL1,
 441         MISCREG_ID_ISAR1_EL1,
 442         MISCREG_ID_ISAR2_EL1,
 443         MISCREG_ID_ISAR3_EL1,
 444         MISCREG_ID_ISAR4_EL1,
 445         MISCREG_ID_ISAR5_EL1,
 446         MISCREG_MVFR0_EL1,
 447         MISCREG_MVFR1_EL1,
 448         MISCREG_MVFR2_EL1,
 449         MISCREG_ID_AA64PFR0_EL1,
 450         MISCREG_ID_AA64PFR1_EL1,
 451         MISCREG_ID_AA64DFR0_EL1,
 452         MISCREG_ID_AA64DFR1_EL1,
 453         MISCREG_ID_AA64AFR0_EL1,
 454         MISCREG_ID_AA64AFR1_EL1,
 455         MISCREG_ID_AA64ISAR0_EL1,
 456         MISCREG_ID_AA64ISAR1_EL1,
 457         MISCREG_ID_AA64MMFR0_EL1,
 458         MISCREG_ID_AA64MMFR1_EL1,
 459         MISCREG_CCSIDR_EL1,
 460         MISCREG_CLIDR_EL1,
 461         MISCREG_AIDR_EL1,
 462         MISCREG_CSSELR_EL1,
 463         MISCREG_CTR_EL0,
 464         MISCREG_DCZID_EL0,
 465         MISCREG_VPIDR_EL2,
 466         MISCREG_VMPIDR_EL2,
 467         MISCREG_SCTLR_EL1,
 468         MISCREG_ACTLR_EL1,
 469         MISCREG_CPACR_EL1,
 470         MISCREG_SCTLR_EL2,
 471         MISCREG_ACTLR_EL2,
 472         MISCREG_HCR_EL2,
 473         MISCREG_MDCR_EL2,
 474         MISCREG_CPTR_EL2,
 475         MISCREG_HSTR_EL2,
 476         MISCREG_HACR_EL2,
 477         MISCREG_SCTLR_EL3,
 478         MISCREG_ACTLR_EL3,
 479         MISCREG_SCR_EL3,
 480         MISCREG_SDER32_EL3,
 481         MISCREG_CPTR_EL3,
 482         MISCREG_MDCR_EL3,
 483         MISCREG_TTBR0_EL1,
 484         MISCREG_TTBR1_EL1,
 485         MISCREG_TCR_EL1,
 486         MISCREG_TTBR0_EL2,
 487         MISCREG_TCR_EL2,
 488         MISCREG_VTTBR_EL2,
 489         MISCREG_VTCR_EL2,
 490         MISCREG_TTBR0_EL3,
 491         MISCREG_TCR_EL3,
 492         MISCREG_DACR32_EL2,
 493         MISCREG_SPSR_EL1,
 494         MISCREG_ELR_EL1,
 495         MISCREG_SP_EL0,
 496         MISCREG_SPSEL,
 497         MISCREG_CURRENTEL,
 498         MISCREG_NZCV,
 499         MISCREG_DAIF,
 500         MISCREG_FPCR,
 501         MISCREG_FPSR,
 502         MISCREG_DSPSR_EL0,
 503         MISCREG_DLR_EL0,
 504         MISCREG_SPSR_EL2,
 505         MISCREG_ELR_EL2,
 506         MISCREG_SP_EL1,
 507         MISCREG_SPSR_IRQ_AA64,
 508         MISCREG_SPSR_ABT_AA64,
 509         MISCREG_SPSR_UND_AA64,
 510         MISCREG_SPSR_FIQ_AA64,
 511         MISCREG_SPSR_EL3,
 512         MISCREG_ELR_EL3,
 513         MISCREG_SP_EL2,
 514         MISCREG_AFSR0_EL1,
 515         MISCREG_AFSR1_EL1,
 516         MISCREG_ESR_EL1,
 517         MISCREG_IFSR32_EL2,
 518         MISCREG_AFSR0_EL2,
 519         MISCREG_AFSR1_EL2,
 520         MISCREG_ESR_EL2,
 521         MISCREG_FPEXC32_EL2,
 522         MISCREG_AFSR0_EL3,
 523         MISCREG_AFSR1_EL3,
 524         MISCREG_ESR_EL3,
 525         MISCREG_FAR_EL1,
 526         MISCREG_FAR_EL2,
 527         MISCREG_HPFAR_EL2,
 528         MISCREG_FAR_EL3,
 529         MISCREG_IC_IALLUIS,
 530         MISCREG_PAR_EL1,
 531         MISCREG_IC_IALLU,
 532         MISCREG_DC_IVAC_Xt,
 533         MISCREG_DC_ISW_Xt,
 534         MISCREG_AT_S1E1R_Xt,
 535         MISCREG_AT_S1E1W_Xt,
 536         MISCREG_AT_S1E0R_Xt,
 537         MISCREG_AT_S1E0W_Xt,
 538         MISCREG_DC_CSW_Xt,
 539         MISCREG_DC_CISW_Xt,
 540         MISCREG_DC_ZVA_Xt,
 541         MISCREG_IC_IVAU_Xt,
 542         MISCREG_DC_CVAC_Xt,
 543         MISCREG_DC_CVAU_Xt,
 544         MISCREG_DC_CIVAC_Xt,
 545         MISCREG_AT_S1E2R_Xt,
 546         MISCREG_AT_S1E2W_Xt,
 547         MISCREG_AT_S12E1R_Xt,
 548         MISCREG_AT_S12E1W_Xt,
 549         MISCREG_AT_S12E0R_Xt,
 550         MISCREG_AT_S12E0W_Xt,
 551         MISCREG_AT_S1E3R_Xt,
 552         MISCREG_AT_S1E3W_Xt,
 553         MISCREG_TLBI_VMALLE1IS,
 554         MISCREG_TLBI_VAE1IS_Xt,
 555         MISCREG_TLBI_ASIDE1IS_Xt,
 556         MISCREG_TLBI_VAAE1IS_Xt,
 557         MISCREG_TLBI_VALE1IS_Xt,
 558         MISCREG_TLBI_VAALE1IS_Xt,
 559         MISCREG_TLBI_VMALLE1,
 560         MISCREG_TLBI_VAE1_Xt,
 561         MISCREG_TLBI_ASIDE1_Xt,
 562         MISCREG_TLBI_VAAE1_Xt,
 563         MISCREG_TLBI_VALE1_Xt,
 564         MISCREG_TLBI_VAALE1_Xt,
 565         MISCREG_TLBI_IPAS2E1IS_Xt,
 566         MISCREG_TLBI_IPAS2LE1IS_Xt,
 567         MISCREG_TLBI_ALLE2IS,
 568         MISCREG_TLBI_VAE2IS_Xt,
 569         MISCREG_TLBI_ALLE1IS,
 570         MISCREG_TLBI_VALE2IS_Xt,
 571         MISCREG_TLBI_VMALLS12E1IS,
 572         MISCREG_TLBI_IPAS2E1_Xt,
 573         MISCREG_TLBI_IPAS2LE1_Xt,
 574         MISCREG_TLBI_ALLE2,
 575         MISCREG_TLBI_VAE2_Xt,
 576         MISCREG_TLBI_ALLE1,
 577         MISCREG_TLBI_VALE2_Xt,
 578         MISCREG_TLBI_VMALLS12E1,
 579         MISCREG_TLBI_ALLE3IS,
 580         MISCREG_TLBI_VAE3IS_Xt,
 581         MISCREG_TLBI_VALE3IS_Xt,
 582         MISCREG_TLBI_ALLE3,
 583         MISCREG_TLBI_VAE3_Xt,
 584         MISCREG_TLBI_VALE3_Xt,
 585         MISCREG_PMINTENSET_EL1,
 586         MISCREG_PMINTENCLR_EL1,
 587         MISCREG_PMCR_EL0,
 588         MISCREG_PMCNTENSET_EL0,
 589         MISCREG_PMCNTENCLR_EL0,
 590         MISCREG_PMOVSCLR_EL0,
 591         MISCREG_PMSWINC_EL0,
 592         MISCREG_PMSELR_EL0,
 593         MISCREG_PMCEID0_EL0,
 594         MISCREG_PMCEID1_EL0,
 595         MISCREG_PMCCNTR_EL0,
 596         MISCREG_PMXEVTYPER_EL0,
 597         MISCREG_PMCCFILTR_EL0,
 598         MISCREG_PMXEVCNTR_EL0,
 599         MISCREG_PMUSERENR_EL0,
 600         MISCREG_PMOVSSET_EL0,
 601         MISCREG_MAIR_EL1,
 602         MISCREG_AMAIR_EL1,
 603         MISCREG_MAIR_EL2,
 604         MISCREG_AMAIR_EL2,
 605         MISCREG_MAIR_EL3,
 606         MISCREG_AMAIR_EL3,
 607         MISCREG_L2CTLR_EL1,
 608         MISCREG_L2ECTLR_EL1,
 609         MISCREG_VBAR_EL1,
 610         MISCREG_RVBAR_EL1,
 611         MISCREG_ISR_EL1,
 612         MISCREG_VBAR_EL2,
 613         MISCREG_RVBAR_EL2,
 614         MISCREG_VBAR_EL3,
 615         MISCREG_RVBAR_EL3,
 616         MISCREG_RMR_EL3,
 617         MISCREG_CONTEXTIDR_EL1,
 618         MISCREG_TPIDR_EL1,
 619         MISCREG_TPIDR_EL0,
 620         MISCREG_TPIDRRO_EL0,
 621         MISCREG_TPIDR_EL2,
 622         MISCREG_TPIDR_EL3,
 623         MISCREG_CNTKCTL_EL1,
 624         MISCREG_CNTFRQ_EL0,
 625         MISCREG_CNTPCT_EL0,
 626         MISCREG_CNTVCT_EL0,
 627         MISCREG_CNTP_TVAL_EL0,
 628         MISCREG_CNTP_CTL_EL0,
 629         MISCREG_CNTP_CVAL_EL0,
 630         MISCREG_CNTV_TVAL_EL0,
 631         MISCREG_CNTV_CTL_EL0,
 632         MISCREG_CNTV_CVAL_EL0,
 633         MISCREG_PMEVCNTR0_EL0,
 634         MISCREG_PMEVCNTR1_EL0,
 635         MISCREG_PMEVCNTR2_EL0,
 636         MISCREG_PMEVCNTR3_EL0,
 637         MISCREG_PMEVCNTR4_EL0,
 638         MISCREG_PMEVCNTR5_EL0,
 639         MISCREG_PMEVTYPER0_EL0,
 640         MISCREG_PMEVTYPER1_EL0,
 641         MISCREG_PMEVTYPER2_EL0,
 642         MISCREG_PMEVTYPER3_EL0,
 643         MISCREG_PMEVTYPER4_EL0,
 644         MISCREG_PMEVTYPER5_EL0,
 645         MISCREG_CNTVOFF_EL2,
 646         MISCREG_CNTHCTL_EL2,
 647         MISCREG_CNTHP_TVAL_EL2,
 648         MISCREG_CNTHP_CTL_EL2,
 649         MISCREG_CNTHP_CVAL_EL2,
 650         MISCREG_CNTPS_TVAL_EL1,
 651         MISCREG_CNTPS_CTL_EL1,
 652         MISCREG_CNTPS_CVAL_EL1,
 653         MISCREG_IL1DATA0_EL1,
 654         MISCREG_IL1DATA1_EL1,
 655         MISCREG_IL1DATA2_EL1,
 656         MISCREG_IL1DATA3_EL1,
 657         MISCREG_DL1DATA0_EL1,
 658         MISCREG_DL1DATA1_EL1,
 659         MISCREG_DL1DATA2_EL1,
 660         MISCREG_DL1DATA3_EL1,
 661         MISCREG_DL1DATA4_EL1,
 662         MISCREG_L2ACTLR_EL1,
 663         MISCREG_CPUACTLR_EL1,
 664         MISCREG_CPUECTLR_EL1,
 665         MISCREG_CPUMERRSR_EL1,
 666         MISCREG_L2MERRSR_EL1,
 667         MISCREG_CBAR_EL1,
 668         MISCREG_CONTEXTIDR_EL2,
 669
 670         // Introduced in ARMv8.1
 671         MISCREG_TTBR1_EL2,
 672         MISCREG_CNTHV_CTL_EL2,
 673         MISCREG_CNTHV_CVAL_EL2,
 674         MISCREG_CNTHV_TVAL_EL2,
 675
 676         MISCREG_ID_AA64MMFR2_EL1,
 677
 678         // GICv3, CPU interface
 679         MISCREG_ICC_PMR_EL1,
 680         MISCREG_ICC_IAR0_EL1,
 681         MISCREG_ICC_EOIR0_EL1,
 682         MISCREG_ICC_HPPIR0_EL1,
 683         MISCREG_ICC_BPR0_EL1,
 684         MISCREG_ICC_AP0R0_EL1,
 685         MISCREG_ICC_AP0R1_EL1,
 686         MISCREG_ICC_AP0R2_EL1,
 687         MISCREG_ICC_AP0R3_EL1,
 688         MISCREG_ICC_AP1R0_EL1,
 689         MISCREG_ICC_AP1R0_EL1_NS,
 690         MISCREG_ICC_AP1R0_EL1_S,
 691         MISCREG_ICC_AP1R1_EL1,
 692         MISCREG_ICC_AP1R1_EL1_NS,
 693         MISCREG_ICC_AP1R1_EL1_S,
 694         MISCREG_ICC_AP1R2_EL1,
 695         MISCREG_ICC_AP1R2_EL1_NS,
 696         MISCREG_ICC_AP1R2_EL1_S,
 697         MISCREG_ICC_AP1R3_EL1,
 698         MISCREG_ICC_AP1R3_EL1_NS,
 699         MISCREG_ICC_AP1R3_EL1_S,
 700         MISCREG_ICC_DIR_EL1,
 701         MISCREG_ICC_RPR_EL1,
 702         MISCREG_ICC_SGI1R_EL1,
 703         MISCREG_ICC_ASGI1R_EL1,
 704         MISCREG_ICC_SGI0R_EL1,
 705         MISCREG_ICC_IAR1_EL1,
 706         MISCREG_ICC_EOIR1_EL1,
 707         MISCREG_ICC_HPPIR1_EL1,
 708         MISCREG_ICC_BPR1_EL1,
 709         MISCREG_ICC_BPR1_EL1_NS,
 710         MISCREG_ICC_BPR1_EL1_S,
 711         MISCREG_ICC_CTLR_EL1,
 712         MISCREG_ICC_CTLR_EL1_NS,
 713         MISCREG_ICC_CTLR_EL1_S,
 714         MISCREG_ICC_SRE_EL1,
 715         MISCREG_ICC_SRE_EL1_NS,
 716         MISCREG_ICC_SRE_EL1_S,
 717         MISCREG_ICC_IGRPEN0_EL1,
 718         MISCREG_ICC_IGRPEN1_EL1,
 719         MISCREG_ICC_IGRPEN1_EL1_NS,
 720         MISCREG_ICC_IGRPEN1_EL1_S,
 721         MISCREG_ICC_SRE_EL2,
 722         MISCREG_ICC_CTLR_EL3,
 723         MISCREG_ICC_SRE_EL3,
 724         MISCREG_ICC_IGRPEN1_EL3,
 725
 726         // GICv3, CPU interface, virtualization
 727         MISCREG_ICH_AP0R0_EL2,
 728         MISCREG_ICH_AP0R1_EL2,
 729         MISCREG_ICH_AP0R2_EL2,
 730         MISCREG_ICH_AP0R3_EL2,
 731         MISCREG_ICH_AP1R0_EL2,
 732         MISCREG_ICH_AP1R1_EL2,
 733         MISCREG_ICH_AP1R2_EL2,
 734         MISCREG_ICH_AP1R3_EL2,
 735         MISCREG_ICH_HCR_EL2,
 736         MISCREG_ICH_VTR_EL2,
 737         MISCREG_ICH_MISR_EL2,
 738         MISCREG_ICH_EISR_EL2,
 739         MISCREG_ICH_ELRSR_EL2,
 740         MISCREG_ICH_VMCR_EL2,
 741         MISCREG_ICH_LR0_EL2,
 742         MISCREG_ICH_LR1_EL2,
 743         MISCREG_ICH_LR2_EL2,
 744         MISCREG_ICH_LR3_EL2,
 745         MISCREG_ICH_LR4_EL2,
 746         MISCREG_ICH_LR5_EL2,
 747         MISCREG_ICH_LR6_EL2,
 748         MISCREG_ICH_LR7_EL2,
 749         MISCREG_ICH_LR8_EL2,
 750         MISCREG_ICH_LR9_EL2,
 751         MISCREG_ICH_LR10_EL2,
 752         MISCREG_ICH_LR11_EL2,
 753         MISCREG_ICH_LR12_EL2,
 754         MISCREG_ICH_LR13_EL2,
 755         MISCREG_ICH_LR14_EL2,
 756         MISCREG_ICH_LR15_EL2,
 757
 758         MISCREG_ICV_PMR_EL1,
 759         MISCREG_ICV_IAR0_EL1,
 760         MISCREG_ICV_EOIR0_EL1,
 761         MISCREG_ICV_HPPIR0_EL1,
 762         MISCREG_ICV_BPR0_EL1,
 763         MISCREG_ICV_AP0R0_EL1,
 764         MISCREG_ICV_AP0R1_EL1,
 765         MISCREG_ICV_AP0R2_EL1,
 766         MISCREG_ICV_AP0R3_EL1,
 767         MISCREG_ICV_AP1R0_EL1,
 768         MISCREG_ICV_AP1R0_EL1_NS,
 769         MISCREG_ICV_AP1R0_EL1_S,
 770         MISCREG_ICV_AP1R1_EL1,
 771         MISCREG_ICV_AP1R1_EL1_NS,
 772         MISCREG_ICV_AP1R1_EL1_S,
 773         MISCREG_ICV_AP1R2_EL1,
 774         MISCREG_ICV_AP1R2_EL1_NS,
 775         MISCREG_ICV_AP1R2_EL1_S,
 776         MISCREG_ICV_AP1R3_EL1,
 777         MISCREG_ICV_AP1R3_EL1_NS,
 778         MISCREG_ICV_AP1R3_EL1_S,
 779         MISCREG_ICV_DIR_EL1,
 780         MISCREG_ICV_RPR_EL1,
 781         MISCREG_ICV_SGI1R_EL1,
 782         MISCREG_ICV_ASGI1R_EL1,
 783         MISCREG_ICV_SGI0R_EL1,
 784         MISCREG_ICV_IAR1_EL1,
 785         MISCREG_ICV_EOIR1_EL1,
 786         MISCREG_ICV_HPPIR1_EL1,
 787         MISCREG_ICV_BPR1_EL1,
 788         MISCREG_ICV_BPR1_EL1_NS,
 789         MISCREG_ICV_BPR1_EL1_S,
 790         MISCREG_ICV_CTLR_EL1,
 791         MISCREG_ICV_CTLR_EL1_NS,
 792         MISCREG_ICV_CTLR_EL1_S,
 793         MISCREG_ICV_SRE_EL1,
 794         MISCREG_ICV_SRE_EL1_NS,
 795         MISCREG_ICV_SRE_EL1_S,
 796         MISCREG_ICV_IGRPEN0_EL1,
 797         MISCREG_ICV_IGRPEN1_EL1,
 798         MISCREG_ICV_IGRPEN1_EL1_NS,
 799         MISCREG_ICV_IGRPEN1_EL1_S,
 800
 801         MISCREG_ICC_AP0R0,
 802         MISCREG_ICC_AP0R1,
 803         MISCREG_ICC_AP0R2,
 804         MISCREG_ICC_AP0R3,
 805         MISCREG_ICC_AP1R0,
 806         MISCREG_ICC_AP1R0_NS,
 807         MISCREG_ICC_AP1R0_S,
 808         MISCREG_ICC_AP1R1,
 809         MISCREG_ICC_AP1R1_NS,
 810         MISCREG_ICC_AP1R1_S,
 811         MISCREG_ICC_AP1R2,
 812         MISCREG_ICC_AP1R2_NS,
 813         MISCREG_ICC_AP1R2_S,
 814         MISCREG_ICC_AP1R3,
 815         MISCREG_ICC_AP1R3_NS,
 816         MISCREG_ICC_AP1R3_S,
 817         MISCREG_ICC_ASGI1R,
 818         MISCREG_ICC_BPR0,
 819         MISCREG_ICC_BPR1,
 820         MISCREG_ICC_BPR1_NS,
 821         MISCREG_ICC_BPR1_S,
 822         MISCREG_ICC_CTLR,
 823         MISCREG_ICC_CTLR_NS,
 824         MISCREG_ICC_CTLR_S,
 825         MISCREG_ICC_DIR,
 826         MISCREG_ICC_EOIR0,
 827         MISCREG_ICC_EOIR1,
 828         MISCREG_ICC_HPPIR0,
 829         MISCREG_ICC_HPPIR1,
 830         MISCREG_ICC_HSRE,
 831         MISCREG_ICC_IAR0,
 832         MISCREG_ICC_IAR1,
 833         MISCREG_ICC_IGRPEN0,
 834         MISCREG_ICC_IGRPEN1,
 835         MISCREG_ICC_IGRPEN1_NS,
 836         MISCREG_ICC_IGRPEN1_S,
 837         MISCREG_ICC_MCTLR,
 838         MISCREG_ICC_MGRPEN1,
 839         MISCREG_ICC_MSRE,
 840         MISCREG_ICC_PMR,
 841         MISCREG_ICC_RPR,
 842         MISCREG_ICC_SGI0R,
 843         MISCREG_ICC_SGI1R,
 844         MISCREG_ICC_SRE,
 845         MISCREG_ICC_SRE_NS,
 846         MISCREG_ICC_SRE_S,
 847
 848         MISCREG_ICH_AP0R0,
 849         MISCREG_ICH_AP0R1,
 850         MISCREG_ICH_AP0R2,
 851         MISCREG_ICH_AP0R3,
 852         MISCREG_ICH_AP1R0,
 853         MISCREG_ICH_AP1R1,
 854         MISCREG_ICH_AP1R2,
 855         MISCREG_ICH_AP1R3,
 856         MISCREG_ICH_HCR,
 857         MISCREG_ICH_VTR,
 858         MISCREG_ICH_MISR,
 859         MISCREG_ICH_EISR,
 860         MISCREG_ICH_ELRSR,
 861         MISCREG_ICH_VMCR,
 862         MISCREG_ICH_LR0,
 863         MISCREG_ICH_LR1,
 864         MISCREG_ICH_LR2,
 865         MISCREG_ICH_LR3,
 866         MISCREG_ICH_LR4,
 867         MISCREG_ICH_LR5,
 868         MISCREG_ICH_LR6,
 869         MISCREG_ICH_LR7,
 870         MISCREG_ICH_LR8,
 871         MISCREG_ICH_LR9,
 872         MISCREG_ICH_LR10,
 873         MISCREG_ICH_LR11,
 874         MISCREG_ICH_LR12,
 875         MISCREG_ICH_LR13,
 876         MISCREG_ICH_LR14,
 877         MISCREG_ICH_LR15,
 878         MISCREG_ICH_LRC0,
 879         MISCREG_ICH_LRC1,
 880         MISCREG_ICH_LRC2,
 881         MISCREG_ICH_LRC3,
 882         MISCREG_ICH_LRC4,
 883         MISCREG_ICH_LRC5,
 884         MISCREG_ICH_LRC6,
 885         MISCREG_ICH_LRC7,
 886         MISCREG_ICH_LRC8,
 887         MISCREG_ICH_LRC9,
 888         MISCREG_ICH_LRC10,
 889         MISCREG_ICH_LRC11,
 890         MISCREG_ICH_LRC12,
 891         MISCREG_ICH_LRC13,
 892         MISCREG_ICH_LRC14,
 893         MISCREG_ICH_LRC15,
 894
 895         // SVE
 896         MISCREG_ID_AA64ZFR0_EL1,
 897         MISCREG_ZCR_EL3,
 898         MISCREG_ZCR_EL2,
 899         MISCREG_ZCR_EL12,
 900         MISCREG_ZCR_EL1,
 901
 902         // NUM_PHYS_MISCREGS specifies the number of actual physical
 903         // registers, not considering the following pseudo-registers
 904         // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
 905         // Checkpointing should use this physical index when
 906         // saving/restoring register values.
 907         NUM_PHYS_MISCREGS,
 908
 909         // Dummy registers
 910         MISCREG_NOP,
 911         MISCREG_RAZ,
 912         MISCREG_CP14_UNIMPL,
 913         MISCREG_CP15_UNIMPL,
 914         MISCREG_UNKNOWN,
 915
 916         // Implementation defined register: this represent
 917         // a pool of unimplemented registers whose access can throw
 918         // either UNDEFINED or hypervisor trap exception.
 919         MISCREG_IMPDEF_UNIMPL,
 920
 921         // RAS extension (unimplemented)
 922         MISCREG_ERRIDR_EL1,
 923         MISCREG_ERRSELR_EL1,
 924         MISCREG_ERXFR_EL1,
 925         MISCREG_ERXCTLR_EL1,
 926         MISCREG_ERXSTATUS_EL1,
 927         MISCREG_ERXADDR_EL1,
 928         MISCREG_ERXMISC0_EL1,
 929         MISCREG_ERXMISC1_EL1,
 930         MISCREG_DISR_EL1,
 931         MISCREG_VSESR_EL2,
 932         MISCREG_VDISR_EL2,
 933
 934         // PSTATE
 935         MISCREG_PAN,
 936
 937         // Total number of Misc Registers: Physical + Dummy
 938         NUM_MISCREGS
 939     };
 940
 941     enum MiscRegInfo {
 942         MISCREG_IMPLEMENTED,
 943         MISCREG_UNVERIFIABLE,   // Does the value change on every read (e.g. a
 944                                 // arch generic counter)
 945         MISCREG_WARN_NOT_FAIL,  // If MISCREG_IMPLEMENTED is deasserted, it
 946                                 // tells whether the instruction should raise a
 947                                 // warning or fail
 948         MISCREG_MUTEX,  // True if the register corresponds to a pair of
 949                         // mutually exclusive registers
 950         MISCREG_BANKED,  // True if the register is banked between the two
 951                          // security states, and this is the parent node of the
 952                          // two banked registers
 953         MISCREG_BANKED64, // True if the register is banked between the two
 954                           // security states, and this is the parent node of
 955                           // the two banked registers. Used in AA64 only.
 956         MISCREG_BANKED_CHILD, // The entry is one of the child registers that
 957                               // forms a banked set of regs (along with the
 958                               // other child regs)
 959
 960         // Access permissions
 961         // User mode
 962         MISCREG_USR_NS_RD,
 963         MISCREG_USR_NS_WR,
 964         MISCREG_USR_S_RD,
 965         MISCREG_USR_S_WR,
 966         // Privileged modes other than hypervisor or monitor
 967         MISCREG_PRI_NS_RD,
 968         MISCREG_PRI_NS_WR,
 969         MISCREG_PRI_S_RD,
 970         MISCREG_PRI_S_WR,
 971         // Hypervisor mode
 972         MISCREG_HYP_RD,
 973         MISCREG_HYP_WR,
 974         // Monitor mode, SCR.NS == 0
 975         MISCREG_MON_NS0_RD,
 976         MISCREG_MON_NS0_WR,
 977         // Monitor mode, SCR.NS == 1
 978         MISCREG_MON_NS1_RD,
 979         MISCREG_MON_NS1_WR,
 980
 981         NUM_MISCREG_INFOS
 982     };
 983
 984     extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
 985
 986     // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
 987     MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
 988                                unsigned crm, unsigned opc2);
 989     MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
 990                                      unsigned crn, unsigned crm,
 991                                      unsigned op2);
 992     // Whether a particular AArch64 system register is -always- read only.
 993     bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
 994
 995     // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
 996     MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
 997                                unsigned crm, unsigned opc2);
 998
 999     // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
1000     MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
1001
1002
1003     const char * const miscRegName[] = {
1004         "cpsr",
1005         "spsr",
1006         "spsr_fiq",
1007         "spsr_irq",
1008         "spsr_svc",
1009         "spsr_mon",
1010         "spsr_abt",
1011         "spsr_hyp",
1012         "spsr_und",
1013         "elr_hyp",
1014         "fpsid",
1015         "fpscr",
1016         "mvfr1",
1017         "mvfr0",
1018         "fpexc",
1019
1020         // Helper registers
1021         "cpsr_mode",
1022         "cpsr_q",
1023         "fpscr_exc",
1024         "fpscr_qc",
1025         "lockaddr",
1026         "lockflag",
1027         "prrr_mair0",
1028         "prrr_mair0_ns",
1029         "prrr_mair0_s",
1030         "nmrr_mair1",
1031         "nmrr_mair1_ns",
1032         "nmrr_mair1_s",
1033         "pmxevtyper_pmccfiltr",
1034         "sctlr_rst",
1035         "sev_mailbox",
1036
1037         // AArch32 CP14 registers
1038         "dbgdidr",
1039         "dbgdscrint",
1040         "dbgdccint",
1041         "dbgdtrtxint",
1042         "dbgdtrrxint",
1043         "dbgwfar",
1044         "dbgvcr",
1045         "dbgdtrrxext",
1046         "dbgdscrext",
1047         "dbgdtrtxext",
1048         "dbgoseccr",
1049         "dbgbvr0",
1050         "dbgbvr1",
1051         "dbgbvr2",
1052         "dbgbvr3",
1053         "dbgbvr4",
1054         "dbgbvr5",
1055         "dbgbcr0",
1056         "dbgbcr1",
1057         "dbgbcr2",
1058         "dbgbcr3",
1059         "dbgbcr4",
1060         "dbgbcr5",
1061         "dbgwvr0",
1062         "dbgwvr1",
1063         "dbgwvr2",
1064         "dbgwvr3",
1065         "dbgwcr0",
1066         "dbgwcr1",
1067         "dbgwcr2",
1068         "dbgwcr3",
1069         "dbgdrar",
1070         "dbgbxvr4",
1071         "dbgbxvr5",
1072         "dbgoslar",
1073         "dbgoslsr",
1074         "dbgosdlr",
1075         "dbgprcr",
1076         "dbgdsar",
1077         "dbgclaimset",
1078         "dbgclaimclr",
1079         "dbgauthstatus",
1080         "dbgdevid2",
1081         "dbgdevid1",
1082         "dbgdevid0",
1083         "teecr",
1084         "jidr",
1085         "teehbr",
1086         "joscr",
1087         "jmcr",
1088
1089         // AArch32 CP15 registers
1090         "midr",
1091         "ctr",
1092         "tcmtr",
1093         "tlbtr",
1094         "mpidr",
1095         "revidr",
1096         "id_pfr0",
1097         "id_pfr1",
1098         "id_dfr0",
1099         "id_afr0",
1100         "id_mmfr0",
1101         "id_mmfr1",
1102         "id_mmfr2",
1103         "id_mmfr3",
1104         "id_isar0",
1105         "id_isar1",
1106         "id_isar2",
1107         "id_isar3",
1108         "id_isar4",
1109         "id_isar5",
1110         "ccsidr",
1111         "clidr",
1112         "aidr",
1113         "csselr",
1114         "csselr_ns",
1115         "csselr_s",
1116         "vpidr",
1117         "vmpidr",
1118         "sctlr",
1119         "sctlr_ns",
1120         "sctlr_s",
1121         "actlr",
1122         "actlr_ns",
1123         "actlr_s",
1124         "cpacr",
1125         "scr",
1126         "sder",
1127         "nsacr",
1128         "hsctlr",
1129         "hactlr",
1130         "hcr",
1131         "hcr2",
1132         "hdcr",
1133         "hcptr",
1134         "hstr",
1135         "hacr",
1136         "ttbr0",
1137         "ttbr0_ns",
1138         "ttbr0_s",
1139         "ttbr1",
1140         "ttbr1_ns",
1141         "ttbr1_s",
1142         "ttbcr",
1143         "ttbcr_ns",
1144         "ttbcr_s",
1145         "htcr",
1146         "vtcr",
1147         "dacr",
1148         "dacr_ns",
1149         "dacr_s",
1150         "dfsr",
1151         "dfsr_ns",
1152         "dfsr_s",
1153         "ifsr",
1154         "ifsr_ns",
1155         "ifsr_s",
1156         "adfsr",
1157         "adfsr_ns",
1158         "adfsr_s",
1159         "aifsr",
1160         "aifsr_ns",
1161         "aifsr_s",
1162         "hadfsr",
1163         "haifsr",
1164         "hsr",
1165         "dfar",
1166         "dfar_ns",
1167         "dfar_s",
1168         "ifar",
1169         "ifar_ns",
1170         "ifar_s",
1171         "hdfar",
1172         "hifar",
1173         "hpfar",
1174         "icialluis",
1175         "bpiallis",
1176         "par",
1177         "par_ns",
1178         "par_s",
1179         "iciallu",
1180         "icimvau",
1181         "cp15isb",
1182         "bpiall",
1183         "bpimva",
1184         "dcimvac",
1185         "dcisw",
1186         "ats1cpr",
1187         "ats1cpw",
1188         "ats1cur",
1189         "ats1cuw",
1190         "ats12nsopr",
1191         "ats12nsopw",
1192         "ats12nsour",
1193         "ats12nsouw",
1194         "dccmvac",
1195         "dccsw",
1196         "cp15dsb",
1197         "cp15dmb",
1198         "dccmvau",
1199         "dccimvac",
1200         "dccisw",
1201         "ats1hr",
1202         "ats1hw",
1203         "tlbiallis",
1204         "tlbimvais",
1205         "tlbiasidis",
1206         "tlbimvaais",
1207         "tlbimvalis",
1208         "tlbimvaalis",
1209         "itlbiall",
1210         "itlbimva",
1211         "itlbiasid",
1212         "dtlbiall",
1213         "dtlbimva",
1214         "dtlbiasid",
1215         "tlbiall",
1216         "tlbimva",
1217         "tlbiasid",
1218         "tlbimvaa",
1219         "tlbimval",
1220         "tlbimvaal",
1221         "tlbiipas2is",
1222         "tlbiipas2lis",
1223         "tlbiallhis",
1224         "tlbimvahis",
1225         "tlbiallnsnhis",
1226         "tlbimvalhis",
1227         "tlbiipas2",
1228         "tlbiipas2l",
1229         "tlbiallh",
1230         "tlbimvah",
1231         "tlbiallnsnh",
1232         "tlbimvalh",
1233         "pmcr",
1234         "pmcntenset",
1235         "pmcntenclr",
1236         "pmovsr",
1237         "pmswinc",
1238         "pmselr",
1239         "pmceid0",
1240         "pmceid1",
1241         "pmccntr",
1242         "pmxevtyper",
1243         "pmccfiltr",
1244         "pmxevcntr",
1245         "pmuserenr",
1246         "pmintenset",
1247         "pmintenclr",
1248         "pmovsset",
1249         "l2ctlr",
1250         "l2ectlr",
1251         "prrr",
1252         "prrr_ns",
1253         "prrr_s",
1254         "mair0",
1255         "mair0_ns",
1256         "mair0_s",
1257         "nmrr",
1258         "nmrr_ns",
1259         "nmrr_s",
1260         "mair1",
1261         "mair1_ns",
1262         "mair1_s",
1263         "amair0",
1264         "amair0_ns",
1265         "amair0_s",
1266         "amair1",
1267         "amair1_ns",
1268         "amair1_s",
1269         "hmair0",
1270         "hmair1",
1271         "hamair0",
1272         "hamair1",
1273         "vbar",
1274         "vbar_ns",
1275         "vbar_s",
1276         "mvbar",
1277         "rmr",
1278         "isr",
1279         "hvbar",
1280         "fcseidr",
1281         "contextidr",
1282         "contextidr_ns",
1283         "contextidr_s",
1284         "tpidrurw",
1285         "tpidrurw_ns",
1286         "tpidrurw_s",
1287         "tpidruro",
1288         "tpidruro_ns",
1289         "tpidruro_s",
1290         "tpidrprw",
1291         "tpidrprw_ns",
1292         "tpidrprw_s",
1293         "htpidr",
1294         "cntfrq",
1295         "cntkctl",
1296         "cntp_tval",
1297         "cntp_tval_ns",
1298         "cntp_tval_s",
1299         "cntp_ctl",
1300         "cntp_ctl_ns",
1301         "cntp_ctl_s",
1302         "cntv_tval",
1303         "cntv_ctl",
1304         "cnthctl",
1305         "cnthp_tval",
1306         "cnthp_ctl",
1307         "il1data0",
1308         "il1data1",
1309         "il1data2",
1310         "il1data3",
1311         "dl1data0",
1312         "dl1data1",
1313         "dl1data2",
1314         "dl1data3",
1315         "dl1data4",
1316         "ramindex",
1317         "l2actlr",
1318         "cbar",
1319         "httbr",
1320         "vttbr",
1321         "cntpct",
1322         "cntvct",
1323         "cntp_cval",
1324         "cntp_cval_ns",
1325         "cntp_cval_s",
1326         "cntv_cval",
1327         "cntvoff",
1328         "cnthp_cval",
1329         "cpumerrsr",
1330         "l2merrsr",
1331
1332         // AArch64 registers (Op0=2)
1333         "mdccint_el1",
1334         "osdtrrx_el1",
1335         "mdscr_el1",
1336         "osdtrtx_el1",
1337         "oseccr_el1",
1338         "dbgbvr0_el1",
1339         "dbgbvr1_el1",
1340         "dbgbvr2_el1",
1341         "dbgbvr3_el1",
1342         "dbgbvr4_el1",
1343         "dbgbvr5_el1",
1344         "dbgbcr0_el1",
1345         "dbgbcr1_el1",
1346         "dbgbcr2_el1",
1347         "dbgbcr3_el1",
1348         "dbgbcr4_el1",
1349         "dbgbcr5_el1",
1350         "dbgwvr0_el1",
1351         "dbgwvr1_el1",
1352         "dbgwvr2_el1",
1353         "dbgwvr3_el1",
1354         "dbgwcr0_el1",
1355         "dbgwcr1_el1",
1356         "dbgwcr2_el1",
1357         "dbgwcr3_el1",
1358         "mdccsr_el0",
1359         "mddtr_el0",
1360         "mddtrtx_el0",
1361         "mddtrrx_el0",
1362         "dbgvcr32_el2",
1363         "mdrar_el1",
1364         "oslar_el1",
1365         "oslsr_el1",
1366         "osdlr_el1",
1367         "dbgprcr_el1",
1368         "dbgclaimset_el1",
1369         "dbgclaimclr_el1",
1370         "dbgauthstatus_el1",
1371         "teecr32_el1",
1372         "teehbr32_el1",
1373
1374         // AArch64 registers (Op0=1,3)
1375         "midr_el1",
1376         "mpidr_el1",
1377         "revidr_el1",
1378         "id_pfr0_el1",
1379         "id_pfr1_el1",
1380         "id_dfr0_el1",
1381         "id_afr0_el1",
1382         "id_mmfr0_el1",
1383         "id_mmfr1_el1",
1384         "id_mmfr2_el1",
1385         "id_mmfr3_el1",
1386         "id_isar0_el1",
1387         "id_isar1_el1",
1388         "id_isar2_el1",
1389         "id_isar3_el1",
1390         "id_isar4_el1",
1391         "id_isar5_el1",
1392         "mvfr0_el1",
1393         "mvfr1_el1",
1394         "mvfr2_el1",
1395         "id_aa64pfr0_el1",
1396         "id_aa64pfr1_el1",
1397         "id_aa64dfr0_el1",
1398         "id_aa64dfr1_el1",
1399         "id_aa64afr0_el1",
1400         "id_aa64afr1_el1",
1401         "id_aa64isar0_el1",
1402         "id_aa64isar1_el1",
1403         "id_aa64mmfr0_el1",
1404         "id_aa64mmfr1_el1",
1405         "ccsidr_el1",
1406         "clidr_el1",
1407         "aidr_el1",
1408         "csselr_el1",
1409         "ctr_el0",
1410         "dczid_el0",
1411         "vpidr_el2",
1412         "vmpidr_el2",
1413         "sctlr_el1",
1414         "actlr_el1",
1415         "cpacr_el1",
1416         "sctlr_el2",
1417         "actlr_el2",
1418         "hcr_el2",
1419         "mdcr_el2",
1420         "cptr_el2",
1421         "hstr_el2",
1422         "hacr_el2",
1423         "sctlr_el3",
1424         "actlr_el3",
1425         "scr_el3",
1426         "sder32_el3",
1427         "cptr_el3",
1428         "mdcr_el3",
1429         "ttbr0_el1",
1430         "ttbr1_el1",
1431         "tcr_el1",
1432         "ttbr0_el2",
1433         "tcr_el2",
1434         "vttbr_el2",
1435         "vtcr_el2",
1436         "ttbr0_el3",
1437         "tcr_el3",
1438         "dacr32_el2",
1439         "spsr_el1",
1440         "elr_el1",
1441         "sp_el0",
1442         "spsel",
1443         "currentel",
1444         "nzcv",
1445         "daif",
1446         "fpcr",
1447         "fpsr",
1448         "dspsr_el0",
1449         "dlr_el0",
1450         "spsr_el2",
1451         "elr_el2",
1452         "sp_el1",
1453         "spsr_irq_aa64",
1454         "spsr_abt_aa64",
1455         "spsr_und_aa64",
1456         "spsr_fiq_aa64",
1457         "spsr_el3",
1458         "elr_el3",
1459         "sp_el2",
1460         "afsr0_el1",
1461         "afsr1_el1",
1462         "esr_el1",
1463         "ifsr32_el2",
1464         "afsr0_el2",
1465         "afsr1_el2",
1466         "esr_el2",
1467         "fpexc32_el2",
1468         "afsr0_el3",
1469         "afsr1_el3",
1470         "esr_el3",
1471         "far_el1",
1472         "far_el2",
1473         "hpfar_el2",
1474         "far_el3",
1475         "ic_ialluis",
1476         "par_el1",
1477         "ic_iallu",
1478         "dc_ivac_xt",
1479         "dc_isw_xt",
1480         "at_s1e1r_xt",
1481         "at_s1e1w_xt",
1482         "at_s1e0r_xt",
1483         "at_s1e0w_xt",
1484         "dc_csw_xt",
1485         "dc_cisw_xt",
1486         "dc_zva_xt",
1487         "ic_ivau_xt",
1488         "dc_cvac_xt",
1489         "dc_cvau_xt",
1490         "dc_civac_xt",
1491         "at_s1e2r_xt",
1492         "at_s1e2w_xt",
1493         "at_s12e1r_xt",
1494         "at_s12e1w_xt",
1495         "at_s12e0r_xt",
1496         "at_s12e0w_xt",
1497         "at_s1e3r_xt",
1498         "at_s1e3w_xt",
1499         "tlbi_vmalle1is",
1500         "tlbi_vae1is_xt",
1501         "tlbi_aside1is_xt",
1502         "tlbi_vaae1is_xt",
1503         "tlbi_vale1is_xt",
1504         "tlbi_vaale1is_xt",
1505         "tlbi_vmalle1",
1506         "tlbi_vae1_xt",
1507         "tlbi_aside1_xt",
1508         "tlbi_vaae1_xt",
1509         "tlbi_vale1_xt",
1510         "tlbi_vaale1_xt",
1511         "tlbi_ipas2e1is_xt",
1512         "tlbi_ipas2le1is_xt",
1513         "tlbi_alle2is",
1514         "tlbi_vae2is_xt",
1515         "tlbi_alle1is",
1516         "tlbi_vale2is_xt",
1517         "tlbi_vmalls12e1is",
1518         "tlbi_ipas2e1_xt",
1519         "tlbi_ipas2le1_xt",
1520         "tlbi_alle2",
1521         "tlbi_vae2_xt",
1522         "tlbi_alle1",
1523         "tlbi_vale2_xt",
1524         "tlbi_vmalls12e1",
1525         "tlbi_alle3is",
1526         "tlbi_vae3is_xt",
1527         "tlbi_vale3is_xt",
1528         "tlbi_alle3",
1529         "tlbi_vae3_xt",
1530         "tlbi_vale3_xt",
1531         "pmintenset_el1",
1532         "pmintenclr_el1",
1533         "pmcr_el0",
1534         "pmcntenset_el0",
1535         "pmcntenclr_el0",
1536         "pmovsclr_el0",
1537         "pmswinc_el0",
1538         "pmselr_el0",
1539         "pmceid0_el0",
1540         "pmceid1_el0",
1541         "pmccntr_el0",
1542         "pmxevtyper_el0",
1543         "pmccfiltr_el0",
1544         "pmxevcntr_el0",
1545         "pmuserenr_el0",
1546         "pmovsset_el0",
1547         "mair_el1",
1548         "amair_el1",
1549         "mair_el2",
1550         "amair_el2",
1551         "mair_el3",
1552         "amair_el3",
1553         "l2ctlr_el1",
1554         "l2ectlr_el1",
1555         "vbar_el1",
1556         "rvbar_el1",
1557         "isr_el1",
1558         "vbar_el2",
1559         "rvbar_el2",
1560         "vbar_el3",
1561         "rvbar_el3",
1562         "rmr_el3",
1563         "contextidr_el1",
1564         "tpidr_el1",
1565         "tpidr_el0",
1566         "tpidrro_el0",
1567         "tpidr_el2",
1568         "tpidr_el3",
1569         "cntkctl_el1",
1570         "cntfrq_el0",
1571         "cntpct_el0",
1572         "cntvct_el0",
1573         "cntp_tval_el0",
1574         "cntp_ctl_el0",
1575         "cntp_cval_el0",
1576         "cntv_tval_el0",
1577         "cntv_ctl_el0",
1578         "cntv_cval_el0",
1579         "pmevcntr0_el0",
1580         "pmevcntr1_el0",
1581         "pmevcntr2_el0",
1582         "pmevcntr3_el0",
1583         "pmevcntr4_el0",
1584         "pmevcntr5_el0",
1585         "pmevtyper0_el0",
1586         "pmevtyper1_el0",
1587         "pmevtyper2_el0",
1588         "pmevtyper3_el0",
1589         "pmevtyper4_el0",
1590         "pmevtyper5_el0",
1591         "cntvoff_el2",
1592         "cnthctl_el2",
1593         "cnthp_tval_el2",
1594         "cnthp_ctl_el2",
1595         "cnthp_cval_el2",
1596         "cntps_tval_el1",
1597         "cntps_ctl_el1",
1598         "cntps_cval_el1",
1599         "il1data0_el1",
1600         "il1data1_el1",
1601         "il1data2_el1",
1602         "il1data3_el1",
1603         "dl1data0_el1",
1604         "dl1data1_el1",
1605         "dl1data2_el1",
1606         "dl1data3_el1",
1607         "dl1data4_el1",
1608         "l2actlr_el1",
1609         "cpuactlr_el1",
1610         "cpuectlr_el1",
1611         "cpumerrsr_el1",
1612         "l2merrsr_el1",
1613         "cbar_el1",
1614         "contextidr_el2",
1615
1616         "ttbr1_el2",
1617         "cnthv_ctl_el2",
1618         "cnthv_cval_el2",
1619         "cnthv_tval_el2",
1620         "id_aa64mmfr2_el1",
1621
1622         // GICv3, CPU interface
1623         "icc_pmr_el1",
1624         "icc_iar0_el1",
1625         "icc_eoir0_el1",
1626         "icc_hppir0_el1",
1627         "icc_bpr0_el1",
1628         "icc_ap0r0_el1",
1629         "icc_ap0r1_el1",
1630         "icc_ap0r2_el1",
1631         "icc_ap0r3_el1",
1632         "icc_ap1r0_el1",
1633         "icc_ap1r0_el1_ns",
1634         "icc_ap1r0_el1_s",
1635         "icc_ap1r1_el1",
1636         "icc_ap1r1_el1_ns",
1637         "icc_ap1r1_el1_s",
1638         "icc_ap1r2_el1",
1639         "icc_ap1r2_el1_ns",
1640         "icc_ap1r2_el1_s",
1641         "icc_ap1r3_el1",
1642         "icc_ap1r3_el1_ns",
1643         "icc_ap1r3_el1_s",
1644         "icc_dir_el1",
1645         "icc_rpr_el1",
1646         "icc_sgi1r_el1",
1647         "icc_asgi1r_el1",
1648         "icc_sgi0r_el1",
1649         "icc_iar1_el1",
1650         "icc_eoir1_el1",
1651         "icc_hppir1_el1",
1652         "icc_bpr1_el1",
1653         "icc_bpr1_el1_ns",
1654         "icc_bpr1_el1_s",
1655         "icc_ctlr_el1",
1656         "icc_ctlr_el1_ns",
1657         "icc_ctlr_el1_s",
1658         "icc_sre_el1",
1659         "icc_sre_el1_ns",
1660         "icc_sre_el1_s",
1661         "icc_igrpen0_el1",
1662         "icc_igrpen1_el1",
1663         "icc_igrpen1_el1_ns",
1664         "icc_igrpen1_el1_s",
1665         "icc_sre_el2",
1666         "icc_ctlr_el3",
1667         "icc_sre_el3",
1668         "icc_igrpen1_el3",
1669
1670         // GICv3, CPU interface, virtualization
1671         "ich_ap0r0_el2",
1672         "ich_ap0r1_el2",
1673         "ich_ap0r2_el2",
1674         "ich_ap0r3_el2",
1675         "ich_ap1r0_el2",
1676         "ich_ap1r1_el2",
1677         "ich_ap1r2_el2",
1678         "ich_ap1r3_el2",
1679         "ich_hcr_el2",
1680         "ich_vtr_el2",
1681         "ich_misr_el2",
1682         "ich_eisr_el2",
1683         "ich_elrsr_el2",
1684         "ich_vmcr_el2",
1685         "ich_lr0_el2",
1686         "ich_lr1_el2",
1687         "ich_lr2_el2",
1688         "ich_lr3_el2",
1689         "ich_lr4_el2",
1690         "ich_lr5_el2",
1691         "ich_lr6_el2",
1692         "ich_lr7_el2",
1693         "ich_lr8_el2",
1694         "ich_lr9_el2",
1695         "ich_lr10_el2",
1696         "ich_lr11_el2",
1697         "ich_lr12_el2",
1698         "ich_lr13_el2",
1699         "ich_lr14_el2",
1700         "ich_lr15_el2",
1701
1702         "icv_pmr_el1",
1703         "icv_iar0_el1",
1704         "icv_eoir0_el1",
1705         "icv_hppir0_el1",
1706         "icv_bpr0_el1",
1707         "icv_ap0r0_el1",
1708         "icv_ap0r1_el1",
1709         "icv_ap0r2_el1",
1710         "icv_ap0r3_el1",
1711         "icv_ap1r0_el1",
1712         "icv_ap1r0_el1_ns",
1713         "icv_ap1r0_el1_s",
1714         "icv_ap1r1_el1",
1715         "icv_ap1r1_el1_ns",
1716         "icv_ap1r1_el1_s",
1717         "icv_ap1r2_el1",
1718         "icv_ap1r2_el1_ns",
1719         "icv_ap1r2_el1_s",
1720         "icv_ap1r3_el1",
1721         "icv_ap1r3_el1_ns",
1722         "icv_ap1r3_el1_s",
1723         "icv_dir_el1",
1724         "icv_rpr_el1",
1725         "icv_sgi1r_el1",
1726         "icv_asgi1r_el1",
1727         "icv_sgi0r_el1",
1728         "icv_iar1_el1",
1729         "icv_eoir1_el1",
1730         "icv_hppir1_el1",
1731         "icv_bpr1_el1",
1732         "icv_bpr1_el1_ns",
1733         "icv_bpr1_el1_s",
1734         "icv_ctlr_el1",
1735         "icv_ctlr_el1_ns",
1736         "icv_ctlr_el1_s",
1737         "icv_sre_el1",
1738         "icv_sre_el1_ns",
1739         "icv_sre_el1_s",
1740         "icv_igrpen0_el1",
1741         "icv_igrpen1_el1",
1742         "icv_igrpen1_el1_ns",
1743         "icv_igrpen1_el1_s",
1744
1745         "icc_ap0r0",
1746         "icc_ap0r1",
1747         "icc_ap0r2",
1748         "icc_ap0r3",
1749         "icc_ap1r0",
1750         "icc_ap1r0_ns",
1751         "icc_ap1r0_s",
1752         "icc_ap1r1",
1753         "icc_ap1r1_ns",
1754         "icc_ap1r1_s",
1755         "icc_ap1r2",
1756         "icc_ap1r2_ns",
1757         "icc_ap1r2_s",
1758         "icc_ap1r3",
1759         "icc_ap1r3_ns",
1760         "icc_ap1r3_s",
1761         "icc_asgi1r",
1762         "icc_bpr0",
1763         "icc_bpr1",
1764         "icc_bpr1_ns",
1765         "icc_bpr1_s",
1766         "icc_ctlr",
1767         "icc_ctlr_ns",
1768         "icc_ctlr_s",
1769         "icc_dir",
1770         "icc_eoir0",
1771         "icc_eoir1",
1772         "icc_hppir0",
1773         "icc_hppir1",
1774         "icc_hsre",
1775         "icc_iar0",
1776         "icc_iar1",
1777         "icc_igrpen0",
1778         "icc_igrpen1",
1779         "icc_igrpen1_ns",
1780         "icc_igrpen1_s",
1781         "icc_mctlr",
1782         "icc_mgrpen1",
1783         "icc_msre",
1784         "icc_pmr",
1785         "icc_rpr",
1786         "icc_sgi0r",
1787         "icc_sgi1r",
1788         "icc_sre",
1789         "icc_sre_ns",
1790         "icc_sre_s",
1791
1792         "ich_ap0r0",
1793         "ich_ap0r1",
1794         "ich_ap0r2",
1795         "ich_ap0r3",
1796         "ich_ap1r0",
1797         "ich_ap1r1",
1798         "ich_ap1r2",
1799         "ich_ap1r3",
1800         "ich_hcr",
1801         "ich_vtr",
1802         "ich_misr",
1803         "ich_eisr",
1804         "ich_elrsr",
1805         "ich_vmcr",
1806         "ich_lr0",
1807         "ich_lr1",
1808         "ich_lr2",
1809         "ich_lr3",
1810         "ich_lr4",
1811         "ich_lr5",
1812         "ich_lr6",
1813         "ich_lr7",
1814         "ich_lr8",
1815         "ich_lr9",
1816         "ich_lr10",
1817         "ich_lr11",
1818         "ich_lr12",
1819         "ich_lr13",
1820         "ich_lr14",
1821         "ich_lr15",
1822         "ich_lrc0",
1823         "ich_lrc1",
1824         "ich_lrc2",
1825         "ich_lrc3",
1826         "ich_lrc4",
1827         "ich_lrc5",
1828         "ich_lrc6",
1829         "ich_lrc7",
1830         "ich_lrc8",
1831         "ich_lrc9",
1832         "ich_lrc10",
1833         "ich_lrc11",
1834         "ich_lrc12",
1835         "ich_lrc13",
1836         "ich_lrc14",
1837         "ich_lrc15",
1838
1839         "id_aa64zfr0_el1",
1840         "zcr_el3",
1841         "zcr_el2",
1842         "zcr_el12",
1843         "zcr_el1",
1844
1845         "num_phys_regs",
1846
1847         // Dummy registers
1848         "nop",
1849         "raz",
1850         "cp14_unimpl",
1851         "cp15_unimpl",
1852         "unknown",
1853         "impl_defined",
1854         "erridr_el1",
1855         "errselr_el1",
1856         "erxfr_el1",
1857         "erxctlr_el1",
1858         "erxstatus_el1",
1859         "erxaddr_el1",
1860         "erxmisc0_el1",
1861         "erxmisc1_el1",
1862         "disr_el1",
1863         "vsesr_el2",
1864         "vdisr_el2",
1865
1866         // PSTATE
1867         "pan",
1868     };
1869
1870     static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1871                   "The miscRegName array and NUM_MISCREGS are inconsistent.");
1872
1873     // This mask selects bits of the CPSR that actually go in the CondCodes
1874     // integer register to allow renaming.
1875     static const uint32_t CondCodesMask   = 0xF00F0000;
1876     static const uint32_t CpsrMaskQ       = 0x08000000;
1877
1878     // APSR (Application Program Status Register Mask). It is the user level
1879     // alias for the CPSR. The APSR is a subset of the CPSR. Although
1880     // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1881     // APSR:
1882     // Bit[9] returns the value of CPSR.E.
1883     // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1884     static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1885
1886     // CPSR (Current Program Status Register Mask).
1887     static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1888
1889     // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1890     // integer register to allow renaming.
1891     static const uint32_t FpCondCodesMask = 0xF0000000;
1892     // This mask selects the cumulative FP exception flags of the FPSCR.
1893     static const uint32_t FpscrExcMask = 0x0000009F;
1894     // This mask selects the cumulative saturation flag of the FPSCR.
1895     static const uint32_t FpscrQcMask = 0x08000000;
1896
1897     /**
1898      * Check for permission to read coprocessor registers.
1899      *
1900      * Checks whether an instruction at the current program mode has
1901      * permissions to read the coprocessor registers. This function
1902      * returns whether the check is undefined and if not whether the
1903      * read access is permitted.
1904      *
1905      * @param the misc reg indicating the coprocessor
1906      * @param the SCR
1907      * @param the CPSR
1908      * @return a tuple of booleans: can_read, undefined
1909      */
1910     std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1911                                            CPSR cpsr);
1912
1913     /**
1914      * Check for permission to write coprocessor registers.
1915      *
1916      * Checks whether an instruction at the current program mode has
1917      * permissions to write the coprocessor registers. This function
1918      * returns whether the check is undefined and if not whether the
1919      * write access is permitted.
1920      *
1921      * @param the misc reg indicating the coprocessor
1922      * @param the SCR
1923      * @param the CPSR
1924      * @return a tuple of booleans: can_write, undefined
1925      */
1926     std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1927                                              CPSR cpsr);
1928
1929     // Checks read access permissions to AArch64 system registers
1930     bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1931                               ThreadContext *tc);
1932
1933     // Checks write access permissions to AArch64 system registers
1934     bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1935                                ThreadContext *tc);
1936
1937     // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1938     // for MCR/MRC instructions
1939     int
1940     snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
1941
1942     // Flattens a misc reg index using the specified security state. This is
1943     // used for opperations (eg address translations) where the security
1944     // state of the register access may differ from the current state of the
1945     // processor
1946     int
1947     snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
1948
1949     int
1950     snsBankedIndex64(MiscRegIndex reg, ThreadContext *tc);
1951
1952     // Takes a misc reg index and returns the root reg if its one of a set of
1953     // banked registers
1954     void
1955     preUnflattenMiscReg();
1956
1957     int
1958     unflattenMiscReg(int reg);
1959
1960 }
1961
1962 #endif // __ARCH_ARM_MISCREGS_HH__