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arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register
[gem5.git] / src / arch / arm / miscregs.hh
1 /*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 * Giacomo Gabrielli
42 */
43 #ifndef __ARCH_ARM_MISCREGS_HH__
44 #define __ARCH_ARM_MISCREGS_HH__
45
46 #include <bitset>
47 #include <tuple>
48
49 #include "arch/arm/miscregs_types.hh"
50 #include "base/compiler.hh"
51
52 class ThreadContext;
53
54
55 namespace ArmISA
56 {
57 enum MiscRegIndex {
58 MISCREG_CPSR = 0, // 0
59 MISCREG_SPSR, // 1
60 MISCREG_SPSR_FIQ, // 2
61 MISCREG_SPSR_IRQ, // 3
62 MISCREG_SPSR_SVC, // 4
63 MISCREG_SPSR_MON, // 5
64 MISCREG_SPSR_ABT, // 6
65 MISCREG_SPSR_HYP, // 7
66 MISCREG_SPSR_UND, // 8
67 MISCREG_ELR_HYP, // 9
68 MISCREG_FPSID, // 10
69 MISCREG_FPSCR, // 11
70 MISCREG_MVFR1, // 12
71 MISCREG_MVFR0, // 13
72 MISCREG_FPEXC, // 14
73
74 // Helper registers
75 MISCREG_CPSR_MODE, // 15
76 MISCREG_CPSR_Q, // 16
77 MISCREG_FPSCR_EXC, // 17
78 MISCREG_FPSCR_QC, // 18
79 MISCREG_LOCKADDR, // 19
80 MISCREG_LOCKFLAG, // 20
81 MISCREG_PRRR_MAIR0, // 21
82 MISCREG_PRRR_MAIR0_NS, // 22
83 MISCREG_PRRR_MAIR0_S, // 23
84 MISCREG_NMRR_MAIR1, // 24
85 MISCREG_NMRR_MAIR1_NS, // 25
86 MISCREG_NMRR_MAIR1_S, // 26
87 MISCREG_PMXEVTYPER_PMCCFILTR, // 27
88 MISCREG_SCTLR_RST, // 28
89 MISCREG_SEV_MAILBOX, // 29
90
91 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
92 MISCREG_DBGDIDR, // 30
93 MISCREG_DBGDSCRint, // 31
94 MISCREG_DBGDCCINT, // 32
95 MISCREG_DBGDTRTXint, // 33
96 MISCREG_DBGDTRRXint, // 34
97 MISCREG_DBGWFAR, // 35
98 MISCREG_DBGVCR, // 36
99 MISCREG_DBGDTRRXext, // 37
100 MISCREG_DBGDSCRext, // 38
101 MISCREG_DBGDTRTXext, // 39
102 MISCREG_DBGOSECCR, // 40
103 MISCREG_DBGBVR0, // 41
104 MISCREG_DBGBVR1, // 42
105 MISCREG_DBGBVR2, // 43
106 MISCREG_DBGBVR3, // 44
107 MISCREG_DBGBVR4, // 45
108 MISCREG_DBGBVR5, // 46
109 MISCREG_DBGBCR0, // 47
110 MISCREG_DBGBCR1, // 48
111 MISCREG_DBGBCR2, // 49
112 MISCREG_DBGBCR3, // 50
113 MISCREG_DBGBCR4, // 51
114 MISCREG_DBGBCR5, // 52
115 MISCREG_DBGWVR0, // 53
116 MISCREG_DBGWVR1, // 54
117 MISCREG_DBGWVR2, // 55
118 MISCREG_DBGWVR3, // 56
119 MISCREG_DBGWCR0, // 57
120 MISCREG_DBGWCR1, // 58
121 MISCREG_DBGWCR2, // 59
122 MISCREG_DBGWCR3, // 60
123 MISCREG_DBGDRAR, // 61
124 MISCREG_DBGBXVR4, // 62
125 MISCREG_DBGBXVR5, // 63
126 MISCREG_DBGOSLAR, // 64
127 MISCREG_DBGOSLSR, // 65
128 MISCREG_DBGOSDLR, // 66
129 MISCREG_DBGPRCR, // 67
130 MISCREG_DBGDSAR, // 68
131 MISCREG_DBGCLAIMSET, // 69
132 MISCREG_DBGCLAIMCLR, // 70
133 MISCREG_DBGAUTHSTATUS, // 71
134 MISCREG_DBGDEVID2, // 72
135 MISCREG_DBGDEVID1, // 73
136 MISCREG_DBGDEVID0, // 74
137 MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+
138 MISCREG_JIDR, // 76
139 MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+
140 MISCREG_JOSCR, // 78
141 MISCREG_JMCR, // 79
142
143 // AArch32 CP15 registers (system control)
144 MISCREG_MIDR, // 80
145 MISCREG_CTR, // 81
146 MISCREG_TCMTR, // 82
147 MISCREG_TLBTR, // 83
148 MISCREG_MPIDR, // 84
149 MISCREG_REVIDR, // 85
150 MISCREG_ID_PFR0, // 86
151 MISCREG_ID_PFR1, // 87
152 MISCREG_ID_DFR0, // 88
153 MISCREG_ID_AFR0, // 89
154 MISCREG_ID_MMFR0, // 90
155 MISCREG_ID_MMFR1, // 91
156 MISCREG_ID_MMFR2, // 92
157 MISCREG_ID_MMFR3, // 93
158 MISCREG_ID_ISAR0, // 94
159 MISCREG_ID_ISAR1, // 95
160 MISCREG_ID_ISAR2, // 96
161 MISCREG_ID_ISAR3, // 97
162 MISCREG_ID_ISAR4, // 98
163 MISCREG_ID_ISAR5, // 99
164 MISCREG_CCSIDR, // 100
165 MISCREG_CLIDR, // 101
166 MISCREG_AIDR, // 102
167 MISCREG_CSSELR, // 103
168 MISCREG_CSSELR_NS, // 104
169 MISCREG_CSSELR_S, // 105
170 MISCREG_VPIDR, // 106
171 MISCREG_VMPIDR, // 107
172 MISCREG_SCTLR, // 108
173 MISCREG_SCTLR_NS, // 109
174 MISCREG_SCTLR_S, // 110
175 MISCREG_ACTLR, // 111
176 MISCREG_ACTLR_NS, // 112
177 MISCREG_ACTLR_S, // 113
178 MISCREG_CPACR, // 114
179 MISCREG_SCR, // 115
180 MISCREG_SDER, // 116
181 MISCREG_NSACR, // 117
182 MISCREG_HSCTLR, // 118
183 MISCREG_HACTLR, // 119
184 MISCREG_HCR, // 120
185 MISCREG_HDCR, // 121
186 MISCREG_HCPTR, // 122
187 MISCREG_HSTR, // 123
188 MISCREG_HACR, // 124
189 MISCREG_TTBR0, // 125
190 MISCREG_TTBR0_NS, // 126
191 MISCREG_TTBR0_S, // 127
192 MISCREG_TTBR1, // 128
193 MISCREG_TTBR1_NS, // 129
194 MISCREG_TTBR1_S, // 130
195 MISCREG_TTBCR, // 131
196 MISCREG_TTBCR_NS, // 132
197 MISCREG_TTBCR_S, // 133
198 MISCREG_HTCR, // 134
199 MISCREG_VTCR, // 135
200 MISCREG_DACR, // 136
201 MISCREG_DACR_NS, // 137
202 MISCREG_DACR_S, // 138
203 MISCREG_DFSR, // 139
204 MISCREG_DFSR_NS, // 140
205 MISCREG_DFSR_S, // 141
206 MISCREG_IFSR, // 142
207 MISCREG_IFSR_NS, // 143
208 MISCREG_IFSR_S, // 144
209 MISCREG_ADFSR, // 145
210 MISCREG_ADFSR_NS, // 146
211 MISCREG_ADFSR_S, // 147
212 MISCREG_AIFSR, // 148
213 MISCREG_AIFSR_NS, // 149
214 MISCREG_AIFSR_S, // 150
215 MISCREG_HADFSR, // 151
216 MISCREG_HAIFSR, // 152
217 MISCREG_HSR, // 153
218 MISCREG_DFAR, // 154
219 MISCREG_DFAR_NS, // 155
220 MISCREG_DFAR_S, // 156
221 MISCREG_IFAR, // 157
222 MISCREG_IFAR_NS, // 158
223 MISCREG_IFAR_S, // 159
224 MISCREG_HDFAR, // 160
225 MISCREG_HIFAR, // 161
226 MISCREG_HPFAR, // 162
227 MISCREG_ICIALLUIS, // 163
228 MISCREG_BPIALLIS, // 164
229 MISCREG_PAR, // 165
230 MISCREG_PAR_NS, // 166
231 MISCREG_PAR_S, // 167
232 MISCREG_ICIALLU, // 168
233 MISCREG_ICIMVAU, // 169
234 MISCREG_CP15ISB, // 170
235 MISCREG_BPIALL, // 171
236 MISCREG_BPIMVA, // 172
237 MISCREG_DCIMVAC, // 173
238 MISCREG_DCISW, // 174
239 MISCREG_ATS1CPR, // 175
240 MISCREG_ATS1CPW, // 176
241 MISCREG_ATS1CUR, // 177
242 MISCREG_ATS1CUW, // 178
243 MISCREG_ATS12NSOPR, // 179
244 MISCREG_ATS12NSOPW, // 180
245 MISCREG_ATS12NSOUR, // 181
246 MISCREG_ATS12NSOUW, // 182
247 MISCREG_DCCMVAC, // 183
248 MISCREG_DCCSW, // 184
249 MISCREG_CP15DSB, // 185
250 MISCREG_CP15DMB, // 186
251 MISCREG_DCCMVAU, // 187
252 MISCREG_DCCIMVAC, // 188
253 MISCREG_DCCISW, // 189
254 MISCREG_ATS1HR, // 190
255 MISCREG_ATS1HW, // 191
256 MISCREG_TLBIALLIS, // 192
257 MISCREG_TLBIMVAIS, // 193
258 MISCREG_TLBIASIDIS, // 194
259 MISCREG_TLBIMVAAIS, // 195
260 MISCREG_TLBIMVALIS, // 196
261 MISCREG_TLBIMVAALIS, // 197
262 MISCREG_ITLBIALL, // 198
263 MISCREG_ITLBIMVA, // 199
264 MISCREG_ITLBIASID, // 200
265 MISCREG_DTLBIALL, // 201
266 MISCREG_DTLBIMVA, // 202
267 MISCREG_DTLBIASID, // 203
268 MISCREG_TLBIALL, // 204
269 MISCREG_TLBIMVA, // 205
270 MISCREG_TLBIASID, // 206
271 MISCREG_TLBIMVAA, // 207
272 MISCREG_TLBIMVAL, // 208
273 MISCREG_TLBIMVAAL, // 209
274 MISCREG_TLBIIPAS2IS, // 210
275 MISCREG_TLBIIPAS2LIS, // 211
276 MISCREG_TLBIALLHIS, // 212
277 MISCREG_TLBIMVAHIS, // 213
278 MISCREG_TLBIALLNSNHIS, // 214
279 MISCREG_TLBIMVALHIS, // 215
280 MISCREG_TLBIIPAS2, // 216
281 MISCREG_TLBIIPAS2L, // 217
282 MISCREG_TLBIALLH, // 218
283 MISCREG_TLBIMVAH, // 219
284 MISCREG_TLBIALLNSNH, // 220
285 MISCREG_TLBIMVALH, // 221
286 MISCREG_PMCR, // 222
287 MISCREG_PMCNTENSET, // 223
288 MISCREG_PMCNTENCLR, // 224
289 MISCREG_PMOVSR, // 225
290 MISCREG_PMSWINC, // 226
291 MISCREG_PMSELR, // 227
292 MISCREG_PMCEID0, // 228
293 MISCREG_PMCEID1, // 229
294 MISCREG_PMCCNTR, // 230
295 MISCREG_PMXEVTYPER, // 231
296 MISCREG_PMCCFILTR, // 232
297 MISCREG_PMXEVCNTR, // 233
298 MISCREG_PMUSERENR, // 234
299 MISCREG_PMINTENSET, // 235
300 MISCREG_PMINTENCLR, // 236
301 MISCREG_PMOVSSET, // 237
302 MISCREG_L2CTLR, // 238
303 MISCREG_L2ECTLR, // 239
304 MISCREG_PRRR, // 240
305 MISCREG_PRRR_NS, // 241
306 MISCREG_PRRR_S, // 242
307 MISCREG_MAIR0, // 243
308 MISCREG_MAIR0_NS, // 244
309 MISCREG_MAIR0_S, // 245
310 MISCREG_NMRR, // 246
311 MISCREG_NMRR_NS, // 247
312 MISCREG_NMRR_S, // 248
313 MISCREG_MAIR1, // 249
314 MISCREG_MAIR1_NS, // 250
315 MISCREG_MAIR1_S, // 251
316 MISCREG_AMAIR0, // 252
317 MISCREG_AMAIR0_NS, // 253
318 MISCREG_AMAIR0_S, // 254
319 MISCREG_AMAIR1, // 255
320 MISCREG_AMAIR1_NS, // 256
321 MISCREG_AMAIR1_S, // 257
322 MISCREG_HMAIR0, // 258
323 MISCREG_HMAIR1, // 259
324 MISCREG_HAMAIR0, // 260
325 MISCREG_HAMAIR1, // 261
326 MISCREG_VBAR, // 262
327 MISCREG_VBAR_NS, // 263
328 MISCREG_VBAR_S, // 264
329 MISCREG_MVBAR, // 265
330 MISCREG_RMR, // 266
331 MISCREG_ISR, // 267
332 MISCREG_HVBAR, // 268
333 MISCREG_FCSEIDR, // 269
334 MISCREG_CONTEXTIDR, // 270
335 MISCREG_CONTEXTIDR_NS, // 271
336 MISCREG_CONTEXTIDR_S, // 272
337 MISCREG_TPIDRURW, // 273
338 MISCREG_TPIDRURW_NS, // 274
339 MISCREG_TPIDRURW_S, // 275
340 MISCREG_TPIDRURO, // 276
341 MISCREG_TPIDRURO_NS, // 277
342 MISCREG_TPIDRURO_S, // 278
343 MISCREG_TPIDRPRW, // 279
344 MISCREG_TPIDRPRW_NS, // 280
345 MISCREG_TPIDRPRW_S, // 281
346 MISCREG_HTPIDR, // 282
347 MISCREG_CNTFRQ, // 283
348 MISCREG_CNTKCTL, // 284
349 MISCREG_CNTP_TVAL, // 285
350 MISCREG_CNTP_TVAL_NS, // 286
351 MISCREG_CNTP_TVAL_S, // 287
352 MISCREG_CNTP_CTL, // 288
353 MISCREG_CNTP_CTL_NS, // 289
354 MISCREG_CNTP_CTL_S, // 290
355 MISCREG_CNTV_TVAL, // 291
356 MISCREG_CNTV_CTL, // 292
357 MISCREG_CNTHCTL, // 293
358 MISCREG_CNTHP_TVAL, // 294
359 MISCREG_CNTHP_CTL, // 295
360 MISCREG_IL1DATA0, // 296
361 MISCREG_IL1DATA1, // 297
362 MISCREG_IL1DATA2, // 298
363 MISCREG_IL1DATA3, // 299
364 MISCREG_DL1DATA0, // 300
365 MISCREG_DL1DATA1, // 301
366 MISCREG_DL1DATA2, // 302
367 MISCREG_DL1DATA3, // 303
368 MISCREG_DL1DATA4, // 304
369 MISCREG_RAMINDEX, // 305
370 MISCREG_L2ACTLR, // 306
371 MISCREG_CBAR, // 307
372 MISCREG_HTTBR, // 308
373 MISCREG_VTTBR, // 309
374 MISCREG_CNTPCT, // 310
375 MISCREG_CNTVCT, // 311
376 MISCREG_CNTP_CVAL, // 312
377 MISCREG_CNTP_CVAL_NS, // 313
378 MISCREG_CNTP_CVAL_S, // 314
379 MISCREG_CNTV_CVAL, // 315
380 MISCREG_CNTVOFF, // 316
381 MISCREG_CNTHP_CVAL, // 317
382 MISCREG_CPUMERRSR, // 318
383 MISCREG_L2MERRSR, // 319
384
385 // AArch64 registers (Op0=2)
386 MISCREG_MDCCINT_EL1, // 320
387 MISCREG_OSDTRRX_EL1, // 321
388 MISCREG_MDSCR_EL1, // 322
389 MISCREG_OSDTRTX_EL1, // 323
390 MISCREG_OSECCR_EL1, // 324
391 MISCREG_DBGBVR0_EL1, // 325
392 MISCREG_DBGBVR1_EL1, // 326
393 MISCREG_DBGBVR2_EL1, // 327
394 MISCREG_DBGBVR3_EL1, // 328
395 MISCREG_DBGBVR4_EL1, // 329
396 MISCREG_DBGBVR5_EL1, // 330
397 MISCREG_DBGBCR0_EL1, // 331
398 MISCREG_DBGBCR1_EL1, // 332
399 MISCREG_DBGBCR2_EL1, // 333
400 MISCREG_DBGBCR3_EL1, // 334
401 MISCREG_DBGBCR4_EL1, // 335
402 MISCREG_DBGBCR5_EL1, // 336
403 MISCREG_DBGWVR0_EL1, // 337
404 MISCREG_DBGWVR1_EL1, // 338
405 MISCREG_DBGWVR2_EL1, // 339
406 MISCREG_DBGWVR3_EL1, // 340
407 MISCREG_DBGWCR0_EL1, // 341
408 MISCREG_DBGWCR1_EL1, // 342
409 MISCREG_DBGWCR2_EL1, // 343
410 MISCREG_DBGWCR3_EL1, // 344
411 MISCREG_MDCCSR_EL0, // 345
412 MISCREG_MDDTR_EL0, // 346
413 MISCREG_MDDTRTX_EL0, // 347
414 MISCREG_MDDTRRX_EL0, // 348
415 MISCREG_DBGVCR32_EL2, // 349
416 MISCREG_MDRAR_EL1, // 350
417 MISCREG_OSLAR_EL1, // 351
418 MISCREG_OSLSR_EL1, // 352
419 MISCREG_OSDLR_EL1, // 353
420 MISCREG_DBGPRCR_EL1, // 354
421 MISCREG_DBGCLAIMSET_EL1, // 355
422 MISCREG_DBGCLAIMCLR_EL1, // 356
423 MISCREG_DBGAUTHSTATUS_EL1, // 357
424 MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+
425 MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+
426
427 // AArch64 registers (Op0=1,3)
428 MISCREG_MIDR_EL1, // 360
429 MISCREG_MPIDR_EL1, // 361
430 MISCREG_REVIDR_EL1, // 362
431 MISCREG_ID_PFR0_EL1, // 363
432 MISCREG_ID_PFR1_EL1, // 364
433 MISCREG_ID_DFR0_EL1, // 365
434 MISCREG_ID_AFR0_EL1, // 366
435 MISCREG_ID_MMFR0_EL1, // 367
436 MISCREG_ID_MMFR1_EL1, // 368
437 MISCREG_ID_MMFR2_EL1, // 369
438 MISCREG_ID_MMFR3_EL1, // 370
439 MISCREG_ID_ISAR0_EL1, // 371
440 MISCREG_ID_ISAR1_EL1, // 372
441 MISCREG_ID_ISAR2_EL1, // 373
442 MISCREG_ID_ISAR3_EL1, // 374
443 MISCREG_ID_ISAR4_EL1, // 375
444 MISCREG_ID_ISAR5_EL1, // 376
445 MISCREG_MVFR0_EL1, // 377
446 MISCREG_MVFR1_EL1, // 378
447 MISCREG_MVFR2_EL1, // 379
448 MISCREG_ID_AA64PFR0_EL1, // 380
449 MISCREG_ID_AA64PFR1_EL1, // 381
450 MISCREG_ID_AA64DFR0_EL1, // 382
451 MISCREG_ID_AA64DFR1_EL1, // 383
452 MISCREG_ID_AA64AFR0_EL1, // 384
453 MISCREG_ID_AA64AFR1_EL1, // 385
454 MISCREG_ID_AA64ISAR0_EL1, // 386
455 MISCREG_ID_AA64ISAR1_EL1, // 387
456 MISCREG_ID_AA64MMFR0_EL1, // 388
457 MISCREG_ID_AA64MMFR1_EL1, // 389
458 MISCREG_CCSIDR_EL1, // 390
459 MISCREG_CLIDR_EL1, // 391
460 MISCREG_AIDR_EL1, // 392
461 MISCREG_CSSELR_EL1, // 393
462 MISCREG_CTR_EL0, // 394
463 MISCREG_DCZID_EL0, // 395
464 MISCREG_VPIDR_EL2, // 396
465 MISCREG_VMPIDR_EL2, // 397
466 MISCREG_SCTLR_EL1, // 398
467 MISCREG_ACTLR_EL1, // 399
468 MISCREG_CPACR_EL1, // 400
469 MISCREG_SCTLR_EL2, // 401
470 MISCREG_ACTLR_EL2, // 402
471 MISCREG_HCR_EL2, // 403
472 MISCREG_MDCR_EL2, // 404
473 MISCREG_CPTR_EL2, // 405
474 MISCREG_HSTR_EL2, // 406
475 MISCREG_HACR_EL2, // 407
476 MISCREG_SCTLR_EL3, // 408
477 MISCREG_ACTLR_EL3, // 409
478 MISCREG_SCR_EL3, // 410
479 MISCREG_SDER32_EL3, // 411
480 MISCREG_CPTR_EL3, // 412
481 MISCREG_MDCR_EL3, // 413
482 MISCREG_TTBR0_EL1, // 414
483 MISCREG_TTBR1_EL1, // 415
484 MISCREG_TCR_EL1, // 416
485 MISCREG_TTBR0_EL2, // 417
486 MISCREG_TCR_EL2, // 418
487 MISCREG_VTTBR_EL2, // 419
488 MISCREG_VTCR_EL2, // 420
489 MISCREG_TTBR0_EL3, // 421
490 MISCREG_TCR_EL3, // 422
491 MISCREG_DACR32_EL2, // 423
492 MISCREG_SPSR_EL1, // 424
493 MISCREG_ELR_EL1, // 425
494 MISCREG_SP_EL0, // 426
495 MISCREG_SPSEL, // 427
496 MISCREG_CURRENTEL, // 428
497 MISCREG_NZCV, // 429
498 MISCREG_DAIF, // 430
499 MISCREG_FPCR, // 431
500 MISCREG_FPSR, // 432
501 MISCREG_DSPSR_EL0, // 433
502 MISCREG_DLR_EL0, // 434
503 MISCREG_SPSR_EL2, // 435
504 MISCREG_ELR_EL2, // 436
505 MISCREG_SP_EL1, // 437
506 MISCREG_SPSR_IRQ_AA64, // 438
507 MISCREG_SPSR_ABT_AA64, // 439
508 MISCREG_SPSR_UND_AA64, // 440
509 MISCREG_SPSR_FIQ_AA64, // 441
510 MISCREG_SPSR_EL3, // 442
511 MISCREG_ELR_EL3, // 443
512 MISCREG_SP_EL2, // 444
513 MISCREG_AFSR0_EL1, // 445
514 MISCREG_AFSR1_EL1, // 446
515 MISCREG_ESR_EL1, // 447
516 MISCREG_IFSR32_EL2, // 448
517 MISCREG_AFSR0_EL2, // 449
518 MISCREG_AFSR1_EL2, // 450
519 MISCREG_ESR_EL2, // 451
520 MISCREG_FPEXC32_EL2, // 452
521 MISCREG_AFSR0_EL3, // 453
522 MISCREG_AFSR1_EL3, // 454
523 MISCREG_ESR_EL3, // 455
524 MISCREG_FAR_EL1, // 456
525 MISCREG_FAR_EL2, // 457
526 MISCREG_HPFAR_EL2, // 458
527 MISCREG_FAR_EL3, // 459
528 MISCREG_IC_IALLUIS, // 460
529 MISCREG_PAR_EL1, // 461
530 MISCREG_IC_IALLU, // 462
531 MISCREG_DC_IVAC_Xt, // 463
532 MISCREG_DC_ISW_Xt, // 464
533 MISCREG_AT_S1E1R_Xt, // 465
534 MISCREG_AT_S1E1W_Xt, // 466
535 MISCREG_AT_S1E0R_Xt, // 467
536 MISCREG_AT_S1E0W_Xt, // 468
537 MISCREG_DC_CSW_Xt, // 469
538 MISCREG_DC_CISW_Xt, // 470
539 MISCREG_DC_ZVA_Xt, // 471
540 MISCREG_IC_IVAU_Xt, // 472
541 MISCREG_DC_CVAC_Xt, // 473
542 MISCREG_DC_CVAU_Xt, // 474
543 MISCREG_DC_CIVAC_Xt, // 475
544 MISCREG_AT_S1E2R_Xt, // 476
545 MISCREG_AT_S1E2W_Xt, // 477
546 MISCREG_AT_S12E1R_Xt, // 478
547 MISCREG_AT_S12E1W_Xt, // 479
548 MISCREG_AT_S12E0R_Xt, // 480
549 MISCREG_AT_S12E0W_Xt, // 481
550 MISCREG_AT_S1E3R_Xt, // 482
551 MISCREG_AT_S1E3W_Xt, // 483
552 MISCREG_TLBI_VMALLE1IS, // 484
553 MISCREG_TLBI_VAE1IS_Xt, // 485
554 MISCREG_TLBI_ASIDE1IS_Xt, // 486
555 MISCREG_TLBI_VAAE1IS_Xt, // 487
556 MISCREG_TLBI_VALE1IS_Xt, // 488
557 MISCREG_TLBI_VAALE1IS_Xt, // 489
558 MISCREG_TLBI_VMALLE1, // 490
559 MISCREG_TLBI_VAE1_Xt, // 491
560 MISCREG_TLBI_ASIDE1_Xt, // 492
561 MISCREG_TLBI_VAAE1_Xt, // 493
562 MISCREG_TLBI_VALE1_Xt, // 494
563 MISCREG_TLBI_VAALE1_Xt, // 495
564 MISCREG_TLBI_IPAS2E1IS_Xt, // 496
565 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497
566 MISCREG_TLBI_ALLE2IS, // 498
567 MISCREG_TLBI_VAE2IS_Xt, // 499
568 MISCREG_TLBI_ALLE1IS, // 500
569 MISCREG_TLBI_VALE2IS_Xt, // 501
570 MISCREG_TLBI_VMALLS12E1IS, // 502
571 MISCREG_TLBI_IPAS2E1_Xt, // 503
572 MISCREG_TLBI_IPAS2LE1_Xt, // 504
573 MISCREG_TLBI_ALLE2, // 505
574 MISCREG_TLBI_VAE2_Xt, // 506
575 MISCREG_TLBI_ALLE1, // 507
576 MISCREG_TLBI_VALE2_Xt, // 508
577 MISCREG_TLBI_VMALLS12E1, // 509
578 MISCREG_TLBI_ALLE3IS, // 510
579 MISCREG_TLBI_VAE3IS_Xt, // 511
580 MISCREG_TLBI_VALE3IS_Xt, // 512
581 MISCREG_TLBI_ALLE3, // 513
582 MISCREG_TLBI_VAE3_Xt, // 514
583 MISCREG_TLBI_VALE3_Xt, // 515
584 MISCREG_PMINTENSET_EL1, // 516
585 MISCREG_PMINTENCLR_EL1, // 517
586 MISCREG_PMCR_EL0, // 518
587 MISCREG_PMCNTENSET_EL0, // 519
588 MISCREG_PMCNTENCLR_EL0, // 520
589 MISCREG_PMOVSCLR_EL0, // 521
590 MISCREG_PMSWINC_EL0, // 522
591 MISCREG_PMSELR_EL0, // 523
592 MISCREG_PMCEID0_EL0, // 524
593 MISCREG_PMCEID1_EL0, // 525
594 MISCREG_PMCCNTR_EL0, // 526
595 MISCREG_PMXEVTYPER_EL0, // 527
596 MISCREG_PMCCFILTR_EL0, // 528
597 MISCREG_PMXEVCNTR_EL0, // 529
598 MISCREG_PMUSERENR_EL0, // 530
599 MISCREG_PMOVSSET_EL0, // 531
600 MISCREG_MAIR_EL1, // 532
601 MISCREG_AMAIR_EL1, // 533
602 MISCREG_MAIR_EL2, // 534
603 MISCREG_AMAIR_EL2, // 535
604 MISCREG_MAIR_EL3, // 536
605 MISCREG_AMAIR_EL3, // 537
606 MISCREG_L2CTLR_EL1, // 538
607 MISCREG_L2ECTLR_EL1, // 539
608 MISCREG_VBAR_EL1, // 540
609 MISCREG_RVBAR_EL1, // 541
610 MISCREG_ISR_EL1, // 542
611 MISCREG_VBAR_EL2, // 543
612 MISCREG_RVBAR_EL2, // 544
613 MISCREG_VBAR_EL3, // 545
614 MISCREG_RVBAR_EL3, // 546
615 MISCREG_RMR_EL3, // 547
616 MISCREG_CONTEXTIDR_EL1, // 548
617 MISCREG_TPIDR_EL1, // 549
618 MISCREG_TPIDR_EL0, // 550
619 MISCREG_TPIDRRO_EL0, // 551
620 MISCREG_TPIDR_EL2, // 552
621 MISCREG_TPIDR_EL3, // 553
622 MISCREG_CNTKCTL_EL1, // 554
623 MISCREG_CNTFRQ_EL0, // 555
624 MISCREG_CNTPCT_EL0, // 556
625 MISCREG_CNTVCT_EL0, // 557
626 MISCREG_CNTP_TVAL_EL0, // 558
627 MISCREG_CNTP_CTL_EL0, // 559
628 MISCREG_CNTP_CVAL_EL0, // 560
629 MISCREG_CNTV_TVAL_EL0, // 561
630 MISCREG_CNTV_CTL_EL0, // 562
631 MISCREG_CNTV_CVAL_EL0, // 563
632 MISCREG_PMEVCNTR0_EL0, // 564
633 MISCREG_PMEVCNTR1_EL0, // 565
634 MISCREG_PMEVCNTR2_EL0, // 566
635 MISCREG_PMEVCNTR3_EL0, // 567
636 MISCREG_PMEVCNTR4_EL0, // 568
637 MISCREG_PMEVCNTR5_EL0, // 569
638 MISCREG_PMEVTYPER0_EL0, // 570
639 MISCREG_PMEVTYPER1_EL0, // 571
640 MISCREG_PMEVTYPER2_EL0, // 572
641 MISCREG_PMEVTYPER3_EL0, // 573
642 MISCREG_PMEVTYPER4_EL0, // 574
643 MISCREG_PMEVTYPER5_EL0, // 575
644 MISCREG_CNTVOFF_EL2, // 576
645 MISCREG_CNTHCTL_EL2, // 577
646 MISCREG_CNTHP_TVAL_EL2, // 578
647 MISCREG_CNTHP_CTL_EL2, // 579
648 MISCREG_CNTHP_CVAL_EL2, // 580
649 MISCREG_CNTPS_TVAL_EL1, // 581
650 MISCREG_CNTPS_CTL_EL1, // 582
651 MISCREG_CNTPS_CVAL_EL1, // 583
652 MISCREG_IL1DATA0_EL1, // 584
653 MISCREG_IL1DATA1_EL1, // 585
654 MISCREG_IL1DATA2_EL1, // 586
655 MISCREG_IL1DATA3_EL1, // 587
656 MISCREG_DL1DATA0_EL1, // 588
657 MISCREG_DL1DATA1_EL1, // 589
658 MISCREG_DL1DATA2_EL1, // 590
659 MISCREG_DL1DATA3_EL1, // 591
660 MISCREG_DL1DATA4_EL1, // 592
661 MISCREG_L2ACTLR_EL1, // 593
662 MISCREG_CPUACTLR_EL1, // 594
663 MISCREG_CPUECTLR_EL1, // 595
664 MISCREG_CPUMERRSR_EL1, // 596
665 MISCREG_L2MERRSR_EL1, // 597
666 MISCREG_CBAR_EL1, // 598
667 MISCREG_CONTEXTIDR_EL2, // 599
668
669 // Introduced in ARMv8.1
670 MISCREG_TTBR1_EL2, // 600
671 MISCREG_CNTHV_CTL_EL2, // 601
672 MISCREG_CNTHV_CVAL_EL2, // 602
673 MISCREG_CNTHV_TVAL_EL2, // 603
674
675 MISCREG_ID_AA64MMFR2_EL1, // 604
676 // These MISCREG_FREESLOT are available Misc Register
677 // slots for future registers to be implemented.
678 MISCREG_FREESLOT_1, // 605
679
680 // NUM_PHYS_MISCREGS specifies the number of actual physical
681 // registers, not considering the following pseudo-registers
682 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
683 // Checkpointing should use this physical index when
684 // saving/restoring register values.
685 NUM_PHYS_MISCREGS = 606, // 606
686
687 // Dummy registers
688 MISCREG_NOP,
689 MISCREG_RAZ,
690 MISCREG_CP14_UNIMPL,
691 MISCREG_CP15_UNIMPL,
692 MISCREG_UNKNOWN,
693
694 // Implementation defined register: this represent
695 // a pool of unimplemented registers whose access can throw
696 // either UNDEFINED or hypervisor trap exception.
697 MISCREG_IMPDEF_UNIMPL,
698
699 // RAS extension (unimplemented)
700 MISCREG_ERRIDR_EL1,
701 MISCREG_ERRSELR_EL1,
702 MISCREG_ERXFR_EL1,
703 MISCREG_ERXCTLR_EL1,
704 MISCREG_ERXSTATUS_EL1,
705 MISCREG_ERXADDR_EL1,
706 MISCREG_ERXMISC0_EL1,
707 MISCREG_ERXMISC1_EL1,
708 MISCREG_DISR_EL1,
709 MISCREG_VSESR_EL2,
710 MISCREG_VDISR_EL2,
711
712 // Total number of Misc Registers: Physical + Dummy
713 NUM_MISCREGS
714 };
715
716 enum MiscRegInfo {
717 MISCREG_IMPLEMENTED,
718 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
719 // arch generic counter)
720 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
721 // tells whether the instruction should raise a
722 // warning or fail
723 MISCREG_MUTEX, // True if the register corresponds to a pair of
724 // mutually exclusive registers
725 MISCREG_BANKED, // True if the register is banked between the two
726 // security states, and this is the parent node of the
727 // two banked registers
728 MISCREG_BANKED_CHILD, // The entry is one of the child registers that
729 // forms a banked set of regs (along with the
730 // other child regs)
731
732 // Access permissions
733 // User mode
734 MISCREG_USR_NS_RD,
735 MISCREG_USR_NS_WR,
736 MISCREG_USR_S_RD,
737 MISCREG_USR_S_WR,
738 // Privileged modes other than hypervisor or monitor
739 MISCREG_PRI_NS_RD,
740 MISCREG_PRI_NS_WR,
741 MISCREG_PRI_S_RD,
742 MISCREG_PRI_S_WR,
743 // Hypervisor mode
744 MISCREG_HYP_RD,
745 MISCREG_HYP_WR,
746 // Monitor mode, SCR.NS == 0
747 MISCREG_MON_NS0_RD,
748 MISCREG_MON_NS0_WR,
749 // Monitor mode, SCR.NS == 1
750 MISCREG_MON_NS1_RD,
751 MISCREG_MON_NS1_WR,
752
753 NUM_MISCREG_INFOS
754 };
755
756 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
757
758 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
759 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
760 unsigned crm, unsigned opc2);
761 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
762 unsigned crn, unsigned crm,
763 unsigned op2);
764 // Whether a particular AArch64 system register is -always- read only.
765 bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
766
767 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
768 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
769 unsigned crm, unsigned opc2);
770
771 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
772 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
773
774
775 const char * const miscRegName[] = {
776 "cpsr",
777 "spsr",
778 "spsr_fiq",
779 "spsr_irq",
780 "spsr_svc",
781 "spsr_mon",
782 "spsr_abt",
783 "spsr_hyp",
784 "spsr_und",
785 "elr_hyp",
786 "fpsid",
787 "fpscr",
788 "mvfr1",
789 "mvfr0",
790 "fpexc",
791
792 // Helper registers
793 "cpsr_mode",
794 "cpsr_q",
795 "fpscr_exc",
796 "fpscr_qc",
797 "lockaddr",
798 "lockflag",
799 "prrr_mair0",
800 "prrr_mair0_ns",
801 "prrr_mair0_s",
802 "nmrr_mair1",
803 "nmrr_mair1_ns",
804 "nmrr_mair1_s",
805 "pmxevtyper_pmccfiltr",
806 "sctlr_rst",
807 "sev_mailbox",
808
809 // AArch32 CP14 registers
810 "dbgdidr",
811 "dbgdscrint",
812 "dbgdccint",
813 "dbgdtrtxint",
814 "dbgdtrrxint",
815 "dbgwfar",
816 "dbgvcr",
817 "dbgdtrrxext",
818 "dbgdscrext",
819 "dbgdtrtxext",
820 "dbgoseccr",
821 "dbgbvr0",
822 "dbgbvr1",
823 "dbgbvr2",
824 "dbgbvr3",
825 "dbgbvr4",
826 "dbgbvr5",
827 "dbgbcr0",
828 "dbgbcr1",
829 "dbgbcr2",
830 "dbgbcr3",
831 "dbgbcr4",
832 "dbgbcr5",
833 "dbgwvr0",
834 "dbgwvr1",
835 "dbgwvr2",
836 "dbgwvr3",
837 "dbgwcr0",
838 "dbgwcr1",
839 "dbgwcr2",
840 "dbgwcr3",
841 "dbgdrar",
842 "dbgbxvr4",
843 "dbgbxvr5",
844 "dbgoslar",
845 "dbgoslsr",
846 "dbgosdlr",
847 "dbgprcr",
848 "dbgdsar",
849 "dbgclaimset",
850 "dbgclaimclr",
851 "dbgauthstatus",
852 "dbgdevid2",
853 "dbgdevid1",
854 "dbgdevid0",
855 "teecr",
856 "jidr",
857 "teehbr",
858 "joscr",
859 "jmcr",
860
861 // AArch32 CP15 registers
862 "midr",
863 "ctr",
864 "tcmtr",
865 "tlbtr",
866 "mpidr",
867 "revidr",
868 "id_pfr0",
869 "id_pfr1",
870 "id_dfr0",
871 "id_afr0",
872 "id_mmfr0",
873 "id_mmfr1",
874 "id_mmfr2",
875 "id_mmfr3",
876 "id_isar0",
877 "id_isar1",
878 "id_isar2",
879 "id_isar3",
880 "id_isar4",
881 "id_isar5",
882 "ccsidr",
883 "clidr",
884 "aidr",
885 "csselr",
886 "csselr_ns",
887 "csselr_s",
888 "vpidr",
889 "vmpidr",
890 "sctlr",
891 "sctlr_ns",
892 "sctlr_s",
893 "actlr",
894 "actlr_ns",
895 "actlr_s",
896 "cpacr",
897 "scr",
898 "sder",
899 "nsacr",
900 "hsctlr",
901 "hactlr",
902 "hcr",
903 "hdcr",
904 "hcptr",
905 "hstr",
906 "hacr",
907 "ttbr0",
908 "ttbr0_ns",
909 "ttbr0_s",
910 "ttbr1",
911 "ttbr1_ns",
912 "ttbr1_s",
913 "ttbcr",
914 "ttbcr_ns",
915 "ttbcr_s",
916 "htcr",
917 "vtcr",
918 "dacr",
919 "dacr_ns",
920 "dacr_s",
921 "dfsr",
922 "dfsr_ns",
923 "dfsr_s",
924 "ifsr",
925 "ifsr_ns",
926 "ifsr_s",
927 "adfsr",
928 "adfsr_ns",
929 "adfsr_s",
930 "aifsr",
931 "aifsr_ns",
932 "aifsr_s",
933 "hadfsr",
934 "haifsr",
935 "hsr",
936 "dfar",
937 "dfar_ns",
938 "dfar_s",
939 "ifar",
940 "ifar_ns",
941 "ifar_s",
942 "hdfar",
943 "hifar",
944 "hpfar",
945 "icialluis",
946 "bpiallis",
947 "par",
948 "par_ns",
949 "par_s",
950 "iciallu",
951 "icimvau",
952 "cp15isb",
953 "bpiall",
954 "bpimva",
955 "dcimvac",
956 "dcisw",
957 "ats1cpr",
958 "ats1cpw",
959 "ats1cur",
960 "ats1cuw",
961 "ats12nsopr",
962 "ats12nsopw",
963 "ats12nsour",
964 "ats12nsouw",
965 "dccmvac",
966 "dccsw",
967 "cp15dsb",
968 "cp15dmb",
969 "dccmvau",
970 "dccimvac",
971 "dccisw",
972 "ats1hr",
973 "ats1hw",
974 "tlbiallis",
975 "tlbimvais",
976 "tlbiasidis",
977 "tlbimvaais",
978 "tlbimvalis",
979 "tlbimvaalis",
980 "itlbiall",
981 "itlbimva",
982 "itlbiasid",
983 "dtlbiall",
984 "dtlbimva",
985 "dtlbiasid",
986 "tlbiall",
987 "tlbimva",
988 "tlbiasid",
989 "tlbimvaa",
990 "tlbimval",
991 "tlbimvaal",
992 "tlbiipas2is",
993 "tlbiipas2lis",
994 "tlbiallhis",
995 "tlbimvahis",
996 "tlbiallnsnhis",
997 "tlbimvalhis",
998 "tlbiipas2",
999 "tlbiipas2l",
1000 "tlbiallh",
1001 "tlbimvah",
1002 "tlbiallnsnh",
1003 "tlbimvalh",
1004 "pmcr",
1005 "pmcntenset",
1006 "pmcntenclr",
1007 "pmovsr",
1008 "pmswinc",
1009 "pmselr",
1010 "pmceid0",
1011 "pmceid1",
1012 "pmccntr",
1013 "pmxevtyper",
1014 "pmccfiltr",
1015 "pmxevcntr",
1016 "pmuserenr",
1017 "pmintenset",
1018 "pmintenclr",
1019 "pmovsset",
1020 "l2ctlr",
1021 "l2ectlr",
1022 "prrr",
1023 "prrr_ns",
1024 "prrr_s",
1025 "mair0",
1026 "mair0_ns",
1027 "mair0_s",
1028 "nmrr",
1029 "nmrr_ns",
1030 "nmrr_s",
1031 "mair1",
1032 "mair1_ns",
1033 "mair1_s",
1034 "amair0",
1035 "amair0_ns",
1036 "amair0_s",
1037 "amair1",
1038 "amair1_ns",
1039 "amair1_s",
1040 "hmair0",
1041 "hmair1",
1042 "hamair0",
1043 "hamair1",
1044 "vbar",
1045 "vbar_ns",
1046 "vbar_s",
1047 "mvbar",
1048 "rmr",
1049 "isr",
1050 "hvbar",
1051 "fcseidr",
1052 "contextidr",
1053 "contextidr_ns",
1054 "contextidr_s",
1055 "tpidrurw",
1056 "tpidrurw_ns",
1057 "tpidrurw_s",
1058 "tpidruro",
1059 "tpidruro_ns",
1060 "tpidruro_s",
1061 "tpidrprw",
1062 "tpidrprw_ns",
1063 "tpidrprw_s",
1064 "htpidr",
1065 "cntfrq",
1066 "cntkctl",
1067 "cntp_tval",
1068 "cntp_tval_ns",
1069 "cntp_tval_s",
1070 "cntp_ctl",
1071 "cntp_ctl_ns",
1072 "cntp_ctl_s",
1073 "cntv_tval",
1074 "cntv_ctl",
1075 "cnthctl",
1076 "cnthp_tval",
1077 "cnthp_ctl",
1078 "il1data0",
1079 "il1data1",
1080 "il1data2",
1081 "il1data3",
1082 "dl1data0",
1083 "dl1data1",
1084 "dl1data2",
1085 "dl1data3",
1086 "dl1data4",
1087 "ramindex",
1088 "l2actlr",
1089 "cbar",
1090 "httbr",
1091 "vttbr",
1092 "cntpct",
1093 "cntvct",
1094 "cntp_cval",
1095 "cntp_cval_ns",
1096 "cntp_cval_s",
1097 "cntv_cval",
1098 "cntvoff",
1099 "cnthp_cval",
1100 "cpumerrsr",
1101 "l2merrsr",
1102
1103 // AArch64 registers (Op0=2)
1104 "mdccint_el1",
1105 "osdtrrx_el1",
1106 "mdscr_el1",
1107 "osdtrtx_el1",
1108 "oseccr_el1",
1109 "dbgbvr0_el1",
1110 "dbgbvr1_el1",
1111 "dbgbvr2_el1",
1112 "dbgbvr3_el1",
1113 "dbgbvr4_el1",
1114 "dbgbvr5_el1",
1115 "dbgbcr0_el1",
1116 "dbgbcr1_el1",
1117 "dbgbcr2_el1",
1118 "dbgbcr3_el1",
1119 "dbgbcr4_el1",
1120 "dbgbcr5_el1",
1121 "dbgwvr0_el1",
1122 "dbgwvr1_el1",
1123 "dbgwvr2_el1",
1124 "dbgwvr3_el1",
1125 "dbgwcr0_el1",
1126 "dbgwcr1_el1",
1127 "dbgwcr2_el1",
1128 "dbgwcr3_el1",
1129 "mdccsr_el0",
1130 "mddtr_el0",
1131 "mddtrtx_el0",
1132 "mddtrrx_el0",
1133 "dbgvcr32_el2",
1134 "mdrar_el1",
1135 "oslar_el1",
1136 "oslsr_el1",
1137 "osdlr_el1",
1138 "dbgprcr_el1",
1139 "dbgclaimset_el1",
1140 "dbgclaimclr_el1",
1141 "dbgauthstatus_el1",
1142 "teecr32_el1",
1143 "teehbr32_el1",
1144
1145 // AArch64 registers (Op0=1,3)
1146 "midr_el1",
1147 "mpidr_el1",
1148 "revidr_el1",
1149 "id_pfr0_el1",
1150 "id_pfr1_el1",
1151 "id_dfr0_el1",
1152 "id_afr0_el1",
1153 "id_mmfr0_el1",
1154 "id_mmfr1_el1",
1155 "id_mmfr2_el1",
1156 "id_mmfr3_el1",
1157 "id_isar0_el1",
1158 "id_isar1_el1",
1159 "id_isar2_el1",
1160 "id_isar3_el1",
1161 "id_isar4_el1",
1162 "id_isar5_el1",
1163 "mvfr0_el1",
1164 "mvfr1_el1",
1165 "mvfr2_el1",
1166 "id_aa64pfr0_el1",
1167 "id_aa64pfr1_el1",
1168 "id_aa64dfr0_el1",
1169 "id_aa64dfr1_el1",
1170 "id_aa64afr0_el1",
1171 "id_aa64afr1_el1",
1172 "id_aa64isar0_el1",
1173 "id_aa64isar1_el1",
1174 "id_aa64mmfr0_el1",
1175 "id_aa64mmfr1_el1",
1176 "ccsidr_el1",
1177 "clidr_el1",
1178 "aidr_el1",
1179 "csselr_el1",
1180 "ctr_el0",
1181 "dczid_el0",
1182 "vpidr_el2",
1183 "vmpidr_el2",
1184 "sctlr_el1",
1185 "actlr_el1",
1186 "cpacr_el1",
1187 "sctlr_el2",
1188 "actlr_el2",
1189 "hcr_el2",
1190 "mdcr_el2",
1191 "cptr_el2",
1192 "hstr_el2",
1193 "hacr_el2",
1194 "sctlr_el3",
1195 "actlr_el3",
1196 "scr_el3",
1197 "sder32_el3",
1198 "cptr_el3",
1199 "mdcr_el3",
1200 "ttbr0_el1",
1201 "ttbr1_el1",
1202 "tcr_el1",
1203 "ttbr0_el2",
1204 "tcr_el2",
1205 "vttbr_el2",
1206 "vtcr_el2",
1207 "ttbr0_el3",
1208 "tcr_el3",
1209 "dacr32_el2",
1210 "spsr_el1",
1211 "elr_el1",
1212 "sp_el0",
1213 "spsel",
1214 "currentel",
1215 "nzcv",
1216 "daif",
1217 "fpcr",
1218 "fpsr",
1219 "dspsr_el0",
1220 "dlr_el0",
1221 "spsr_el2",
1222 "elr_el2",
1223 "sp_el1",
1224 "spsr_irq_aa64",
1225 "spsr_abt_aa64",
1226 "spsr_und_aa64",
1227 "spsr_fiq_aa64",
1228 "spsr_el3",
1229 "elr_el3",
1230 "sp_el2",
1231 "afsr0_el1",
1232 "afsr1_el1",
1233 "esr_el1",
1234 "ifsr32_el2",
1235 "afsr0_el2",
1236 "afsr1_el2",
1237 "esr_el2",
1238 "fpexc32_el2",
1239 "afsr0_el3",
1240 "afsr1_el3",
1241 "esr_el3",
1242 "far_el1",
1243 "far_el2",
1244 "hpfar_el2",
1245 "far_el3",
1246 "ic_ialluis",
1247 "par_el1",
1248 "ic_iallu",
1249 "dc_ivac_xt",
1250 "dc_isw_xt",
1251 "at_s1e1r_xt",
1252 "at_s1e1w_xt",
1253 "at_s1e0r_xt",
1254 "at_s1e0w_xt",
1255 "dc_csw_xt",
1256 "dc_cisw_xt",
1257 "dc_zva_xt",
1258 "ic_ivau_xt",
1259 "dc_cvac_xt",
1260 "dc_cvau_xt",
1261 "dc_civac_xt",
1262 "at_s1e2r_xt",
1263 "at_s1e2w_xt",
1264 "at_s12e1r_xt",
1265 "at_s12e1w_xt",
1266 "at_s12e0r_xt",
1267 "at_s12e0w_xt",
1268 "at_s1e3r_xt",
1269 "at_s1e3w_xt",
1270 "tlbi_vmalle1is",
1271 "tlbi_vae1is_xt",
1272 "tlbi_aside1is_xt",
1273 "tlbi_vaae1is_xt",
1274 "tlbi_vale1is_xt",
1275 "tlbi_vaale1is_xt",
1276 "tlbi_vmalle1",
1277 "tlbi_vae1_xt",
1278 "tlbi_aside1_xt",
1279 "tlbi_vaae1_xt",
1280 "tlbi_vale1_xt",
1281 "tlbi_vaale1_xt",
1282 "tlbi_ipas2e1is_xt",
1283 "tlbi_ipas2le1is_xt",
1284 "tlbi_alle2is",
1285 "tlbi_vae2is_xt",
1286 "tlbi_alle1is",
1287 "tlbi_vale2is_xt",
1288 "tlbi_vmalls12e1is",
1289 "tlbi_ipas2e1_xt",
1290 "tlbi_ipas2le1_xt",
1291 "tlbi_alle2",
1292 "tlbi_vae2_xt",
1293 "tlbi_alle1",
1294 "tlbi_vale2_xt",
1295 "tlbi_vmalls12e1",
1296 "tlbi_alle3is",
1297 "tlbi_vae3is_xt",
1298 "tlbi_vale3is_xt",
1299 "tlbi_alle3",
1300 "tlbi_vae3_xt",
1301 "tlbi_vale3_xt",
1302 "pmintenset_el1",
1303 "pmintenclr_el1",
1304 "pmcr_el0",
1305 "pmcntenset_el0",
1306 "pmcntenclr_el0",
1307 "pmovsclr_el0",
1308 "pmswinc_el0",
1309 "pmselr_el0",
1310 "pmceid0_el0",
1311 "pmceid1_el0",
1312 "pmccntr_el0",
1313 "pmxevtyper_el0",
1314 "pmccfiltr_el0",
1315 "pmxevcntr_el0",
1316 "pmuserenr_el0",
1317 "pmovsset_el0",
1318 "mair_el1",
1319 "amair_el1",
1320 "mair_el2",
1321 "amair_el2",
1322 "mair_el3",
1323 "amair_el3",
1324 "l2ctlr_el1",
1325 "l2ectlr_el1",
1326 "vbar_el1",
1327 "rvbar_el1",
1328 "isr_el1",
1329 "vbar_el2",
1330 "rvbar_el2",
1331 "vbar_el3",
1332 "rvbar_el3",
1333 "rmr_el3",
1334 "contextidr_el1",
1335 "tpidr_el1",
1336 "tpidr_el0",
1337 "tpidrro_el0",
1338 "tpidr_el2",
1339 "tpidr_el3",
1340 "cntkctl_el1",
1341 "cntfrq_el0",
1342 "cntpct_el0",
1343 "cntvct_el0",
1344 "cntp_tval_el0",
1345 "cntp_ctl_el0",
1346 "cntp_cval_el0",
1347 "cntv_tval_el0",
1348 "cntv_ctl_el0",
1349 "cntv_cval_el0",
1350 "pmevcntr0_el0",
1351 "pmevcntr1_el0",
1352 "pmevcntr2_el0",
1353 "pmevcntr3_el0",
1354 "pmevcntr4_el0",
1355 "pmevcntr5_el0",
1356 "pmevtyper0_el0",
1357 "pmevtyper1_el0",
1358 "pmevtyper2_el0",
1359 "pmevtyper3_el0",
1360 "pmevtyper4_el0",
1361 "pmevtyper5_el0",
1362 "cntvoff_el2",
1363 "cnthctl_el2",
1364 "cnthp_tval_el2",
1365 "cnthp_ctl_el2",
1366 "cnthp_cval_el2",
1367 "cntps_tval_el1",
1368 "cntps_ctl_el1",
1369 "cntps_cval_el1",
1370 "il1data0_el1",
1371 "il1data1_el1",
1372 "il1data2_el1",
1373 "il1data3_el1",
1374 "dl1data0_el1",
1375 "dl1data1_el1",
1376 "dl1data2_el1",
1377 "dl1data3_el1",
1378 "dl1data4_el1",
1379 "l2actlr_el1",
1380 "cpuactlr_el1",
1381 "cpuectlr_el1",
1382 "cpumerrsr_el1",
1383 "l2merrsr_el1",
1384 "cbar_el1",
1385 "contextidr_el2",
1386
1387 "ttbr1_el2",
1388 "cnthv_ctl_el2",
1389 "cnthv_cval_el2",
1390 "cnthv_tval_el2",
1391 "id_aa64mmfr2_el1",
1392 "freeslot2",
1393
1394 "num_phys_regs",
1395
1396 // Dummy registers
1397 "nop",
1398 "raz",
1399 "cp14_unimpl",
1400 "cp15_unimpl",
1401 "unknown",
1402 "impl_defined",
1403 "erridr_el1",
1404 "errselr_el1",
1405 "erxfr_el1",
1406 "erxctlr_el1",
1407 "erxstatus_el1",
1408 "erxaddr_el1",
1409 "erxmisc0_el1",
1410 "erxmisc1_el1",
1411 "disr_el1",
1412 "vsesr_el2",
1413 "vdisr_el2",
1414 };
1415
1416 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1417 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1418
1419 // This mask selects bits of the CPSR that actually go in the CondCodes
1420 // integer register to allow renaming.
1421 static const uint32_t CondCodesMask = 0xF00F0000;
1422 static const uint32_t CpsrMaskQ = 0x08000000;
1423
1424 // APSR (Application Program Status Register Mask). It is the user level
1425 // alias for the CPSR. The APSR is a subset of the CPSR. Although
1426 // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1427 // APSR:
1428 // Bit[9] returns the value of CPSR.E.
1429 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1430 static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1431
1432 // CPSR (Current Program Status Register Mask).
1433 static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1434
1435 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1436 // integer register to allow renaming.
1437 static const uint32_t FpCondCodesMask = 0xF0000000;
1438 // This mask selects the cumulative FP exception flags of the FPSCR.
1439 static const uint32_t FpscrExcMask = 0x0000009F;
1440 // This mask selects the cumulative saturation flag of the FPSCR.
1441 static const uint32_t FpscrQcMask = 0x08000000;
1442
1443 /**
1444 * Check for permission to read coprocessor registers.
1445 *
1446 * Checks whether an instruction at the current program mode has
1447 * permissions to read the coprocessor registers. This function
1448 * returns whether the check is undefined and if not whether the
1449 * read access is permitted.
1450 *
1451 * @param the misc reg indicating the coprocessor
1452 * @param the SCR
1453 * @param the CPSR
1454 * @return a tuple of booleans: can_read, undefined
1455 */
1456 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1457 CPSR cpsr);
1458
1459 /**
1460 * Check for permission to write coprocessor registers.
1461 *
1462 * Checks whether an instruction at the current program mode has
1463 * permissions to write the coprocessor registers. This function
1464 * returns whether the check is undefined and if not whether the
1465 * write access is permitted.
1466 *
1467 * @param the misc reg indicating the coprocessor
1468 * @param the SCR
1469 * @param the CPSR
1470 * @return a tuple of booleans: can_write, undefined
1471 */
1472 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1473 CPSR cpsr);
1474
1475 // Checks read access permissions to AArch64 system registers
1476 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1477 ThreadContext *tc);
1478
1479 // Checks write access permissions to AArch64 system registers
1480 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1481 ThreadContext *tc);
1482
1483 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1484 // for MCR/MRC instructions
1485 int
1486 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
1487
1488 // Flattens a misc reg index using the specified security state. This is
1489 // used for opperations (eg address translations) where the security
1490 // state of the register access may differ from the current state of the
1491 // processor
1492 int
1493 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
1494
1495 // Takes a misc reg index and returns the root reg if its one of a set of
1496 // banked registers
1497 void
1498 preUnflattenMiscReg();
1499
1500 int
1501 unflattenMiscReg(int reg);
1502
1503 }
1504
1505 #endif // __ARCH_ARM_MISCREGS_HH__