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43 #ifndef __ARCH_ARM_MISCREGS_HH__
44 #define __ARCH_ARM_MISCREGS_HH__
49 #include "arch/arm/miscregs_types.hh"
50 #include "base/compiler.hh"
58 MISCREG_CPSR = 0, // 0
60 MISCREG_SPSR_FIQ, // 2
61 MISCREG_SPSR_IRQ, // 3
62 MISCREG_SPSR_SVC, // 4
63 MISCREG_SPSR_MON, // 5
64 MISCREG_SPSR_ABT, // 6
65 MISCREG_SPSR_HYP, // 7
66 MISCREG_SPSR_UND, // 8
75 MISCREG_CPSR_MODE, // 15
77 MISCREG_FPSCR_EXC, // 17
78 MISCREG_FPSCR_QC, // 18
79 MISCREG_LOCKADDR, // 19
80 MISCREG_LOCKFLAG, // 20
81 MISCREG_PRRR_MAIR0, // 21
82 MISCREG_PRRR_MAIR0_NS, // 22
83 MISCREG_PRRR_MAIR0_S, // 23
84 MISCREG_NMRR_MAIR1, // 24
85 MISCREG_NMRR_MAIR1_NS, // 25
86 MISCREG_NMRR_MAIR1_S, // 26
87 MISCREG_PMXEVTYPER_PMCCFILTR, // 27
88 MISCREG_SCTLR_RST, // 28
89 MISCREG_SEV_MAILBOX, // 29
91 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
92 MISCREG_DBGDIDR, // 30
93 MISCREG_DBGDSCRint, // 31
94 MISCREG_DBGDCCINT, // 32
95 MISCREG_DBGDTRTXint, // 33
96 MISCREG_DBGDTRRXint, // 34
97 MISCREG_DBGWFAR, // 35
99 MISCREG_DBGDTRRXext, // 37
100 MISCREG_DBGDSCRext, // 38
101 MISCREG_DBGDTRTXext, // 39
102 MISCREG_DBGOSECCR, // 40
103 MISCREG_DBGBVR0, // 41
104 MISCREG_DBGBVR1, // 42
105 MISCREG_DBGBVR2, // 43
106 MISCREG_DBGBVR3, // 44
107 MISCREG_DBGBVR4, // 45
108 MISCREG_DBGBVR5, // 46
109 MISCREG_DBGBCR0, // 47
110 MISCREG_DBGBCR1, // 48
111 MISCREG_DBGBCR2, // 49
112 MISCREG_DBGBCR3, // 50
113 MISCREG_DBGBCR4, // 51
114 MISCREG_DBGBCR5, // 52
115 MISCREG_DBGWVR0, // 53
116 MISCREG_DBGWVR1, // 54
117 MISCREG_DBGWVR2, // 55
118 MISCREG_DBGWVR3, // 56
119 MISCREG_DBGWCR0, // 57
120 MISCREG_DBGWCR1, // 58
121 MISCREG_DBGWCR2, // 59
122 MISCREG_DBGWCR3, // 60
123 MISCREG_DBGDRAR, // 61
124 MISCREG_DBGBXVR4, // 62
125 MISCREG_DBGBXVR5, // 63
126 MISCREG_DBGOSLAR, // 64
127 MISCREG_DBGOSLSR, // 65
128 MISCREG_DBGOSDLR, // 66
129 MISCREG_DBGPRCR, // 67
130 MISCREG_DBGDSAR, // 68
131 MISCREG_DBGCLAIMSET, // 69
132 MISCREG_DBGCLAIMCLR, // 70
133 MISCREG_DBGAUTHSTATUS, // 71
134 MISCREG_DBGDEVID2, // 72
135 MISCREG_DBGDEVID1, // 73
136 MISCREG_DBGDEVID0, // 74
137 MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+
139 MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+
143 // AArch32 CP15 registers (system control)
149 MISCREG_REVIDR, // 85
150 MISCREG_ID_PFR0, // 86
151 MISCREG_ID_PFR1, // 87
152 MISCREG_ID_DFR0, // 88
153 MISCREG_ID_AFR0, // 89
154 MISCREG_ID_MMFR0, // 90
155 MISCREG_ID_MMFR1, // 91
156 MISCREG_ID_MMFR2, // 92
157 MISCREG_ID_MMFR3, // 93
158 MISCREG_ID_ISAR0, // 94
159 MISCREG_ID_ISAR1, // 95
160 MISCREG_ID_ISAR2, // 96
161 MISCREG_ID_ISAR3, // 97
162 MISCREG_ID_ISAR4, // 98
163 MISCREG_ID_ISAR5, // 99
164 MISCREG_CCSIDR, // 100
165 MISCREG_CLIDR, // 101
167 MISCREG_CSSELR, // 103
168 MISCREG_CSSELR_NS, // 104
169 MISCREG_CSSELR_S, // 105
170 MISCREG_VPIDR, // 106
171 MISCREG_VMPIDR, // 107
172 MISCREG_SCTLR, // 108
173 MISCREG_SCTLR_NS, // 109
174 MISCREG_SCTLR_S, // 110
175 MISCREG_ACTLR, // 111
176 MISCREG_ACTLR_NS, // 112
177 MISCREG_ACTLR_S, // 113
178 MISCREG_CPACR, // 114
181 MISCREG_NSACR, // 117
182 MISCREG_HSCTLR, // 118
183 MISCREG_HACTLR, // 119
186 MISCREG_HCPTR, // 122
189 MISCREG_TTBR0, // 125
190 MISCREG_TTBR0_NS, // 126
191 MISCREG_TTBR0_S, // 127
192 MISCREG_TTBR1, // 128
193 MISCREG_TTBR1_NS, // 129
194 MISCREG_TTBR1_S, // 130
195 MISCREG_TTBCR, // 131
196 MISCREG_TTBCR_NS, // 132
197 MISCREG_TTBCR_S, // 133
201 MISCREG_DACR_NS, // 137
202 MISCREG_DACR_S, // 138
204 MISCREG_DFSR_NS, // 140
205 MISCREG_DFSR_S, // 141
207 MISCREG_IFSR_NS, // 143
208 MISCREG_IFSR_S, // 144
209 MISCREG_ADFSR, // 145
210 MISCREG_ADFSR_NS, // 146
211 MISCREG_ADFSR_S, // 147
212 MISCREG_AIFSR, // 148
213 MISCREG_AIFSR_NS, // 149
214 MISCREG_AIFSR_S, // 150
215 MISCREG_HADFSR, // 151
216 MISCREG_HAIFSR, // 152
219 MISCREG_DFAR_NS, // 155
220 MISCREG_DFAR_S, // 156
222 MISCREG_IFAR_NS, // 158
223 MISCREG_IFAR_S, // 159
224 MISCREG_HDFAR, // 160
225 MISCREG_HIFAR, // 161
226 MISCREG_HPFAR, // 162
227 MISCREG_ICIALLUIS, // 163
228 MISCREG_BPIALLIS, // 164
230 MISCREG_PAR_NS, // 166
231 MISCREG_PAR_S, // 167
232 MISCREG_ICIALLU, // 168
233 MISCREG_ICIMVAU, // 169
234 MISCREG_CP15ISB, // 170
235 MISCREG_BPIALL, // 171
236 MISCREG_BPIMVA, // 172
237 MISCREG_DCIMVAC, // 173
238 MISCREG_DCISW, // 174
239 MISCREG_ATS1CPR, // 175
240 MISCREG_ATS1CPW, // 176
241 MISCREG_ATS1CUR, // 177
242 MISCREG_ATS1CUW, // 178
243 MISCREG_ATS12NSOPR, // 179
244 MISCREG_ATS12NSOPW, // 180
245 MISCREG_ATS12NSOUR, // 181
246 MISCREG_ATS12NSOUW, // 182
247 MISCREG_DCCMVAC, // 183
248 MISCREG_DCCSW, // 184
249 MISCREG_CP15DSB, // 185
250 MISCREG_CP15DMB, // 186
251 MISCREG_DCCMVAU, // 187
252 MISCREG_DCCIMVAC, // 188
253 MISCREG_DCCISW, // 189
254 MISCREG_ATS1HR, // 190
255 MISCREG_ATS1HW, // 191
256 MISCREG_TLBIALLIS, // 192
257 MISCREG_TLBIMVAIS, // 193
258 MISCREG_TLBIASIDIS, // 194
259 MISCREG_TLBIMVAAIS, // 195
260 MISCREG_TLBIMVALIS, // 196
261 MISCREG_TLBIMVAALIS, // 197
262 MISCREG_ITLBIALL, // 198
263 MISCREG_ITLBIMVA, // 199
264 MISCREG_ITLBIASID, // 200
265 MISCREG_DTLBIALL, // 201
266 MISCREG_DTLBIMVA, // 202
267 MISCREG_DTLBIASID, // 203
268 MISCREG_TLBIALL, // 204
269 MISCREG_TLBIMVA, // 205
270 MISCREG_TLBIASID, // 206
271 MISCREG_TLBIMVAA, // 207
272 MISCREG_TLBIMVAL, // 208
273 MISCREG_TLBIMVAAL, // 209
274 MISCREG_TLBIIPAS2IS, // 210
275 MISCREG_TLBIIPAS2LIS, // 211
276 MISCREG_TLBIALLHIS, // 212
277 MISCREG_TLBIMVAHIS, // 213
278 MISCREG_TLBIALLNSNHIS, // 214
279 MISCREG_TLBIMVALHIS, // 215
280 MISCREG_TLBIIPAS2, // 216
281 MISCREG_TLBIIPAS2L, // 217
282 MISCREG_TLBIALLH, // 218
283 MISCREG_TLBIMVAH, // 219
284 MISCREG_TLBIALLNSNH, // 220
285 MISCREG_TLBIMVALH, // 221
287 MISCREG_PMCNTENSET, // 223
288 MISCREG_PMCNTENCLR, // 224
289 MISCREG_PMOVSR, // 225
290 MISCREG_PMSWINC, // 226
291 MISCREG_PMSELR, // 227
292 MISCREG_PMCEID0, // 228
293 MISCREG_PMCEID1, // 229
294 MISCREG_PMCCNTR, // 230
295 MISCREG_PMXEVTYPER, // 231
296 MISCREG_PMCCFILTR, // 232
297 MISCREG_PMXEVCNTR, // 233
298 MISCREG_PMUSERENR, // 234
299 MISCREG_PMINTENSET, // 235
300 MISCREG_PMINTENCLR, // 236
301 MISCREG_PMOVSSET, // 237
302 MISCREG_L2CTLR, // 238
303 MISCREG_L2ECTLR, // 239
305 MISCREG_PRRR_NS, // 241
306 MISCREG_PRRR_S, // 242
307 MISCREG_MAIR0, // 243
308 MISCREG_MAIR0_NS, // 244
309 MISCREG_MAIR0_S, // 245
311 MISCREG_NMRR_NS, // 247
312 MISCREG_NMRR_S, // 248
313 MISCREG_MAIR1, // 249
314 MISCREG_MAIR1_NS, // 250
315 MISCREG_MAIR1_S, // 251
316 MISCREG_AMAIR0, // 252
317 MISCREG_AMAIR0_NS, // 253
318 MISCREG_AMAIR0_S, // 254
319 MISCREG_AMAIR1, // 255
320 MISCREG_AMAIR1_NS, // 256
321 MISCREG_AMAIR1_S, // 257
322 MISCREG_HMAIR0, // 258
323 MISCREG_HMAIR1, // 259
324 MISCREG_HAMAIR0, // 260
325 MISCREG_HAMAIR1, // 261
327 MISCREG_VBAR_NS, // 263
328 MISCREG_VBAR_S, // 264
329 MISCREG_MVBAR, // 265
332 MISCREG_HVBAR, // 268
333 MISCREG_FCSEIDR, // 269
334 MISCREG_CONTEXTIDR, // 270
335 MISCREG_CONTEXTIDR_NS, // 271
336 MISCREG_CONTEXTIDR_S, // 272
337 MISCREG_TPIDRURW, // 273
338 MISCREG_TPIDRURW_NS, // 274
339 MISCREG_TPIDRURW_S, // 275
340 MISCREG_TPIDRURO, // 276
341 MISCREG_TPIDRURO_NS, // 277
342 MISCREG_TPIDRURO_S, // 278
343 MISCREG_TPIDRPRW, // 279
344 MISCREG_TPIDRPRW_NS, // 280
345 MISCREG_TPIDRPRW_S, // 281
346 MISCREG_HTPIDR, // 282
347 MISCREG_CNTFRQ, // 283
348 MISCREG_CNTKCTL, // 284
349 MISCREG_CNTP_TVAL, // 285
350 MISCREG_CNTP_TVAL_NS, // 286
351 MISCREG_CNTP_TVAL_S, // 287
352 MISCREG_CNTP_CTL, // 288
353 MISCREG_CNTP_CTL_NS, // 289
354 MISCREG_CNTP_CTL_S, // 290
355 MISCREG_CNTV_TVAL, // 291
356 MISCREG_CNTV_CTL, // 292
357 MISCREG_CNTHCTL, // 293
358 MISCREG_CNTHP_TVAL, // 294
359 MISCREG_CNTHP_CTL, // 295
360 MISCREG_IL1DATA0, // 296
361 MISCREG_IL1DATA1, // 297
362 MISCREG_IL1DATA2, // 298
363 MISCREG_IL1DATA3, // 299
364 MISCREG_DL1DATA0, // 300
365 MISCREG_DL1DATA1, // 301
366 MISCREG_DL1DATA2, // 302
367 MISCREG_DL1DATA3, // 303
368 MISCREG_DL1DATA4, // 304
369 MISCREG_RAMINDEX, // 305
370 MISCREG_L2ACTLR, // 306
372 MISCREG_HTTBR, // 308
373 MISCREG_VTTBR, // 309
374 MISCREG_CNTPCT, // 310
375 MISCREG_CNTVCT, // 311
376 MISCREG_CNTP_CVAL, // 312
377 MISCREG_CNTP_CVAL_NS, // 313
378 MISCREG_CNTP_CVAL_S, // 314
379 MISCREG_CNTV_CVAL, // 315
380 MISCREG_CNTVOFF, // 316
381 MISCREG_CNTHP_CVAL, // 317
382 MISCREG_CPUMERRSR, // 318
383 MISCREG_L2MERRSR, // 319
385 // AArch64 registers (Op0=2)
386 MISCREG_MDCCINT_EL1, // 320
387 MISCREG_OSDTRRX_EL1, // 321
388 MISCREG_MDSCR_EL1, // 322
389 MISCREG_OSDTRTX_EL1, // 323
390 MISCREG_OSECCR_EL1, // 324
391 MISCREG_DBGBVR0_EL1, // 325
392 MISCREG_DBGBVR1_EL1, // 326
393 MISCREG_DBGBVR2_EL1, // 327
394 MISCREG_DBGBVR3_EL1, // 328
395 MISCREG_DBGBVR4_EL1, // 329
396 MISCREG_DBGBVR5_EL1, // 330
397 MISCREG_DBGBCR0_EL1, // 331
398 MISCREG_DBGBCR1_EL1, // 332
399 MISCREG_DBGBCR2_EL1, // 333
400 MISCREG_DBGBCR3_EL1, // 334
401 MISCREG_DBGBCR4_EL1, // 335
402 MISCREG_DBGBCR5_EL1, // 336
403 MISCREG_DBGWVR0_EL1, // 337
404 MISCREG_DBGWVR1_EL1, // 338
405 MISCREG_DBGWVR2_EL1, // 339
406 MISCREG_DBGWVR3_EL1, // 340
407 MISCREG_DBGWCR0_EL1, // 341
408 MISCREG_DBGWCR1_EL1, // 342
409 MISCREG_DBGWCR2_EL1, // 343
410 MISCREG_DBGWCR3_EL1, // 344
411 MISCREG_MDCCSR_EL0, // 345
412 MISCREG_MDDTR_EL0, // 346
413 MISCREG_MDDTRTX_EL0, // 347
414 MISCREG_MDDTRRX_EL0, // 348
415 MISCREG_DBGVCR32_EL2, // 349
416 MISCREG_MDRAR_EL1, // 350
417 MISCREG_OSLAR_EL1, // 351
418 MISCREG_OSLSR_EL1, // 352
419 MISCREG_OSDLR_EL1, // 353
420 MISCREG_DBGPRCR_EL1, // 354
421 MISCREG_DBGCLAIMSET_EL1, // 355
422 MISCREG_DBGCLAIMCLR_EL1, // 356
423 MISCREG_DBGAUTHSTATUS_EL1, // 357
424 MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+
425 MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+
427 // AArch64 registers (Op0=1,3)
428 MISCREG_MIDR_EL1, // 360
429 MISCREG_MPIDR_EL1, // 361
430 MISCREG_REVIDR_EL1, // 362
431 MISCREG_ID_PFR0_EL1, // 363
432 MISCREG_ID_PFR1_EL1, // 364
433 MISCREG_ID_DFR0_EL1, // 365
434 MISCREG_ID_AFR0_EL1, // 366
435 MISCREG_ID_MMFR0_EL1, // 367
436 MISCREG_ID_MMFR1_EL1, // 368
437 MISCREG_ID_MMFR2_EL1, // 369
438 MISCREG_ID_MMFR3_EL1, // 370
439 MISCREG_ID_ISAR0_EL1, // 371
440 MISCREG_ID_ISAR1_EL1, // 372
441 MISCREG_ID_ISAR2_EL1, // 373
442 MISCREG_ID_ISAR3_EL1, // 374
443 MISCREG_ID_ISAR4_EL1, // 375
444 MISCREG_ID_ISAR5_EL1, // 376
445 MISCREG_MVFR0_EL1, // 377
446 MISCREG_MVFR1_EL1, // 378
447 MISCREG_MVFR2_EL1, // 379
448 MISCREG_ID_AA64PFR0_EL1, // 380
449 MISCREG_ID_AA64PFR1_EL1, // 381
450 MISCREG_ID_AA64DFR0_EL1, // 382
451 MISCREG_ID_AA64DFR1_EL1, // 383
452 MISCREG_ID_AA64AFR0_EL1, // 384
453 MISCREG_ID_AA64AFR1_EL1, // 385
454 MISCREG_ID_AA64ISAR0_EL1, // 386
455 MISCREG_ID_AA64ISAR1_EL1, // 387
456 MISCREG_ID_AA64MMFR0_EL1, // 388
457 MISCREG_ID_AA64MMFR1_EL1, // 389
458 MISCREG_CCSIDR_EL1, // 390
459 MISCREG_CLIDR_EL1, // 391
460 MISCREG_AIDR_EL1, // 392
461 MISCREG_CSSELR_EL1, // 393
462 MISCREG_CTR_EL0, // 394
463 MISCREG_DCZID_EL0, // 395
464 MISCREG_VPIDR_EL2, // 396
465 MISCREG_VMPIDR_EL2, // 397
466 MISCREG_SCTLR_EL1, // 398
467 MISCREG_ACTLR_EL1, // 399
468 MISCREG_CPACR_EL1, // 400
469 MISCREG_SCTLR_EL2, // 401
470 MISCREG_ACTLR_EL2, // 402
471 MISCREG_HCR_EL2, // 403
472 MISCREG_MDCR_EL2, // 404
473 MISCREG_CPTR_EL2, // 405
474 MISCREG_HSTR_EL2, // 406
475 MISCREG_HACR_EL2, // 407
476 MISCREG_SCTLR_EL3, // 408
477 MISCREG_ACTLR_EL3, // 409
478 MISCREG_SCR_EL3, // 410
479 MISCREG_SDER32_EL3, // 411
480 MISCREG_CPTR_EL3, // 412
481 MISCREG_MDCR_EL3, // 413
482 MISCREG_TTBR0_EL1, // 414
483 MISCREG_TTBR1_EL1, // 415
484 MISCREG_TCR_EL1, // 416
485 MISCREG_TTBR0_EL2, // 417
486 MISCREG_TCR_EL2, // 418
487 MISCREG_VTTBR_EL2, // 419
488 MISCREG_VTCR_EL2, // 420
489 MISCREG_TTBR0_EL3, // 421
490 MISCREG_TCR_EL3, // 422
491 MISCREG_DACR32_EL2, // 423
492 MISCREG_SPSR_EL1, // 424
493 MISCREG_ELR_EL1, // 425
494 MISCREG_SP_EL0, // 426
495 MISCREG_SPSEL, // 427
496 MISCREG_CURRENTEL, // 428
501 MISCREG_DSPSR_EL0, // 433
502 MISCREG_DLR_EL0, // 434
503 MISCREG_SPSR_EL2, // 435
504 MISCREG_ELR_EL2, // 436
505 MISCREG_SP_EL1, // 437
506 MISCREG_SPSR_IRQ_AA64, // 438
507 MISCREG_SPSR_ABT_AA64, // 439
508 MISCREG_SPSR_UND_AA64, // 440
509 MISCREG_SPSR_FIQ_AA64, // 441
510 MISCREG_SPSR_EL3, // 442
511 MISCREG_ELR_EL3, // 443
512 MISCREG_SP_EL2, // 444
513 MISCREG_AFSR0_EL1, // 445
514 MISCREG_AFSR1_EL1, // 446
515 MISCREG_ESR_EL1, // 447
516 MISCREG_IFSR32_EL2, // 448
517 MISCREG_AFSR0_EL2, // 449
518 MISCREG_AFSR1_EL2, // 450
519 MISCREG_ESR_EL2, // 451
520 MISCREG_FPEXC32_EL2, // 452
521 MISCREG_AFSR0_EL3, // 453
522 MISCREG_AFSR1_EL3, // 454
523 MISCREG_ESR_EL3, // 455
524 MISCREG_FAR_EL1, // 456
525 MISCREG_FAR_EL2, // 457
526 MISCREG_HPFAR_EL2, // 458
527 MISCREG_FAR_EL3, // 459
528 MISCREG_IC_IALLUIS, // 460
529 MISCREG_PAR_EL1, // 461
530 MISCREG_IC_IALLU, // 462
531 MISCREG_DC_IVAC_Xt, // 463
532 MISCREG_DC_ISW_Xt, // 464
533 MISCREG_AT_S1E1R_Xt, // 465
534 MISCREG_AT_S1E1W_Xt, // 466
535 MISCREG_AT_S1E0R_Xt, // 467
536 MISCREG_AT_S1E0W_Xt, // 468
537 MISCREG_DC_CSW_Xt, // 469
538 MISCREG_DC_CISW_Xt, // 470
539 MISCREG_DC_ZVA_Xt, // 471
540 MISCREG_IC_IVAU_Xt, // 472
541 MISCREG_DC_CVAC_Xt, // 473
542 MISCREG_DC_CVAU_Xt, // 474
543 MISCREG_DC_CIVAC_Xt, // 475
544 MISCREG_AT_S1E2R_Xt, // 476
545 MISCREG_AT_S1E2W_Xt, // 477
546 MISCREG_AT_S12E1R_Xt, // 478
547 MISCREG_AT_S12E1W_Xt, // 479
548 MISCREG_AT_S12E0R_Xt, // 480
549 MISCREG_AT_S12E0W_Xt, // 481
550 MISCREG_AT_S1E3R_Xt, // 482
551 MISCREG_AT_S1E3W_Xt, // 483
552 MISCREG_TLBI_VMALLE1IS, // 484
553 MISCREG_TLBI_VAE1IS_Xt, // 485
554 MISCREG_TLBI_ASIDE1IS_Xt, // 486
555 MISCREG_TLBI_VAAE1IS_Xt, // 487
556 MISCREG_TLBI_VALE1IS_Xt, // 488
557 MISCREG_TLBI_VAALE1IS_Xt, // 489
558 MISCREG_TLBI_VMALLE1, // 490
559 MISCREG_TLBI_VAE1_Xt, // 491
560 MISCREG_TLBI_ASIDE1_Xt, // 492
561 MISCREG_TLBI_VAAE1_Xt, // 493
562 MISCREG_TLBI_VALE1_Xt, // 494
563 MISCREG_TLBI_VAALE1_Xt, // 495
564 MISCREG_TLBI_IPAS2E1IS_Xt, // 496
565 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497
566 MISCREG_TLBI_ALLE2IS, // 498
567 MISCREG_TLBI_VAE2IS_Xt, // 499
568 MISCREG_TLBI_ALLE1IS, // 500
569 MISCREG_TLBI_VALE2IS_Xt, // 501
570 MISCREG_TLBI_VMALLS12E1IS, // 502
571 MISCREG_TLBI_IPAS2E1_Xt, // 503
572 MISCREG_TLBI_IPAS2LE1_Xt, // 504
573 MISCREG_TLBI_ALLE2, // 505
574 MISCREG_TLBI_VAE2_Xt, // 506
575 MISCREG_TLBI_ALLE1, // 507
576 MISCREG_TLBI_VALE2_Xt, // 508
577 MISCREG_TLBI_VMALLS12E1, // 509
578 MISCREG_TLBI_ALLE3IS, // 510
579 MISCREG_TLBI_VAE3IS_Xt, // 511
580 MISCREG_TLBI_VALE3IS_Xt, // 512
581 MISCREG_TLBI_ALLE3, // 513
582 MISCREG_TLBI_VAE3_Xt, // 514
583 MISCREG_TLBI_VALE3_Xt, // 515
584 MISCREG_PMINTENSET_EL1, // 516
585 MISCREG_PMINTENCLR_EL1, // 517
586 MISCREG_PMCR_EL0, // 518
587 MISCREG_PMCNTENSET_EL0, // 519
588 MISCREG_PMCNTENCLR_EL0, // 520
589 MISCREG_PMOVSCLR_EL0, // 521
590 MISCREG_PMSWINC_EL0, // 522
591 MISCREG_PMSELR_EL0, // 523
592 MISCREG_PMCEID0_EL0, // 524
593 MISCREG_PMCEID1_EL0, // 525
594 MISCREG_PMCCNTR_EL0, // 526
595 MISCREG_PMXEVTYPER_EL0, // 527
596 MISCREG_PMCCFILTR_EL0, // 528
597 MISCREG_PMXEVCNTR_EL0, // 529
598 MISCREG_PMUSERENR_EL0, // 530
599 MISCREG_PMOVSSET_EL0, // 531
600 MISCREG_MAIR_EL1, // 532
601 MISCREG_AMAIR_EL1, // 533
602 MISCREG_MAIR_EL2, // 534
603 MISCREG_AMAIR_EL2, // 535
604 MISCREG_MAIR_EL3, // 536
605 MISCREG_AMAIR_EL3, // 537
606 MISCREG_L2CTLR_EL1, // 538
607 MISCREG_L2ECTLR_EL1, // 539
608 MISCREG_VBAR_EL1, // 540
609 MISCREG_RVBAR_EL1, // 541
610 MISCREG_ISR_EL1, // 542
611 MISCREG_VBAR_EL2, // 543
612 MISCREG_RVBAR_EL2, // 544
613 MISCREG_VBAR_EL3, // 545
614 MISCREG_RVBAR_EL3, // 546
615 MISCREG_RMR_EL3, // 547
616 MISCREG_CONTEXTIDR_EL1, // 548
617 MISCREG_TPIDR_EL1, // 549
618 MISCREG_TPIDR_EL0, // 550
619 MISCREG_TPIDRRO_EL0, // 551
620 MISCREG_TPIDR_EL2, // 552
621 MISCREG_TPIDR_EL3, // 553
622 MISCREG_CNTKCTL_EL1, // 554
623 MISCREG_CNTFRQ_EL0, // 555
624 MISCREG_CNTPCT_EL0, // 556
625 MISCREG_CNTVCT_EL0, // 557
626 MISCREG_CNTP_TVAL_EL0, // 558
627 MISCREG_CNTP_CTL_EL0, // 559
628 MISCREG_CNTP_CVAL_EL0, // 560
629 MISCREG_CNTV_TVAL_EL0, // 561
630 MISCREG_CNTV_CTL_EL0, // 562
631 MISCREG_CNTV_CVAL_EL0, // 563
632 MISCREG_PMEVCNTR0_EL0, // 564
633 MISCREG_PMEVCNTR1_EL0, // 565
634 MISCREG_PMEVCNTR2_EL0, // 566
635 MISCREG_PMEVCNTR3_EL0, // 567
636 MISCREG_PMEVCNTR4_EL0, // 568
637 MISCREG_PMEVCNTR5_EL0, // 569
638 MISCREG_PMEVTYPER0_EL0, // 570
639 MISCREG_PMEVTYPER1_EL0, // 571
640 MISCREG_PMEVTYPER2_EL0, // 572
641 MISCREG_PMEVTYPER3_EL0, // 573
642 MISCREG_PMEVTYPER4_EL0, // 574
643 MISCREG_PMEVTYPER5_EL0, // 575
644 MISCREG_CNTVOFF_EL2, // 576
645 MISCREG_CNTHCTL_EL2, // 577
646 MISCREG_CNTHP_TVAL_EL2, // 578
647 MISCREG_CNTHP_CTL_EL2, // 579
648 MISCREG_CNTHP_CVAL_EL2, // 580
649 MISCREG_CNTPS_TVAL_EL1, // 581
650 MISCREG_CNTPS_CTL_EL1, // 582
651 MISCREG_CNTPS_CVAL_EL1, // 583
652 MISCREG_IL1DATA0_EL1, // 584
653 MISCREG_IL1DATA1_EL1, // 585
654 MISCREG_IL1DATA2_EL1, // 586
655 MISCREG_IL1DATA3_EL1, // 587
656 MISCREG_DL1DATA0_EL1, // 588
657 MISCREG_DL1DATA1_EL1, // 589
658 MISCREG_DL1DATA2_EL1, // 590
659 MISCREG_DL1DATA3_EL1, // 591
660 MISCREG_DL1DATA4_EL1, // 592
661 MISCREG_L2ACTLR_EL1, // 593
662 MISCREG_CPUACTLR_EL1, // 594
663 MISCREG_CPUECTLR_EL1, // 595
664 MISCREG_CPUMERRSR_EL1, // 596
665 MISCREG_L2MERRSR_EL1, // 597
666 MISCREG_CBAR_EL1, // 598
667 MISCREG_CONTEXTIDR_EL2, // 599
669 // Introduced in ARMv8.1
670 MISCREG_TTBR1_EL2, // 600
671 MISCREG_CNTHV_CTL_EL2, // 601
672 MISCREG_CNTHV_CVAL_EL2, // 602
673 MISCREG_CNTHV_TVAL_EL2, // 603
675 // These MISCREG_FREESLOT are available Misc Register
676 // slots for future registers to be implemented.
677 MISCREG_FREESLOT_1, // 604
678 MISCREG_FREESLOT_2, // 605
680 // NUM_PHYS_MISCREGS specifies the number of actual physical
681 // registers, not considering the following pseudo-registers
682 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
683 // Checkpointing should use this physical index when
684 // saving/restoring register values.
685 NUM_PHYS_MISCREGS = 606, // 606
694 // Implementation defined register: this represent
695 // a pool of unimplemented registers whose access can throw
696 // either UNDEFINED or hypervisor trap exception.
697 MISCREG_IMPDEF_UNIMPL,
699 // RAS extension (unimplemented)
704 MISCREG_ERXSTATUS_EL1,
706 MISCREG_ERXMISC0_EL1,
707 MISCREG_ERXMISC1_EL1,
712 // Total number of Misc Registers: Physical + Dummy
718 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
719 // arch generic counter)
720 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
721 // tells whether the instruction should raise a
723 MISCREG_MUTEX, // True if the register corresponds to a pair of
724 // mutually exclusive registers
725 MISCREG_BANKED, // True if the register is banked between the two
726 // security states, and this is the parent node of the
727 // two banked registers
728 MISCREG_BANKED_CHILD, // The entry is one of the child registers that
729 // forms a banked set of regs (along with the
732 // Access permissions
738 // Privileged modes other than hypervisor or monitor
746 // Monitor mode, SCR.NS == 0
749 // Monitor mode, SCR.NS == 1
756 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
758 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
759 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
760 unsigned crm, unsigned opc2);
761 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
762 unsigned crn, unsigned crm,
764 // Whether a particular AArch64 system register is -always- read only.
765 bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
767 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
768 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
769 unsigned crm, unsigned opc2);
771 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
772 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
775 const char * const miscRegName[] = {
805 "pmxevtyper_pmccfiltr",
809 // AArch32 CP14 registers
861 // AArch32 CP15 registers
1103 // AArch64 registers (Op0=2)
1141 "dbgauthstatus_el1",
1145 // AArch64 registers (Op0=1,3)
1282 "tlbi_ipas2e1is_xt",
1283 "tlbi_ipas2le1is_xt",
1288 "tlbi_vmalls12e1is",
1416 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1417 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1419 // This mask selects bits of the CPSR that actually go in the CondCodes
1420 // integer register to allow renaming.
1421 static const uint32_t CondCodesMask = 0xF00F0000;
1422 static const uint32_t CpsrMaskQ = 0x08000000;
1424 // APSR (Application Program Status Register Mask). It is the user level
1425 // alias for the CPSR. The APSR is a subset of the CPSR. Although
1426 // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1428 // Bit[9] returns the value of CPSR.E.
1429 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1430 static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1432 // CPSR (Current Program Status Register Mask).
1433 static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1435 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1436 // integer register to allow renaming.
1437 static const uint32_t FpCondCodesMask = 0xF0000000;
1438 // This mask selects the cumulative FP exception flags of the FPSCR.
1439 static const uint32_t FpscrExcMask = 0x0000009F;
1440 // This mask selects the cumulative saturation flag of the FPSCR.
1441 static const uint32_t FpscrQcMask = 0x08000000;
1444 * Check for permission to read coprocessor registers.
1446 * Checks whether an instruction at the current program mode has
1447 * permissions to read the coprocessor registers. This function
1448 * returns whether the check is undefined and if not whether the
1449 * read access is permitted.
1451 * @param the misc reg indicating the coprocessor
1454 * @return a tuple of booleans: can_read, undefined
1456 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1460 * Check for permission to write coprocessor registers.
1462 * Checks whether an instruction at the current program mode has
1463 * permissions to write the coprocessor registers. This function
1464 * returns whether the check is undefined and if not whether the
1465 * write access is permitted.
1467 * @param the misc reg indicating the coprocessor
1470 * @return a tuple of booleans: can_write, undefined
1472 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1475 // Checks read access permissions to AArch64 system registers
1476 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1479 // Checks write access permissions to AArch64 system registers
1480 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1483 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1484 // for MCR/MRC instructions
1486 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
1488 // Flattens a misc reg index using the specified security state. This is
1489 // used for opperations (eg address translations) where the security
1490 // state of the register access may differ from the current state of the
1493 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
1495 // Takes a misc reg index and returns the root reg if its one of a set of
1498 preUnflattenMiscReg();
1501 unflattenMiscReg(int reg);
1505 #endif // __ARCH_ARM_MISCREGS_HH__