src/arch/arm/miscregs.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42 #ifndef __ARCH_ARM_MISCREGS_HH__
  43 #define __ARCH_ARM_MISCREGS_HH__
  44
  45 #include "base/bitunion.hh"
  46
  47 namespace ArmISA
  48 {
  49     enum ConditionCode {
  50         COND_EQ  =   0,
  51         COND_NE, //  1
  52         COND_CS, //  2
  53         COND_CC, //  3
  54         COND_MI, //  4
  55         COND_PL, //  5
  56         COND_VS, //  6
  57         COND_VC, //  7
  58         COND_HI, //  8
  59         COND_LS, //  9
  60         COND_GE, // 10
  61         COND_LT, // 11
  62         COND_GT, // 12
  63         COND_LE, // 13
  64         COND_AL, // 14
  65         COND_UC  // 15
  66     };
  67
  68     enum MiscRegIndex {
  69         MISCREG_CPSR = 0,
  70         MISCREG_SPSR,
  71         MISCREG_SPSR_FIQ,
  72         MISCREG_SPSR_IRQ,
  73         MISCREG_SPSR_SVC,
  74         MISCREG_SPSR_MON,
  75         MISCREG_SPSR_UND,
  76         MISCREG_SPSR_ABT,
  77         MISCREG_FPSR,
  78         MISCREG_FPSID,
  79         MISCREG_FPSCR,
  80         MISCREG_FPEXC,
  81
  82         // CP15 registers
  83         MISCREG_CP15_START,
  84         MISCREG_SCTLR = MISCREG_CP15_START,
  85         MISCREG_CP15_UNIMP_START,
  86         MISCREG_CTR = MISCREG_CP15_UNIMP_START,
  87         MISCREG_TCMTR,
  88         MISCREG_MPUIR,
  89         MISCREG_MPIDR,
  90         MISCREG_MIDR,
  91         MISCREG_ID_PFR0,
  92         MISCREG_ID_PFR1,
  93         MISCREG_ID_DFR0,
  94         MISCREG_ID_AFR0,
  95         MISCREG_ID_MMFR0,
  96         MISCREG_ID_MMFR1,
  97         MISCREG_ID_MMFR2,
  98         MISCREG_ID_MMFR3,
  99         MISCREG_ID_ISAR0,
 100         MISCREG_ID_ISAR1,
 101         MISCREG_ID_ISAR2,
 102         MISCREG_ID_ISAR3,
 103         MISCREG_ID_ISAR4,
 104         MISCREG_ID_ISAR5,
 105         MISCREG_CCSIDR,
 106         MISCREG_CLIDR,
 107         MISCREG_AIDR,
 108         MISCREG_CSSELR,
 109         MISCREG_ACTLR,
 110         MISCREG_CPACR,
 111         MISCREG_DFSR,
 112         MISCREG_IFSR,
 113         MISCREG_ADFSR,
 114         MISCREG_AIFSR,
 115         MISCREG_DFAR,
 116         MISCREG_IFAR,
 117         MISCREG_DRBAR,
 118         MISCREG_IRBAR,
 119         MISCREG_DRSR,
 120         MISCREG_IRSR,
 121         MISCREG_DRACR,
 122         MISCREG_IRACR,
 123         MISCREG_RGNR,
 124         MISCREG_ICIALLUIS,
 125         MISCREG_BPIALLIS,
 126         MISCREG_ICIALLU,
 127         MISCREG_ICIMVAU,
 128         MISCREG_CP15ISB,
 129         MISCREG_BPIALL,
 130         MISCREG_BPIMVA,
 131         MISCREG_DCIMVAC,
 132         MISCREG_DCISW,
 133         MISCREG_DCCMVAC,
 134         MISCREG_MCCSW,
 135         MISCREG_CP15DSB,
 136         MISCREG_CP15DMB,
 137         MISCREG_DCCMVAU,
 138         MISCREG_DCCIMVAC,
 139         MISCREG_DCCISW,
 140         MISCREG_CONTEXTIDR,
 141         MISCREG_TPIDRURW,
 142         MISCREG_TPIDRURO,
 143         MISCREG_TPIDRPRW,
 144
 145         MISCREG_CP15_END,
 146
 147         // Dummy indices
 148         MISCREG_NOP = MISCREG_CP15_END,
 149         MISCREG_RAZ,
 150
 151         NUM_MISCREGS
 152     };
 153
 154     MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
 155                                unsigned crm, unsigned opc2);
 156
 157     const char * const miscRegName[NUM_MISCREGS] = {
 158         "cpsr", "spsr", "spsr_fiq", "spsr_irq", "spsr_svc",
 159         "spsr_mon", "spsr_und", "spsr_abt",
 160         "fpsr", "fpsid", "fpscr", "fpexc",
 161         "sctlr", "ctr", "tcmtr", "mpuir", "mpidr", "midr",
 162         "id_pfr0", "id_pfr1", "id_dfr0", "id_afr0",
 163         "id_mmfr0", "id_mmfr1", "id_mmfr2", "id_mmfr3",
 164         "id_isar0", "id_isar1", "id_isar2", "id_isar3", "id_isar4", "id_isar5",
 165         "ccsidr", "clidr", "aidr", "csselr", "actlr", "cpacr",
 166         "dfsr", "ifsr", "adfsr", "aifsr", "dfar", "ifar",
 167         "drbar", "irbar", "drsr", "irsr", "dracr", "iracr",
 168         "rgnr", "icialluis", "bpiallis", "iciallu", "icimvau",
 169         "cp15isb", "bpiall", "bpimva", "dcimvac", "dcisw", "dccmvac", "mccsw",
 170         "cp15dsb", "cp15dmb", "dccmvau", "dccimvac", "dccisw",
 171         "contextidr", "tpidrurw", "tpidruro", "tpidrprw",
 172         "nop", "raz"
 173     };
 174
 175     BitUnion32(CPSR)
 176         Bitfield<31> n;
 177         Bitfield<30> z;
 178         Bitfield<29> c;
 179         Bitfield<28> v;
 180         Bitfield<27> q;
 181         Bitfield<26,25> it1;
 182         Bitfield<24> j;
 183         Bitfield<19, 16> ge;
 184         Bitfield<15,10> it2;
 185         Bitfield<9> e;
 186         Bitfield<8> a;
 187         Bitfield<7> i;
 188         Bitfield<6> f;
 189         Bitfield<5> t;
 190         Bitfield<4, 0> mode;
 191     EndBitUnion(CPSR)
 192
 193     // This mask selects bits of the CPSR that actually go in the CondCodes
 194     // integer register to allow renaming.
 195     static const uint32_t CondCodesMask = 0xF80F0000;
 196
 197     // These otherwise unused bits of the PC are used to select a mode
 198     // like the J and T bits of the CPSR.
 199     static const Addr PcJBitShift = 33;
 200     static const Addr PcTBitShift = 34;
 201     static const Addr PcModeMask = (ULL(1) << PcJBitShift) |
 202                                    (ULL(1) << PcTBitShift);
 203
 204     BitUnion32(SCTLR)
 205         Bitfield<30> te;  // Thumb Exception Enable
 206         Bitfield<29> afe; // Access flag enable
 207         Bitfield<28> tre; // TEX Remap bit
 208         Bitfield<27> nmfi;// Non-maskable fast interrupts enable
 209         Bitfield<25> ee;  // Exception Endianness bit
 210         Bitfield<24> ve;  // Interrupt vectors enable
 211         Bitfield<23> rao1;// Read as one
 212         Bitfield<22> u;   // Alignment (now unused)
 213         Bitfield<21> fi;  // Fast interrupts configuration enable
 214         Bitfield<18> rao2;// Read as one
 215         Bitfield<17> ha;  // Hardware access flag enable
 216         Bitfield<16> rao3;// Read as one
 217         Bitfield<14> rr;  // Round robin cache replacement
 218         Bitfield<13> v;   // Base address for exception vectors
 219         Bitfield<12> i;   // instruction cache enable
 220         Bitfield<11> z;   // branch prediction enable bit
 221         Bitfield<10> sw;  // Enable swp/swpb
 222         Bitfield<6,3> rao4;// Read as one
 223         Bitfield<7>  b;   // Endianness support (unused)
 224         Bitfield<2>  c;   // Cache enable bit
 225         Bitfield<1>  a;   // Alignment fault checking
 226         Bitfield<0>  m;   // MMU enable bit
 227     EndBitUnion(SCTLR)
 228 };
 229
 230 #endif // __ARCH_ARM_MISCREGS_HH__