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43 #ifndef __ARCH_ARM_MISCREGS_HH__
44 #define __ARCH_ARM_MISCREGS_HH__
49 #include "arch/arm/miscregs_types.hh"
50 #include "base/compiler.hh"
82 MISCREG_PRRR_MAIR0_NS,
85 MISCREG_NMRR_MAIR1_NS,
87 MISCREG_PMXEVTYPER_PMCCFILTR,
91 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
133 MISCREG_DBGAUTHSTATUS,
137 MISCREG_TEECR, // not in ARM DDI 0487A.b+
139 MISCREG_TEEHBR, // not in ARM DDI 0487A.b+
143 // AArch32 CP15 registers (system control)
275 MISCREG_TLBIIPAS2LIS,
278 MISCREG_TLBIALLNSNHIS,
335 MISCREG_CONTEXTIDR_NS,
336 MISCREG_CONTEXTIDR_S,
350 MISCREG_CNTP_TVAL_NS,
377 MISCREG_CNTP_CVAL_NS,
385 // AArch64 registers (Op0=2)
415 MISCREG_DBGVCR32_EL2,
421 MISCREG_DBGCLAIMSET_EL1,
422 MISCREG_DBGCLAIMCLR_EL1,
423 MISCREG_DBGAUTHSTATUS_EL1,
424 MISCREG_TEECR32_EL1, // not in ARM DDI 0487A.b+
425 MISCREG_TEEHBR32_EL1, // not in ARM DDI 0487A.b+
427 // AArch64 registers (Op0=1,3)
435 MISCREG_ID_MMFR0_EL1,
436 MISCREG_ID_MMFR1_EL1,
437 MISCREG_ID_MMFR2_EL1,
438 MISCREG_ID_MMFR3_EL1,
439 MISCREG_ID_ISAR0_EL1,
440 MISCREG_ID_ISAR1_EL1,
441 MISCREG_ID_ISAR2_EL1,
442 MISCREG_ID_ISAR3_EL1,
443 MISCREG_ID_ISAR4_EL1,
444 MISCREG_ID_ISAR5_EL1,
448 MISCREG_ID_AA64PFR0_EL1,
449 MISCREG_ID_AA64PFR1_EL1,
450 MISCREG_ID_AA64DFR0_EL1,
451 MISCREG_ID_AA64DFR1_EL1,
452 MISCREG_ID_AA64AFR0_EL1,
453 MISCREG_ID_AA64AFR1_EL1,
454 MISCREG_ID_AA64ISAR0_EL1,
455 MISCREG_ID_AA64ISAR1_EL1,
456 MISCREG_ID_AA64MMFR0_EL1,
457 MISCREG_ID_AA64MMFR1_EL1,
506 MISCREG_SPSR_IRQ_AA64,
507 MISCREG_SPSR_ABT_AA64,
508 MISCREG_SPSR_UND_AA64,
509 MISCREG_SPSR_FIQ_AA64,
546 MISCREG_AT_S12E1R_Xt,
547 MISCREG_AT_S12E1W_Xt,
548 MISCREG_AT_S12E0R_Xt,
549 MISCREG_AT_S12E0W_Xt,
552 MISCREG_TLBI_VMALLE1IS,
553 MISCREG_TLBI_VAE1IS_Xt,
554 MISCREG_TLBI_ASIDE1IS_Xt,
555 MISCREG_TLBI_VAAE1IS_Xt,
556 MISCREG_TLBI_VALE1IS_Xt,
557 MISCREG_TLBI_VAALE1IS_Xt,
558 MISCREG_TLBI_VMALLE1,
559 MISCREG_TLBI_VAE1_Xt,
560 MISCREG_TLBI_ASIDE1_Xt,
561 MISCREG_TLBI_VAAE1_Xt,
562 MISCREG_TLBI_VALE1_Xt,
563 MISCREG_TLBI_VAALE1_Xt,
564 MISCREG_TLBI_IPAS2E1IS_Xt,
565 MISCREG_TLBI_IPAS2LE1IS_Xt,
566 MISCREG_TLBI_ALLE2IS,
567 MISCREG_TLBI_VAE2IS_Xt,
568 MISCREG_TLBI_ALLE1IS,
569 MISCREG_TLBI_VALE2IS_Xt,
570 MISCREG_TLBI_VMALLS12E1IS,
571 MISCREG_TLBI_IPAS2E1_Xt,
572 MISCREG_TLBI_IPAS2LE1_Xt,
574 MISCREG_TLBI_VAE2_Xt,
576 MISCREG_TLBI_VALE2_Xt,
577 MISCREG_TLBI_VMALLS12E1,
578 MISCREG_TLBI_ALLE3IS,
579 MISCREG_TLBI_VAE3IS_Xt,
580 MISCREG_TLBI_VALE3IS_Xt,
582 MISCREG_TLBI_VAE3_Xt,
583 MISCREG_TLBI_VALE3_Xt,
584 MISCREG_PMINTENSET_EL1,
585 MISCREG_PMINTENCLR_EL1,
587 MISCREG_PMCNTENSET_EL0,
588 MISCREG_PMCNTENCLR_EL0,
589 MISCREG_PMOVSCLR_EL0,
595 MISCREG_PMXEVTYPER_EL0,
596 MISCREG_PMCCFILTR_EL0,
597 MISCREG_PMXEVCNTR_EL0,
598 MISCREG_PMUSERENR_EL0,
599 MISCREG_PMOVSSET_EL0,
616 MISCREG_CONTEXTIDR_EL1,
626 MISCREG_CNTP_TVAL_EL0,
627 MISCREG_CNTP_CTL_EL0,
628 MISCREG_CNTP_CVAL_EL0,
629 MISCREG_CNTV_TVAL_EL0,
630 MISCREG_CNTV_CTL_EL0,
631 MISCREG_CNTV_CVAL_EL0,
632 MISCREG_PMEVCNTR0_EL0,
633 MISCREG_PMEVCNTR1_EL0,
634 MISCREG_PMEVCNTR2_EL0,
635 MISCREG_PMEVCNTR3_EL0,
636 MISCREG_PMEVCNTR4_EL0,
637 MISCREG_PMEVCNTR5_EL0,
638 MISCREG_PMEVTYPER0_EL0,
639 MISCREG_PMEVTYPER1_EL0,
640 MISCREG_PMEVTYPER2_EL0,
641 MISCREG_PMEVTYPER3_EL0,
642 MISCREG_PMEVTYPER4_EL0,
643 MISCREG_PMEVTYPER5_EL0,
646 MISCREG_CNTHP_TVAL_EL2,
647 MISCREG_CNTHP_CTL_EL2,
648 MISCREG_CNTHP_CVAL_EL2,
649 MISCREG_CNTPS_TVAL_EL1,
650 MISCREG_CNTPS_CTL_EL1,
651 MISCREG_CNTPS_CVAL_EL1,
652 MISCREG_IL1DATA0_EL1,
653 MISCREG_IL1DATA1_EL1,
654 MISCREG_IL1DATA2_EL1,
655 MISCREG_IL1DATA3_EL1,
656 MISCREG_DL1DATA0_EL1,
657 MISCREG_DL1DATA1_EL1,
658 MISCREG_DL1DATA2_EL1,
659 MISCREG_DL1DATA3_EL1,
660 MISCREG_DL1DATA4_EL1,
662 MISCREG_CPUACTLR_EL1,
663 MISCREG_CPUECTLR_EL1,
664 MISCREG_CPUMERRSR_EL1,
665 MISCREG_L2MERRSR_EL1,
667 MISCREG_CONTEXTIDR_EL2,
669 // Introduced in ARMv8.1
671 MISCREG_CNTHV_CTL_EL2,
672 MISCREG_CNTHV_CVAL_EL2,
673 MISCREG_CNTHV_TVAL_EL2,
675 MISCREG_ID_AA64MMFR2_EL1,
677 // GICv3, CPU interface
679 MISCREG_ICC_IAR0_EL1,
680 MISCREG_ICC_EOIR0_EL1,
681 MISCREG_ICC_HPPIR0_EL1,
682 MISCREG_ICC_BPR0_EL1,
683 MISCREG_ICC_AP0R0_EL1,
684 MISCREG_ICC_AP0R1_EL1,
685 MISCREG_ICC_AP0R2_EL1,
686 MISCREG_ICC_AP0R3_EL1,
687 MISCREG_ICC_AP1R0_EL1,
688 MISCREG_ICC_AP1R0_EL1_NS,
689 MISCREG_ICC_AP1R0_EL1_S,
690 MISCREG_ICC_AP1R1_EL1,
691 MISCREG_ICC_AP1R1_EL1_NS,
692 MISCREG_ICC_AP1R1_EL1_S,
693 MISCREG_ICC_AP1R2_EL1,
694 MISCREG_ICC_AP1R2_EL1_NS,
695 MISCREG_ICC_AP1R2_EL1_S,
696 MISCREG_ICC_AP1R3_EL1,
697 MISCREG_ICC_AP1R3_EL1_NS,
698 MISCREG_ICC_AP1R3_EL1_S,
701 MISCREG_ICC_SGI1R_EL1,
702 MISCREG_ICC_ASGI1R_EL1,
703 MISCREG_ICC_SGI0R_EL1,
704 MISCREG_ICC_IAR1_EL1,
705 MISCREG_ICC_EOIR1_EL1,
706 MISCREG_ICC_HPPIR1_EL1,
707 MISCREG_ICC_BPR1_EL1,
708 MISCREG_ICC_BPR1_EL1_NS,
709 MISCREG_ICC_BPR1_EL1_S,
710 MISCREG_ICC_CTLR_EL1,
711 MISCREG_ICC_CTLR_EL1_NS,
712 MISCREG_ICC_CTLR_EL1_S,
714 MISCREG_ICC_SRE_EL1_NS,
715 MISCREG_ICC_SRE_EL1_S,
716 MISCREG_ICC_IGRPEN0_EL1,
717 MISCREG_ICC_IGRPEN1_EL1,
718 MISCREG_ICC_IGRPEN1_EL1_NS,
719 MISCREG_ICC_IGRPEN1_EL1_S,
721 MISCREG_ICC_CTLR_EL3,
723 MISCREG_ICC_IGRPEN1_EL3,
725 // GICv3, CPU interface, virtualization
726 MISCREG_ICH_AP0R0_EL2,
727 MISCREG_ICH_AP0R1_EL2,
728 MISCREG_ICH_AP0R2_EL2,
729 MISCREG_ICH_AP0R3_EL2,
730 MISCREG_ICH_AP1R0_EL2,
731 MISCREG_ICH_AP1R1_EL2,
732 MISCREG_ICH_AP1R2_EL2,
733 MISCREG_ICH_AP1R3_EL2,
736 MISCREG_ICH_MISR_EL2,
737 MISCREG_ICH_EISR_EL2,
738 MISCREG_ICH_ELRSR_EL2,
739 MISCREG_ICH_VMCR_EL2,
750 MISCREG_ICH_LR10_EL2,
751 MISCREG_ICH_LR11_EL2,
752 MISCREG_ICH_LR12_EL2,
753 MISCREG_ICH_LR13_EL2,
754 MISCREG_ICH_LR14_EL2,
755 MISCREG_ICH_LR15_EL2,
758 MISCREG_ICV_IAR0_EL1,
759 MISCREG_ICV_EOIR0_EL1,
760 MISCREG_ICV_HPPIR0_EL1,
761 MISCREG_ICV_BPR0_EL1,
762 MISCREG_ICV_AP0R0_EL1,
763 MISCREG_ICV_AP0R1_EL1,
764 MISCREG_ICV_AP0R2_EL1,
765 MISCREG_ICV_AP0R3_EL1,
766 MISCREG_ICV_AP1R0_EL1,
767 MISCREG_ICV_AP1R0_EL1_NS,
768 MISCREG_ICV_AP1R0_EL1_S,
769 MISCREG_ICV_AP1R1_EL1,
770 MISCREG_ICV_AP1R1_EL1_NS,
771 MISCREG_ICV_AP1R1_EL1_S,
772 MISCREG_ICV_AP1R2_EL1,
773 MISCREG_ICV_AP1R2_EL1_NS,
774 MISCREG_ICV_AP1R2_EL1_S,
775 MISCREG_ICV_AP1R3_EL1,
776 MISCREG_ICV_AP1R3_EL1_NS,
777 MISCREG_ICV_AP1R3_EL1_S,
780 MISCREG_ICV_SGI1R_EL1,
781 MISCREG_ICV_ASGI1R_EL1,
782 MISCREG_ICV_SGI0R_EL1,
783 MISCREG_ICV_IAR1_EL1,
784 MISCREG_ICV_EOIR1_EL1,
785 MISCREG_ICV_HPPIR1_EL1,
786 MISCREG_ICV_BPR1_EL1,
787 MISCREG_ICV_BPR1_EL1_NS,
788 MISCREG_ICV_BPR1_EL1_S,
789 MISCREG_ICV_CTLR_EL1,
790 MISCREG_ICV_CTLR_EL1_NS,
791 MISCREG_ICV_CTLR_EL1_S,
793 MISCREG_ICV_SRE_EL1_NS,
794 MISCREG_ICV_SRE_EL1_S,
795 MISCREG_ICV_IGRPEN0_EL1,
796 MISCREG_ICV_IGRPEN1_EL1,
797 MISCREG_ICV_IGRPEN1_EL1_NS,
798 MISCREG_ICV_IGRPEN1_EL1_S,
805 MISCREG_ICC_AP1R0_NS,
808 MISCREG_ICC_AP1R1_NS,
811 MISCREG_ICC_AP1R2_NS,
814 MISCREG_ICC_AP1R3_NS,
834 MISCREG_ICC_IGRPEN1_NS,
835 MISCREG_ICC_IGRPEN1_S,
895 MISCREG_ID_AA64ZFR0_EL1,
901 // NUM_PHYS_MISCREGS specifies the number of actual physical
902 // registers, not considering the following pseudo-registers
903 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
904 // Checkpointing should use this physical index when
905 // saving/restoring register values.
915 // Implementation defined register: this represent
916 // a pool of unimplemented registers whose access can throw
917 // either UNDEFINED or hypervisor trap exception.
918 MISCREG_IMPDEF_UNIMPL,
920 // RAS extension (unimplemented)
925 MISCREG_ERXSTATUS_EL1,
927 MISCREG_ERXMISC0_EL1,
928 MISCREG_ERXMISC1_EL1,
933 // Total number of Misc Registers: Physical + Dummy
939 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
940 // arch generic counter)
941 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
942 // tells whether the instruction should raise a
944 MISCREG_MUTEX, // True if the register corresponds to a pair of
945 // mutually exclusive registers
946 MISCREG_BANKED, // True if the register is banked between the two
947 // security states, and this is the parent node of the
948 // two banked registers
949 MISCREG_BANKED_CHILD, // The entry is one of the child registers that
950 // forms a banked set of regs (along with the
953 // Access permissions
959 // Privileged modes other than hypervisor or monitor
967 // Monitor mode, SCR.NS == 0
970 // Monitor mode, SCR.NS == 1
977 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
979 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
980 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
981 unsigned crm, unsigned opc2);
982 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
983 unsigned crn, unsigned crm,
985 // Whether a particular AArch64 system register is -always- read only.
986 bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
988 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
989 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
990 unsigned crm, unsigned opc2);
992 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
993 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
996 const char * const miscRegName[] = {
1026 "pmxevtyper_pmccfiltr",
1030 // AArch32 CP14 registers
1082 // AArch32 CP15 registers
1324 // AArch64 registers (Op0=2)
1362 "dbgauthstatus_el1",
1366 // AArch64 registers (Op0=1,3)
1503 "tlbi_ipas2e1is_xt",
1504 "tlbi_ipas2le1is_xt",
1509 "tlbi_vmalls12e1is",
1614 // GICv3, CPU interface
1655 "icc_igrpen1_el1_ns",
1656 "icc_igrpen1_el1_s",
1662 // GICv3, CPU interface, virtualization
1734 "icv_igrpen1_el1_ns",
1735 "icv_igrpen1_el1_s",
1859 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1860 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1862 // This mask selects bits of the CPSR that actually go in the CondCodes
1863 // integer register to allow renaming.
1864 static const uint32_t CondCodesMask = 0xF00F0000;
1865 static const uint32_t CpsrMaskQ = 0x08000000;
1867 // APSR (Application Program Status Register Mask). It is the user level
1868 // alias for the CPSR. The APSR is a subset of the CPSR. Although
1869 // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1871 // Bit[9] returns the value of CPSR.E.
1872 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1873 static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1875 // CPSR (Current Program Status Register Mask).
1876 static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1878 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1879 // integer register to allow renaming.
1880 static const uint32_t FpCondCodesMask = 0xF0000000;
1881 // This mask selects the cumulative FP exception flags of the FPSCR.
1882 static const uint32_t FpscrExcMask = 0x0000009F;
1883 // This mask selects the cumulative saturation flag of the FPSCR.
1884 static const uint32_t FpscrQcMask = 0x08000000;
1887 * Check for permission to read coprocessor registers.
1889 * Checks whether an instruction at the current program mode has
1890 * permissions to read the coprocessor registers. This function
1891 * returns whether the check is undefined and if not whether the
1892 * read access is permitted.
1894 * @param the misc reg indicating the coprocessor
1897 * @return a tuple of booleans: can_read, undefined
1899 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1903 * Check for permission to write coprocessor registers.
1905 * Checks whether an instruction at the current program mode has
1906 * permissions to write the coprocessor registers. This function
1907 * returns whether the check is undefined and if not whether the
1908 * write access is permitted.
1910 * @param the misc reg indicating the coprocessor
1913 * @return a tuple of booleans: can_write, undefined
1915 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1918 // Checks read access permissions to AArch64 system registers
1919 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1922 // Checks write access permissions to AArch64 system registers
1923 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1926 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1927 // for MCR/MRC instructions
1929 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
1931 // Flattens a misc reg index using the specified security state. This is
1932 // used for opperations (eg address translations) where the security
1933 // state of the register access may differ from the current state of the
1936 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
1938 // Takes a misc reg index and returns the root reg if its one of a set of
1941 preUnflattenMiscReg();
1944 unflattenMiscReg(int reg);
1948 #endif // __ARCH_ARM_MISCREGS_HH__