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arch-arm: Fix incorrect t{0,1}sz field in TTBCR
[gem5.git] / src / arch / arm / miscregs.hh
1 /*
2 * Copyright (c) 2010-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 * Giacomo Gabrielli
42 */
43 #ifndef __ARCH_ARM_MISCREGS_HH__
44 #define __ARCH_ARM_MISCREGS_HH__
45
46 #include <bitset>
47 #include <tuple>
48
49 #include "base/bitunion.hh"
50 #include "base/compiler.hh"
51
52 class ThreadContext;
53
54
55 namespace ArmISA
56 {
57 enum MiscRegIndex {
58 MISCREG_CPSR = 0, // 0
59 MISCREG_SPSR, // 1
60 MISCREG_SPSR_FIQ, // 2
61 MISCREG_SPSR_IRQ, // 3
62 MISCREG_SPSR_SVC, // 4
63 MISCREG_SPSR_MON, // 5
64 MISCREG_SPSR_ABT, // 6
65 MISCREG_SPSR_HYP, // 7
66 MISCREG_SPSR_UND, // 8
67 MISCREG_ELR_HYP, // 9
68 MISCREG_FPSID, // 10
69 MISCREG_FPSCR, // 11
70 MISCREG_MVFR1, // 12
71 MISCREG_MVFR0, // 13
72 MISCREG_FPEXC, // 14
73
74 // Helper registers
75 MISCREG_CPSR_MODE, // 15
76 MISCREG_CPSR_Q, // 16
77 MISCREG_FPSCR_EXC, // 17
78 MISCREG_FPSCR_QC, // 18
79 MISCREG_LOCKADDR, // 19
80 MISCREG_LOCKFLAG, // 20
81 MISCREG_PRRR_MAIR0, // 21
82 MISCREG_PRRR_MAIR0_NS, // 22
83 MISCREG_PRRR_MAIR0_S, // 23
84 MISCREG_NMRR_MAIR1, // 24
85 MISCREG_NMRR_MAIR1_NS, // 25
86 MISCREG_NMRR_MAIR1_S, // 26
87 MISCREG_PMXEVTYPER_PMCCFILTR, // 27
88 MISCREG_SCTLR_RST, // 28
89 MISCREG_SEV_MAILBOX, // 29
90
91 // AArch32 CP14 registers (debug/trace/ThumbEE/Jazelle control)
92 MISCREG_DBGDIDR, // 30
93 MISCREG_DBGDSCRint, // 31
94 MISCREG_DBGDCCINT, // 32
95 MISCREG_DBGDTRTXint, // 33
96 MISCREG_DBGDTRRXint, // 34
97 MISCREG_DBGWFAR, // 35
98 MISCREG_DBGVCR, // 36
99 MISCREG_DBGDTRRXext, // 37
100 MISCREG_DBGDSCRext, // 38
101 MISCREG_DBGDTRTXext, // 39
102 MISCREG_DBGOSECCR, // 40
103 MISCREG_DBGBVR0, // 41
104 MISCREG_DBGBVR1, // 42
105 MISCREG_DBGBVR2, // 43
106 MISCREG_DBGBVR3, // 44
107 MISCREG_DBGBVR4, // 45
108 MISCREG_DBGBVR5, // 46
109 MISCREG_DBGBCR0, // 47
110 MISCREG_DBGBCR1, // 48
111 MISCREG_DBGBCR2, // 49
112 MISCREG_DBGBCR3, // 50
113 MISCREG_DBGBCR4, // 51
114 MISCREG_DBGBCR5, // 52
115 MISCREG_DBGWVR0, // 53
116 MISCREG_DBGWVR1, // 54
117 MISCREG_DBGWVR2, // 55
118 MISCREG_DBGWVR3, // 56
119 MISCREG_DBGWCR0, // 57
120 MISCREG_DBGWCR1, // 58
121 MISCREG_DBGWCR2, // 59
122 MISCREG_DBGWCR3, // 60
123 MISCREG_DBGDRAR, // 61
124 MISCREG_DBGBXVR4, // 62
125 MISCREG_DBGBXVR5, // 63
126 MISCREG_DBGOSLAR, // 64
127 MISCREG_DBGOSLSR, // 65
128 MISCREG_DBGOSDLR, // 66
129 MISCREG_DBGPRCR, // 67
130 MISCREG_DBGDSAR, // 68
131 MISCREG_DBGCLAIMSET, // 69
132 MISCREG_DBGCLAIMCLR, // 70
133 MISCREG_DBGAUTHSTATUS, // 71
134 MISCREG_DBGDEVID2, // 72
135 MISCREG_DBGDEVID1, // 73
136 MISCREG_DBGDEVID0, // 74
137 MISCREG_TEECR, // 75, not in ARM DDI 0487A.b+
138 MISCREG_JIDR, // 76
139 MISCREG_TEEHBR, // 77, not in ARM DDI 0487A.b+
140 MISCREG_JOSCR, // 78
141 MISCREG_JMCR, // 79
142
143 // AArch32 CP15 registers (system control)
144 MISCREG_MIDR, // 80
145 MISCREG_CTR, // 81
146 MISCREG_TCMTR, // 82
147 MISCREG_TLBTR, // 83
148 MISCREG_MPIDR, // 84
149 MISCREG_REVIDR, // 85
150 MISCREG_ID_PFR0, // 86
151 MISCREG_ID_PFR1, // 87
152 MISCREG_ID_DFR0, // 88
153 MISCREG_ID_AFR0, // 89
154 MISCREG_ID_MMFR0, // 90
155 MISCREG_ID_MMFR1, // 91
156 MISCREG_ID_MMFR2, // 92
157 MISCREG_ID_MMFR3, // 93
158 MISCREG_ID_ISAR0, // 94
159 MISCREG_ID_ISAR1, // 95
160 MISCREG_ID_ISAR2, // 96
161 MISCREG_ID_ISAR3, // 97
162 MISCREG_ID_ISAR4, // 98
163 MISCREG_ID_ISAR5, // 99
164 MISCREG_CCSIDR, // 100
165 MISCREG_CLIDR, // 101
166 MISCREG_AIDR, // 102
167 MISCREG_CSSELR, // 103
168 MISCREG_CSSELR_NS, // 104
169 MISCREG_CSSELR_S, // 105
170 MISCREG_VPIDR, // 106
171 MISCREG_VMPIDR, // 107
172 MISCREG_SCTLR, // 108
173 MISCREG_SCTLR_NS, // 109
174 MISCREG_SCTLR_S, // 110
175 MISCREG_ACTLR, // 111
176 MISCREG_ACTLR_NS, // 112
177 MISCREG_ACTLR_S, // 113
178 MISCREG_CPACR, // 114
179 MISCREG_SCR, // 115
180 MISCREG_SDER, // 116
181 MISCREG_NSACR, // 117
182 MISCREG_HSCTLR, // 118
183 MISCREG_HACTLR, // 119
184 MISCREG_HCR, // 120
185 MISCREG_HDCR, // 121
186 MISCREG_HCPTR, // 122
187 MISCREG_HSTR, // 123
188 MISCREG_HACR, // 124
189 MISCREG_TTBR0, // 125
190 MISCREG_TTBR0_NS, // 126
191 MISCREG_TTBR0_S, // 127
192 MISCREG_TTBR1, // 128
193 MISCREG_TTBR1_NS, // 129
194 MISCREG_TTBR1_S, // 130
195 MISCREG_TTBCR, // 131
196 MISCREG_TTBCR_NS, // 132
197 MISCREG_TTBCR_S, // 133
198 MISCREG_HTCR, // 134
199 MISCREG_VTCR, // 135
200 MISCREG_DACR, // 136
201 MISCREG_DACR_NS, // 137
202 MISCREG_DACR_S, // 138
203 MISCREG_DFSR, // 139
204 MISCREG_DFSR_NS, // 140
205 MISCREG_DFSR_S, // 141
206 MISCREG_IFSR, // 142
207 MISCREG_IFSR_NS, // 143
208 MISCREG_IFSR_S, // 144
209 MISCREG_ADFSR, // 145
210 MISCREG_ADFSR_NS, // 146
211 MISCREG_ADFSR_S, // 147
212 MISCREG_AIFSR, // 148
213 MISCREG_AIFSR_NS, // 149
214 MISCREG_AIFSR_S, // 150
215 MISCREG_HADFSR, // 151
216 MISCREG_HAIFSR, // 152
217 MISCREG_HSR, // 153
218 MISCREG_DFAR, // 154
219 MISCREG_DFAR_NS, // 155
220 MISCREG_DFAR_S, // 156
221 MISCREG_IFAR, // 157
222 MISCREG_IFAR_NS, // 158
223 MISCREG_IFAR_S, // 159
224 MISCREG_HDFAR, // 160
225 MISCREG_HIFAR, // 161
226 MISCREG_HPFAR, // 162
227 MISCREG_ICIALLUIS, // 163
228 MISCREG_BPIALLIS, // 164
229 MISCREG_PAR, // 165
230 MISCREG_PAR_NS, // 166
231 MISCREG_PAR_S, // 167
232 MISCREG_ICIALLU, // 168
233 MISCREG_ICIMVAU, // 169
234 MISCREG_CP15ISB, // 170
235 MISCREG_BPIALL, // 171
236 MISCREG_BPIMVA, // 172
237 MISCREG_DCIMVAC, // 173
238 MISCREG_DCISW, // 174
239 MISCREG_ATS1CPR, // 175
240 MISCREG_ATS1CPW, // 176
241 MISCREG_ATS1CUR, // 177
242 MISCREG_ATS1CUW, // 178
243 MISCREG_ATS12NSOPR, // 179
244 MISCREG_ATS12NSOPW, // 180
245 MISCREG_ATS12NSOUR, // 181
246 MISCREG_ATS12NSOUW, // 182
247 MISCREG_DCCMVAC, // 183
248 MISCREG_DCCSW, // 184
249 MISCREG_CP15DSB, // 185
250 MISCREG_CP15DMB, // 186
251 MISCREG_DCCMVAU, // 187
252 MISCREG_DCCIMVAC, // 188
253 MISCREG_DCCISW, // 189
254 MISCREG_ATS1HR, // 190
255 MISCREG_ATS1HW, // 191
256 MISCREG_TLBIALLIS, // 192
257 MISCREG_TLBIMVAIS, // 193
258 MISCREG_TLBIASIDIS, // 194
259 MISCREG_TLBIMVAAIS, // 195
260 MISCREG_TLBIMVALIS, // 196
261 MISCREG_TLBIMVAALIS, // 197
262 MISCREG_ITLBIALL, // 198
263 MISCREG_ITLBIMVA, // 199
264 MISCREG_ITLBIASID, // 200
265 MISCREG_DTLBIALL, // 201
266 MISCREG_DTLBIMVA, // 202
267 MISCREG_DTLBIASID, // 203
268 MISCREG_TLBIALL, // 204
269 MISCREG_TLBIMVA, // 205
270 MISCREG_TLBIASID, // 206
271 MISCREG_TLBIMVAA, // 207
272 MISCREG_TLBIMVAL, // 208
273 MISCREG_TLBIMVAAL, // 209
274 MISCREG_TLBIIPAS2IS, // 210
275 MISCREG_TLBIIPAS2LIS, // 211
276 MISCREG_TLBIALLHIS, // 212
277 MISCREG_TLBIMVAHIS, // 213
278 MISCREG_TLBIALLNSNHIS, // 214
279 MISCREG_TLBIMVALHIS, // 215
280 MISCREG_TLBIIPAS2, // 216
281 MISCREG_TLBIIPAS2L, // 217
282 MISCREG_TLBIALLH, // 218
283 MISCREG_TLBIMVAH, // 219
284 MISCREG_TLBIALLNSNH, // 220
285 MISCREG_TLBIMVALH, // 221
286 MISCREG_PMCR, // 222
287 MISCREG_PMCNTENSET, // 223
288 MISCREG_PMCNTENCLR, // 224
289 MISCREG_PMOVSR, // 225
290 MISCREG_PMSWINC, // 226
291 MISCREG_PMSELR, // 227
292 MISCREG_PMCEID0, // 228
293 MISCREG_PMCEID1, // 229
294 MISCREG_PMCCNTR, // 230
295 MISCREG_PMXEVTYPER, // 231
296 MISCREG_PMCCFILTR, // 232
297 MISCREG_PMXEVCNTR, // 233
298 MISCREG_PMUSERENR, // 234
299 MISCREG_PMINTENSET, // 235
300 MISCREG_PMINTENCLR, // 236
301 MISCREG_PMOVSSET, // 237
302 MISCREG_L2CTLR, // 238
303 MISCREG_L2ECTLR, // 239
304 MISCREG_PRRR, // 240
305 MISCREG_PRRR_NS, // 241
306 MISCREG_PRRR_S, // 242
307 MISCREG_MAIR0, // 243
308 MISCREG_MAIR0_NS, // 244
309 MISCREG_MAIR0_S, // 245
310 MISCREG_NMRR, // 246
311 MISCREG_NMRR_NS, // 247
312 MISCREG_NMRR_S, // 248
313 MISCREG_MAIR1, // 249
314 MISCREG_MAIR1_NS, // 250
315 MISCREG_MAIR1_S, // 251
316 MISCREG_AMAIR0, // 252
317 MISCREG_AMAIR0_NS, // 253
318 MISCREG_AMAIR0_S, // 254
319 MISCREG_AMAIR1, // 255
320 MISCREG_AMAIR1_NS, // 256
321 MISCREG_AMAIR1_S, // 257
322 MISCREG_HMAIR0, // 258
323 MISCREG_HMAIR1, // 259
324 MISCREG_HAMAIR0, // 260
325 MISCREG_HAMAIR1, // 261
326 MISCREG_VBAR, // 262
327 MISCREG_VBAR_NS, // 263
328 MISCREG_VBAR_S, // 264
329 MISCREG_MVBAR, // 265
330 MISCREG_RMR, // 266
331 MISCREG_ISR, // 267
332 MISCREG_HVBAR, // 268
333 MISCREG_FCSEIDR, // 269
334 MISCREG_CONTEXTIDR, // 270
335 MISCREG_CONTEXTIDR_NS, // 271
336 MISCREG_CONTEXTIDR_S, // 272
337 MISCREG_TPIDRURW, // 273
338 MISCREG_TPIDRURW_NS, // 274
339 MISCREG_TPIDRURW_S, // 275
340 MISCREG_TPIDRURO, // 276
341 MISCREG_TPIDRURO_NS, // 277
342 MISCREG_TPIDRURO_S, // 278
343 MISCREG_TPIDRPRW, // 279
344 MISCREG_TPIDRPRW_NS, // 280
345 MISCREG_TPIDRPRW_S, // 281
346 MISCREG_HTPIDR, // 282
347 MISCREG_CNTFRQ, // 283
348 MISCREG_CNTKCTL, // 284
349 MISCREG_CNTP_TVAL, // 285
350 MISCREG_CNTP_TVAL_NS, // 286
351 MISCREG_CNTP_TVAL_S, // 287
352 MISCREG_CNTP_CTL, // 288
353 MISCREG_CNTP_CTL_NS, // 289
354 MISCREG_CNTP_CTL_S, // 290
355 MISCREG_CNTV_TVAL, // 291
356 MISCREG_CNTV_CTL, // 292
357 MISCREG_CNTHCTL, // 293
358 MISCREG_CNTHP_TVAL, // 294
359 MISCREG_CNTHP_CTL, // 295
360 MISCREG_IL1DATA0, // 296
361 MISCREG_IL1DATA1, // 297
362 MISCREG_IL1DATA2, // 298
363 MISCREG_IL1DATA3, // 299
364 MISCREG_DL1DATA0, // 300
365 MISCREG_DL1DATA1, // 301
366 MISCREG_DL1DATA2, // 302
367 MISCREG_DL1DATA3, // 303
368 MISCREG_DL1DATA4, // 304
369 MISCREG_RAMINDEX, // 305
370 MISCREG_L2ACTLR, // 306
371 MISCREG_CBAR, // 307
372 MISCREG_HTTBR, // 308
373 MISCREG_VTTBR, // 309
374 MISCREG_CNTPCT, // 310
375 MISCREG_CNTVCT, // 311
376 MISCREG_CNTP_CVAL, // 312
377 MISCREG_CNTP_CVAL_NS, // 313
378 MISCREG_CNTP_CVAL_S, // 314
379 MISCREG_CNTV_CVAL, // 315
380 MISCREG_CNTVOFF, // 316
381 MISCREG_CNTHP_CVAL, // 317
382 MISCREG_CPUMERRSR, // 318
383 MISCREG_L2MERRSR, // 319
384
385 // AArch64 registers (Op0=2)
386 MISCREG_MDCCINT_EL1, // 320
387 MISCREG_OSDTRRX_EL1, // 321
388 MISCREG_MDSCR_EL1, // 322
389 MISCREG_OSDTRTX_EL1, // 323
390 MISCREG_OSECCR_EL1, // 324
391 MISCREG_DBGBVR0_EL1, // 325
392 MISCREG_DBGBVR1_EL1, // 326
393 MISCREG_DBGBVR2_EL1, // 327
394 MISCREG_DBGBVR3_EL1, // 328
395 MISCREG_DBGBVR4_EL1, // 329
396 MISCREG_DBGBVR5_EL1, // 330
397 MISCREG_DBGBCR0_EL1, // 331
398 MISCREG_DBGBCR1_EL1, // 332
399 MISCREG_DBGBCR2_EL1, // 333
400 MISCREG_DBGBCR3_EL1, // 334
401 MISCREG_DBGBCR4_EL1, // 335
402 MISCREG_DBGBCR5_EL1, // 336
403 MISCREG_DBGWVR0_EL1, // 337
404 MISCREG_DBGWVR1_EL1, // 338
405 MISCREG_DBGWVR2_EL1, // 339
406 MISCREG_DBGWVR3_EL1, // 340
407 MISCREG_DBGWCR0_EL1, // 341
408 MISCREG_DBGWCR1_EL1, // 342
409 MISCREG_DBGWCR2_EL1, // 343
410 MISCREG_DBGWCR3_EL1, // 344
411 MISCREG_MDCCSR_EL0, // 345
412 MISCREG_MDDTR_EL0, // 346
413 MISCREG_MDDTRTX_EL0, // 347
414 MISCREG_MDDTRRX_EL0, // 348
415 MISCREG_DBGVCR32_EL2, // 349
416 MISCREG_MDRAR_EL1, // 350
417 MISCREG_OSLAR_EL1, // 351
418 MISCREG_OSLSR_EL1, // 352
419 MISCREG_OSDLR_EL1, // 353
420 MISCREG_DBGPRCR_EL1, // 354
421 MISCREG_DBGCLAIMSET_EL1, // 355
422 MISCREG_DBGCLAIMCLR_EL1, // 356
423 MISCREG_DBGAUTHSTATUS_EL1, // 357
424 MISCREG_TEECR32_EL1, // 358, not in ARM DDI 0487A.b+
425 MISCREG_TEEHBR32_EL1, // 359, not in ARM DDI 0487A.b+
426
427 // AArch64 registers (Op0=1,3)
428 MISCREG_MIDR_EL1, // 360
429 MISCREG_MPIDR_EL1, // 361
430 MISCREG_REVIDR_EL1, // 362
431 MISCREG_ID_PFR0_EL1, // 363
432 MISCREG_ID_PFR1_EL1, // 364
433 MISCREG_ID_DFR0_EL1, // 365
434 MISCREG_ID_AFR0_EL1, // 366
435 MISCREG_ID_MMFR0_EL1, // 367
436 MISCREG_ID_MMFR1_EL1, // 368
437 MISCREG_ID_MMFR2_EL1, // 369
438 MISCREG_ID_MMFR3_EL1, // 370
439 MISCREG_ID_ISAR0_EL1, // 371
440 MISCREG_ID_ISAR1_EL1, // 372
441 MISCREG_ID_ISAR2_EL1, // 373
442 MISCREG_ID_ISAR3_EL1, // 374
443 MISCREG_ID_ISAR4_EL1, // 375
444 MISCREG_ID_ISAR5_EL1, // 376
445 MISCREG_MVFR0_EL1, // 377
446 MISCREG_MVFR1_EL1, // 378
447 MISCREG_MVFR2_EL1, // 379
448 MISCREG_ID_AA64PFR0_EL1, // 380
449 MISCREG_ID_AA64PFR1_EL1, // 381
450 MISCREG_ID_AA64DFR0_EL1, // 382
451 MISCREG_ID_AA64DFR1_EL1, // 383
452 MISCREG_ID_AA64AFR0_EL1, // 384
453 MISCREG_ID_AA64AFR1_EL1, // 385
454 MISCREG_ID_AA64ISAR0_EL1, // 386
455 MISCREG_ID_AA64ISAR1_EL1, // 387
456 MISCREG_ID_AA64MMFR0_EL1, // 388
457 MISCREG_ID_AA64MMFR1_EL1, // 389
458 MISCREG_CCSIDR_EL1, // 390
459 MISCREG_CLIDR_EL1, // 391
460 MISCREG_AIDR_EL1, // 392
461 MISCREG_CSSELR_EL1, // 393
462 MISCREG_CTR_EL0, // 394
463 MISCREG_DCZID_EL0, // 395
464 MISCREG_VPIDR_EL2, // 396
465 MISCREG_VMPIDR_EL2, // 397
466 MISCREG_SCTLR_EL1, // 398
467 MISCREG_ACTLR_EL1, // 399
468 MISCREG_CPACR_EL1, // 400
469 MISCREG_SCTLR_EL2, // 401
470 MISCREG_ACTLR_EL2, // 402
471 MISCREG_HCR_EL2, // 403
472 MISCREG_MDCR_EL2, // 404
473 MISCREG_CPTR_EL2, // 405
474 MISCREG_HSTR_EL2, // 406
475 MISCREG_HACR_EL2, // 407
476 MISCREG_SCTLR_EL3, // 408
477 MISCREG_ACTLR_EL3, // 409
478 MISCREG_SCR_EL3, // 410
479 MISCREG_SDER32_EL3, // 411
480 MISCREG_CPTR_EL3, // 412
481 MISCREG_MDCR_EL3, // 413
482 MISCREG_TTBR0_EL1, // 414
483 MISCREG_TTBR1_EL1, // 415
484 MISCREG_TCR_EL1, // 416
485 MISCREG_TTBR0_EL2, // 417
486 MISCREG_TCR_EL2, // 418
487 MISCREG_VTTBR_EL2, // 419
488 MISCREG_VTCR_EL2, // 420
489 MISCREG_TTBR0_EL3, // 421
490 MISCREG_TCR_EL3, // 422
491 MISCREG_DACR32_EL2, // 423
492 MISCREG_SPSR_EL1, // 424
493 MISCREG_ELR_EL1, // 425
494 MISCREG_SP_EL0, // 426
495 MISCREG_SPSEL, // 427
496 MISCREG_CURRENTEL, // 428
497 MISCREG_NZCV, // 429
498 MISCREG_DAIF, // 430
499 MISCREG_FPCR, // 431
500 MISCREG_FPSR, // 432
501 MISCREG_DSPSR_EL0, // 433
502 MISCREG_DLR_EL0, // 434
503 MISCREG_SPSR_EL2, // 435
504 MISCREG_ELR_EL2, // 436
505 MISCREG_SP_EL1, // 437
506 MISCREG_SPSR_IRQ_AA64, // 438
507 MISCREG_SPSR_ABT_AA64, // 439
508 MISCREG_SPSR_UND_AA64, // 440
509 MISCREG_SPSR_FIQ_AA64, // 441
510 MISCREG_SPSR_EL3, // 442
511 MISCREG_ELR_EL3, // 443
512 MISCREG_SP_EL2, // 444
513 MISCREG_AFSR0_EL1, // 445
514 MISCREG_AFSR1_EL1, // 446
515 MISCREG_ESR_EL1, // 447
516 MISCREG_IFSR32_EL2, // 448
517 MISCREG_AFSR0_EL2, // 449
518 MISCREG_AFSR1_EL2, // 450
519 MISCREG_ESR_EL2, // 451
520 MISCREG_FPEXC32_EL2, // 452
521 MISCREG_AFSR0_EL3, // 453
522 MISCREG_AFSR1_EL3, // 454
523 MISCREG_ESR_EL3, // 455
524 MISCREG_FAR_EL1, // 456
525 MISCREG_FAR_EL2, // 457
526 MISCREG_HPFAR_EL2, // 458
527 MISCREG_FAR_EL3, // 459
528 MISCREG_IC_IALLUIS, // 460
529 MISCREG_PAR_EL1, // 461
530 MISCREG_IC_IALLU, // 462
531 MISCREG_DC_IVAC_Xt, // 463
532 MISCREG_DC_ISW_Xt, // 464
533 MISCREG_AT_S1E1R_Xt, // 465
534 MISCREG_AT_S1E1W_Xt, // 466
535 MISCREG_AT_S1E0R_Xt, // 467
536 MISCREG_AT_S1E0W_Xt, // 468
537 MISCREG_DC_CSW_Xt, // 469
538 MISCREG_DC_CISW_Xt, // 470
539 MISCREG_DC_ZVA_Xt, // 471
540 MISCREG_IC_IVAU_Xt, // 472
541 MISCREG_DC_CVAC_Xt, // 473
542 MISCREG_DC_CVAU_Xt, // 474
543 MISCREG_DC_CIVAC_Xt, // 475
544 MISCREG_AT_S1E2R_Xt, // 476
545 MISCREG_AT_S1E2W_Xt, // 477
546 MISCREG_AT_S12E1R_Xt, // 478
547 MISCREG_AT_S12E1W_Xt, // 479
548 MISCREG_AT_S12E0R_Xt, // 480
549 MISCREG_AT_S12E0W_Xt, // 481
550 MISCREG_AT_S1E3R_Xt, // 482
551 MISCREG_AT_S1E3W_Xt, // 483
552 MISCREG_TLBI_VMALLE1IS, // 484
553 MISCREG_TLBI_VAE1IS_Xt, // 485
554 MISCREG_TLBI_ASIDE1IS_Xt, // 486
555 MISCREG_TLBI_VAAE1IS_Xt, // 487
556 MISCREG_TLBI_VALE1IS_Xt, // 488
557 MISCREG_TLBI_VAALE1IS_Xt, // 489
558 MISCREG_TLBI_VMALLE1, // 490
559 MISCREG_TLBI_VAE1_Xt, // 491
560 MISCREG_TLBI_ASIDE1_Xt, // 492
561 MISCREG_TLBI_VAAE1_Xt, // 493
562 MISCREG_TLBI_VALE1_Xt, // 494
563 MISCREG_TLBI_VAALE1_Xt, // 495
564 MISCREG_TLBI_IPAS2E1IS_Xt, // 496
565 MISCREG_TLBI_IPAS2LE1IS_Xt, // 497
566 MISCREG_TLBI_ALLE2IS, // 498
567 MISCREG_TLBI_VAE2IS_Xt, // 499
568 MISCREG_TLBI_ALLE1IS, // 500
569 MISCREG_TLBI_VALE2IS_Xt, // 501
570 MISCREG_TLBI_VMALLS12E1IS, // 502
571 MISCREG_TLBI_IPAS2E1_Xt, // 503
572 MISCREG_TLBI_IPAS2LE1_Xt, // 504
573 MISCREG_TLBI_ALLE2, // 505
574 MISCREG_TLBI_VAE2_Xt, // 506
575 MISCREG_TLBI_ALLE1, // 507
576 MISCREG_TLBI_VALE2_Xt, // 508
577 MISCREG_TLBI_VMALLS12E1, // 509
578 MISCREG_TLBI_ALLE3IS, // 510
579 MISCREG_TLBI_VAE3IS_Xt, // 511
580 MISCREG_TLBI_VALE3IS_Xt, // 512
581 MISCREG_TLBI_ALLE3, // 513
582 MISCREG_TLBI_VAE3_Xt, // 514
583 MISCREG_TLBI_VALE3_Xt, // 515
584 MISCREG_PMINTENSET_EL1, // 516
585 MISCREG_PMINTENCLR_EL1, // 517
586 MISCREG_PMCR_EL0, // 518
587 MISCREG_PMCNTENSET_EL0, // 519
588 MISCREG_PMCNTENCLR_EL0, // 520
589 MISCREG_PMOVSCLR_EL0, // 521
590 MISCREG_PMSWINC_EL0, // 522
591 MISCREG_PMSELR_EL0, // 523
592 MISCREG_PMCEID0_EL0, // 524
593 MISCREG_PMCEID1_EL0, // 525
594 MISCREG_PMCCNTR_EL0, // 526
595 MISCREG_PMXEVTYPER_EL0, // 527
596 MISCREG_PMCCFILTR_EL0, // 528
597 MISCREG_PMXEVCNTR_EL0, // 529
598 MISCREG_PMUSERENR_EL0, // 530
599 MISCREG_PMOVSSET_EL0, // 531
600 MISCREG_MAIR_EL1, // 532
601 MISCREG_AMAIR_EL1, // 533
602 MISCREG_MAIR_EL2, // 534
603 MISCREG_AMAIR_EL2, // 535
604 MISCREG_MAIR_EL3, // 536
605 MISCREG_AMAIR_EL3, // 537
606 MISCREG_L2CTLR_EL1, // 538
607 MISCREG_L2ECTLR_EL1, // 539
608 MISCREG_VBAR_EL1, // 540
609 MISCREG_RVBAR_EL1, // 541
610 MISCREG_ISR_EL1, // 542
611 MISCREG_VBAR_EL2, // 543
612 MISCREG_RVBAR_EL2, // 544
613 MISCREG_VBAR_EL3, // 545
614 MISCREG_RVBAR_EL3, // 546
615 MISCREG_RMR_EL3, // 547
616 MISCREG_CONTEXTIDR_EL1, // 548
617 MISCREG_TPIDR_EL1, // 549
618 MISCREG_TPIDR_EL0, // 550
619 MISCREG_TPIDRRO_EL0, // 551
620 MISCREG_TPIDR_EL2, // 552
621 MISCREG_TPIDR_EL3, // 553
622 MISCREG_CNTKCTL_EL1, // 554
623 MISCREG_CNTFRQ_EL0, // 555
624 MISCREG_CNTPCT_EL0, // 556
625 MISCREG_CNTVCT_EL0, // 557
626 MISCREG_CNTP_TVAL_EL0, // 558
627 MISCREG_CNTP_CTL_EL0, // 559
628 MISCREG_CNTP_CVAL_EL0, // 560
629 MISCREG_CNTV_TVAL_EL0, // 561
630 MISCREG_CNTV_CTL_EL0, // 562
631 MISCREG_CNTV_CVAL_EL0, // 563
632 MISCREG_PMEVCNTR0_EL0, // 564
633 MISCREG_PMEVCNTR1_EL0, // 565
634 MISCREG_PMEVCNTR2_EL0, // 566
635 MISCREG_PMEVCNTR3_EL0, // 567
636 MISCREG_PMEVCNTR4_EL0, // 568
637 MISCREG_PMEVCNTR5_EL0, // 569
638 MISCREG_PMEVTYPER0_EL0, // 570
639 MISCREG_PMEVTYPER1_EL0, // 571
640 MISCREG_PMEVTYPER2_EL0, // 572
641 MISCREG_PMEVTYPER3_EL0, // 573
642 MISCREG_PMEVTYPER4_EL0, // 574
643 MISCREG_PMEVTYPER5_EL0, // 575
644 MISCREG_CNTVOFF_EL2, // 576
645 MISCREG_CNTHCTL_EL2, // 577
646 MISCREG_CNTHP_TVAL_EL2, // 578
647 MISCREG_CNTHP_CTL_EL2, // 579
648 MISCREG_CNTHP_CVAL_EL2, // 580
649 MISCREG_CNTPS_TVAL_EL1, // 581
650 MISCREG_CNTPS_CTL_EL1, // 582
651 MISCREG_CNTPS_CVAL_EL1, // 583
652 MISCREG_IL1DATA0_EL1, // 584
653 MISCREG_IL1DATA1_EL1, // 585
654 MISCREG_IL1DATA2_EL1, // 586
655 MISCREG_IL1DATA3_EL1, // 587
656 MISCREG_DL1DATA0_EL1, // 588
657 MISCREG_DL1DATA1_EL1, // 589
658 MISCREG_DL1DATA2_EL1, // 590
659 MISCREG_DL1DATA3_EL1, // 591
660 MISCREG_DL1DATA4_EL1, // 592
661 MISCREG_L2ACTLR_EL1, // 593
662 MISCREG_CPUACTLR_EL1, // 594
663 MISCREG_CPUECTLR_EL1, // 595
664 MISCREG_CPUMERRSR_EL1, // 596
665 MISCREG_L2MERRSR_EL1, // 597
666 MISCREG_CBAR_EL1, // 598
667 MISCREG_CONTEXTIDR_EL2, // 599
668
669 // Introduced in ARMv8.1
670 MISCREG_TTBR1_EL2, // 600
671
672 // These MISCREG_FREESLOT are available Misc Register
673 // slots for future registers to be implemented.
674 MISCREG_FREESLOT_1, // 601
675 MISCREG_FREESLOT_2, // 602
676 MISCREG_FREESLOT_3, // 603
677 MISCREG_FREESLOT_4, // 604
678 MISCREG_FREESLOT_5, // 605
679
680 // NUM_PHYS_MISCREGS specifies the number of actual physical
681 // registers, not considering the following pseudo-registers
682 // (dummy registers), like UNKNOWN, CP15_UNIMPL, MISCREG_IMPDEF_UNIMPL.
683 // Checkpointing should use this physical index when
684 // saving/restoring register values.
685 NUM_PHYS_MISCREGS = 606, // 606
686
687 // Dummy registers
688 MISCREG_NOP,
689 MISCREG_RAZ,
690 MISCREG_CP14_UNIMPL,
691 MISCREG_CP15_UNIMPL,
692 MISCREG_UNKNOWN,
693
694 // Implementation defined register: this represent
695 // a pool of unimplemented registers whose access can throw
696 // either UNDEFINED or hypervisor trap exception.
697 MISCREG_IMPDEF_UNIMPL,
698
699 // Total number of Misc Registers: Physical + Dummy
700 NUM_MISCREGS
701 };
702
703 enum MiscRegInfo {
704 MISCREG_IMPLEMENTED,
705 MISCREG_UNVERIFIABLE, // Does the value change on every read (e.g. a
706 // arch generic counter)
707 MISCREG_WARN_NOT_FAIL, // If MISCREG_IMPLEMENTED is deasserted, it
708 // tells whether the instruction should raise a
709 // warning or fail
710 MISCREG_MUTEX, // True if the register corresponds to a pair of
711 // mutually exclusive registers
712 MISCREG_BANKED, // True if the register is banked between the two
713 // security states, and this is the parent node of the
714 // two banked registers
715 MISCREG_BANKED_CHILD, // The entry is one of the child registers that
716 // forms a banked set of regs (along with the
717 // other child regs)
718
719 // Access permissions
720 // User mode
721 MISCREG_USR_NS_RD,
722 MISCREG_USR_NS_WR,
723 MISCREG_USR_S_RD,
724 MISCREG_USR_S_WR,
725 // Privileged modes other than hypervisor or monitor
726 MISCREG_PRI_NS_RD,
727 MISCREG_PRI_NS_WR,
728 MISCREG_PRI_S_RD,
729 MISCREG_PRI_S_WR,
730 // Hypervisor mode
731 MISCREG_HYP_RD,
732 MISCREG_HYP_WR,
733 // Monitor mode, SCR.NS == 0
734 MISCREG_MON_NS0_RD,
735 MISCREG_MON_NS0_WR,
736 // Monitor mode, SCR.NS == 1
737 MISCREG_MON_NS1_RD,
738 MISCREG_MON_NS1_WR,
739
740 NUM_MISCREG_INFOS
741 };
742
743 extern std::bitset<NUM_MISCREG_INFOS> miscRegInfo[NUM_MISCREGS];
744
745 // Decodes 32-bit CP14 registers accessible through MCR/MRC instructions
746 MiscRegIndex decodeCP14Reg(unsigned crn, unsigned opc1,
747 unsigned crm, unsigned opc2);
748 MiscRegIndex decodeAArch64SysReg(unsigned op0, unsigned op1,
749 unsigned crn, unsigned crm,
750 unsigned op2);
751 // Whether a particular AArch64 system register is -always- read only.
752 bool aarch64SysRegReadOnly(MiscRegIndex miscReg);
753
754 // Decodes 32-bit CP15 registers accessible through MCR/MRC instructions
755 MiscRegIndex decodeCP15Reg(unsigned crn, unsigned opc1,
756 unsigned crm, unsigned opc2);
757
758 // Decodes 64-bit CP15 registers accessible through MCRR/MRRC instructions
759 MiscRegIndex decodeCP15Reg64(unsigned crm, unsigned opc1);
760
761
762 const char * const miscRegName[] = {
763 "cpsr",
764 "spsr",
765 "spsr_fiq",
766 "spsr_irq",
767 "spsr_svc",
768 "spsr_mon",
769 "spsr_abt",
770 "spsr_hyp",
771 "spsr_und",
772 "elr_hyp",
773 "fpsid",
774 "fpscr",
775 "mvfr1",
776 "mvfr0",
777 "fpexc",
778
779 // Helper registers
780 "cpsr_mode",
781 "cpsr_q",
782 "fpscr_exc",
783 "fpscr_qc",
784 "lockaddr",
785 "lockflag",
786 "prrr_mair0",
787 "prrr_mair0_ns",
788 "prrr_mair0_s",
789 "nmrr_mair1",
790 "nmrr_mair1_ns",
791 "nmrr_mair1_s",
792 "pmxevtyper_pmccfiltr",
793 "sctlr_rst",
794 "sev_mailbox",
795
796 // AArch32 CP14 registers
797 "dbgdidr",
798 "dbgdscrint",
799 "dbgdccint",
800 "dbgdtrtxint",
801 "dbgdtrrxint",
802 "dbgwfar",
803 "dbgvcr",
804 "dbgdtrrxext",
805 "dbgdscrext",
806 "dbgdtrtxext",
807 "dbgoseccr",
808 "dbgbvr0",
809 "dbgbvr1",
810 "dbgbvr2",
811 "dbgbvr3",
812 "dbgbvr4",
813 "dbgbvr5",
814 "dbgbcr0",
815 "dbgbcr1",
816 "dbgbcr2",
817 "dbgbcr3",
818 "dbgbcr4",
819 "dbgbcr5",
820 "dbgwvr0",
821 "dbgwvr1",
822 "dbgwvr2",
823 "dbgwvr3",
824 "dbgwcr0",
825 "dbgwcr1",
826 "dbgwcr2",
827 "dbgwcr3",
828 "dbgdrar",
829 "dbgbxvr4",
830 "dbgbxvr5",
831 "dbgoslar",
832 "dbgoslsr",
833 "dbgosdlr",
834 "dbgprcr",
835 "dbgdsar",
836 "dbgclaimset",
837 "dbgclaimclr",
838 "dbgauthstatus",
839 "dbgdevid2",
840 "dbgdevid1",
841 "dbgdevid0",
842 "teecr",
843 "jidr",
844 "teehbr",
845 "joscr",
846 "jmcr",
847
848 // AArch32 CP15 registers
849 "midr",
850 "ctr",
851 "tcmtr",
852 "tlbtr",
853 "mpidr",
854 "revidr",
855 "id_pfr0",
856 "id_pfr1",
857 "id_dfr0",
858 "id_afr0",
859 "id_mmfr0",
860 "id_mmfr1",
861 "id_mmfr2",
862 "id_mmfr3",
863 "id_isar0",
864 "id_isar1",
865 "id_isar2",
866 "id_isar3",
867 "id_isar4",
868 "id_isar5",
869 "ccsidr",
870 "clidr",
871 "aidr",
872 "csselr",
873 "csselr_ns",
874 "csselr_s",
875 "vpidr",
876 "vmpidr",
877 "sctlr",
878 "sctlr_ns",
879 "sctlr_s",
880 "actlr",
881 "actlr_ns",
882 "actlr_s",
883 "cpacr",
884 "scr",
885 "sder",
886 "nsacr",
887 "hsctlr",
888 "hactlr",
889 "hcr",
890 "hdcr",
891 "hcptr",
892 "hstr",
893 "hacr",
894 "ttbr0",
895 "ttbr0_ns",
896 "ttbr0_s",
897 "ttbr1",
898 "ttbr1_ns",
899 "ttbr1_s",
900 "ttbcr",
901 "ttbcr_ns",
902 "ttbcr_s",
903 "htcr",
904 "vtcr",
905 "dacr",
906 "dacr_ns",
907 "dacr_s",
908 "dfsr",
909 "dfsr_ns",
910 "dfsr_s",
911 "ifsr",
912 "ifsr_ns",
913 "ifsr_s",
914 "adfsr",
915 "adfsr_ns",
916 "adfsr_s",
917 "aifsr",
918 "aifsr_ns",
919 "aifsr_s",
920 "hadfsr",
921 "haifsr",
922 "hsr",
923 "dfar",
924 "dfar_ns",
925 "dfar_s",
926 "ifar",
927 "ifar_ns",
928 "ifar_s",
929 "hdfar",
930 "hifar",
931 "hpfar",
932 "icialluis",
933 "bpiallis",
934 "par",
935 "par_ns",
936 "par_s",
937 "iciallu",
938 "icimvau",
939 "cp15isb",
940 "bpiall",
941 "bpimva",
942 "dcimvac",
943 "dcisw",
944 "ats1cpr",
945 "ats1cpw",
946 "ats1cur",
947 "ats1cuw",
948 "ats12nsopr",
949 "ats12nsopw",
950 "ats12nsour",
951 "ats12nsouw",
952 "dccmvac",
953 "dccsw",
954 "cp15dsb",
955 "cp15dmb",
956 "dccmvau",
957 "dccimvac",
958 "dccisw",
959 "ats1hr",
960 "ats1hw",
961 "tlbiallis",
962 "tlbimvais",
963 "tlbiasidis",
964 "tlbimvaais",
965 "tlbimvalis",
966 "tlbimvaalis",
967 "itlbiall",
968 "itlbimva",
969 "itlbiasid",
970 "dtlbiall",
971 "dtlbimva",
972 "dtlbiasid",
973 "tlbiall",
974 "tlbimva",
975 "tlbiasid",
976 "tlbimvaa",
977 "tlbimval",
978 "tlbimvaal",
979 "tlbiipas2is",
980 "tlbiipas2lis",
981 "tlbiallhis",
982 "tlbimvahis",
983 "tlbiallnsnhis",
984 "tlbimvalhis",
985 "tlbiipas2",
986 "tlbiipas2l",
987 "tlbiallh",
988 "tlbimvah",
989 "tlbiallnsnh",
990 "tlbimvalh",
991 "pmcr",
992 "pmcntenset",
993 "pmcntenclr",
994 "pmovsr",
995 "pmswinc",
996 "pmselr",
997 "pmceid0",
998 "pmceid1",
999 "pmccntr",
1000 "pmxevtyper",
1001 "pmccfiltr",
1002 "pmxevcntr",
1003 "pmuserenr",
1004 "pmintenset",
1005 "pmintenclr",
1006 "pmovsset",
1007 "l2ctlr",
1008 "l2ectlr",
1009 "prrr",
1010 "prrr_ns",
1011 "prrr_s",
1012 "mair0",
1013 "mair0_ns",
1014 "mair0_s",
1015 "nmrr",
1016 "nmrr_ns",
1017 "nmrr_s",
1018 "mair1",
1019 "mair1_ns",
1020 "mair1_s",
1021 "amair0",
1022 "amair0_ns",
1023 "amair0_s",
1024 "amair1",
1025 "amair1_ns",
1026 "amair1_s",
1027 "hmair0",
1028 "hmair1",
1029 "hamair0",
1030 "hamair1",
1031 "vbar",
1032 "vbar_ns",
1033 "vbar_s",
1034 "mvbar",
1035 "rmr",
1036 "isr",
1037 "hvbar",
1038 "fcseidr",
1039 "contextidr",
1040 "contextidr_ns",
1041 "contextidr_s",
1042 "tpidrurw",
1043 "tpidrurw_ns",
1044 "tpidrurw_s",
1045 "tpidruro",
1046 "tpidruro_ns",
1047 "tpidruro_s",
1048 "tpidrprw",
1049 "tpidrprw_ns",
1050 "tpidrprw_s",
1051 "htpidr",
1052 "cntfrq",
1053 "cntkctl",
1054 "cntp_tval",
1055 "cntp_tval_ns",
1056 "cntp_tval_s",
1057 "cntp_ctl",
1058 "cntp_ctl_ns",
1059 "cntp_ctl_s",
1060 "cntv_tval",
1061 "cntv_ctl",
1062 "cnthctl",
1063 "cnthp_tval",
1064 "cnthp_ctl",
1065 "il1data0",
1066 "il1data1",
1067 "il1data2",
1068 "il1data3",
1069 "dl1data0",
1070 "dl1data1",
1071 "dl1data2",
1072 "dl1data3",
1073 "dl1data4",
1074 "ramindex",
1075 "l2actlr",
1076 "cbar",
1077 "httbr",
1078 "vttbr",
1079 "cntpct",
1080 "cntvct",
1081 "cntp_cval",
1082 "cntp_cval_ns",
1083 "cntp_cval_s",
1084 "cntv_cval",
1085 "cntvoff",
1086 "cnthp_cval",
1087 "cpumerrsr",
1088 "l2merrsr",
1089
1090 // AArch64 registers (Op0=2)
1091 "mdccint_el1",
1092 "osdtrrx_el1",
1093 "mdscr_el1",
1094 "osdtrtx_el1",
1095 "oseccr_el1",
1096 "dbgbvr0_el1",
1097 "dbgbvr1_el1",
1098 "dbgbvr2_el1",
1099 "dbgbvr3_el1",
1100 "dbgbvr4_el1",
1101 "dbgbvr5_el1",
1102 "dbgbcr0_el1",
1103 "dbgbcr1_el1",
1104 "dbgbcr2_el1",
1105 "dbgbcr3_el1",
1106 "dbgbcr4_el1",
1107 "dbgbcr5_el1",
1108 "dbgwvr0_el1",
1109 "dbgwvr1_el1",
1110 "dbgwvr2_el1",
1111 "dbgwvr3_el1",
1112 "dbgwcr0_el1",
1113 "dbgwcr1_el1",
1114 "dbgwcr2_el1",
1115 "dbgwcr3_el1",
1116 "mdccsr_el0",
1117 "mddtr_el0",
1118 "mddtrtx_el0",
1119 "mddtrrx_el0",
1120 "dbgvcr32_el2",
1121 "mdrar_el1",
1122 "oslar_el1",
1123 "oslsr_el1",
1124 "osdlr_el1",
1125 "dbgprcr_el1",
1126 "dbgclaimset_el1",
1127 "dbgclaimclr_el1",
1128 "dbgauthstatus_el1",
1129 "teecr32_el1",
1130 "teehbr32_el1",
1131
1132 // AArch64 registers (Op0=1,3)
1133 "midr_el1",
1134 "mpidr_el1",
1135 "revidr_el1",
1136 "id_pfr0_el1",
1137 "id_pfr1_el1",
1138 "id_dfr0_el1",
1139 "id_afr0_el1",
1140 "id_mmfr0_el1",
1141 "id_mmfr1_el1",
1142 "id_mmfr2_el1",
1143 "id_mmfr3_el1",
1144 "id_isar0_el1",
1145 "id_isar1_el1",
1146 "id_isar2_el1",
1147 "id_isar3_el1",
1148 "id_isar4_el1",
1149 "id_isar5_el1",
1150 "mvfr0_el1",
1151 "mvfr1_el1",
1152 "mvfr2_el1",
1153 "id_aa64pfr0_el1",
1154 "id_aa64pfr1_el1",
1155 "id_aa64dfr0_el1",
1156 "id_aa64dfr1_el1",
1157 "id_aa64afr0_el1",
1158 "id_aa64afr1_el1",
1159 "id_aa64isar0_el1",
1160 "id_aa64isar1_el1",
1161 "id_aa64mmfr0_el1",
1162 "id_aa64mmfr1_el1",
1163 "ccsidr_el1",
1164 "clidr_el1",
1165 "aidr_el1",
1166 "csselr_el1",
1167 "ctr_el0",
1168 "dczid_el0",
1169 "vpidr_el2",
1170 "vmpidr_el2",
1171 "sctlr_el1",
1172 "actlr_el1",
1173 "cpacr_el1",
1174 "sctlr_el2",
1175 "actlr_el2",
1176 "hcr_el2",
1177 "mdcr_el2",
1178 "cptr_el2",
1179 "hstr_el2",
1180 "hacr_el2",
1181 "sctlr_el3",
1182 "actlr_el3",
1183 "scr_el3",
1184 "sder32_el3",
1185 "cptr_el3",
1186 "mdcr_el3",
1187 "ttbr0_el1",
1188 "ttbr1_el1",
1189 "tcr_el1",
1190 "ttbr0_el2",
1191 "tcr_el2",
1192 "vttbr_el2",
1193 "vtcr_el2",
1194 "ttbr0_el3",
1195 "tcr_el3",
1196 "dacr32_el2",
1197 "spsr_el1",
1198 "elr_el1",
1199 "sp_el0",
1200 "spsel",
1201 "currentel",
1202 "nzcv",
1203 "daif",
1204 "fpcr",
1205 "fpsr",
1206 "dspsr_el0",
1207 "dlr_el0",
1208 "spsr_el2",
1209 "elr_el2",
1210 "sp_el1",
1211 "spsr_irq_aa64",
1212 "spsr_abt_aa64",
1213 "spsr_und_aa64",
1214 "spsr_fiq_aa64",
1215 "spsr_el3",
1216 "elr_el3",
1217 "sp_el2",
1218 "afsr0_el1",
1219 "afsr1_el1",
1220 "esr_el1",
1221 "ifsr32_el2",
1222 "afsr0_el2",
1223 "afsr1_el2",
1224 "esr_el2",
1225 "fpexc32_el2",
1226 "afsr0_el3",
1227 "afsr1_el3",
1228 "esr_el3",
1229 "far_el1",
1230 "far_el2",
1231 "hpfar_el2",
1232 "far_el3",
1233 "ic_ialluis",
1234 "par_el1",
1235 "ic_iallu",
1236 "dc_ivac_xt",
1237 "dc_isw_xt",
1238 "at_s1e1r_xt",
1239 "at_s1e1w_xt",
1240 "at_s1e0r_xt",
1241 "at_s1e0w_xt",
1242 "dc_csw_xt",
1243 "dc_cisw_xt",
1244 "dc_zva_xt",
1245 "ic_ivau_xt",
1246 "dc_cvac_xt",
1247 "dc_cvau_xt",
1248 "dc_civac_xt",
1249 "at_s1e2r_xt",
1250 "at_s1e2w_xt",
1251 "at_s12e1r_xt",
1252 "at_s12e1w_xt",
1253 "at_s12e0r_xt",
1254 "at_s12e0w_xt",
1255 "at_s1e3r_xt",
1256 "at_s1e3w_xt",
1257 "tlbi_vmalle1is",
1258 "tlbi_vae1is_xt",
1259 "tlbi_aside1is_xt",
1260 "tlbi_vaae1is_xt",
1261 "tlbi_vale1is_xt",
1262 "tlbi_vaale1is_xt",
1263 "tlbi_vmalle1",
1264 "tlbi_vae1_xt",
1265 "tlbi_aside1_xt",
1266 "tlbi_vaae1_xt",
1267 "tlbi_vale1_xt",
1268 "tlbi_vaale1_xt",
1269 "tlbi_ipas2e1is_xt",
1270 "tlbi_ipas2le1is_xt",
1271 "tlbi_alle2is",
1272 "tlbi_vae2is_xt",
1273 "tlbi_alle1is",
1274 "tlbi_vale2is_xt",
1275 "tlbi_vmalls12e1is",
1276 "tlbi_ipas2e1_xt",
1277 "tlbi_ipas2le1_xt",
1278 "tlbi_alle2",
1279 "tlbi_vae2_xt",
1280 "tlbi_alle1",
1281 "tlbi_vale2_xt",
1282 "tlbi_vmalls12e1",
1283 "tlbi_alle3is",
1284 "tlbi_vae3is_xt",
1285 "tlbi_vale3is_xt",
1286 "tlbi_alle3",
1287 "tlbi_vae3_xt",
1288 "tlbi_vale3_xt",
1289 "pmintenset_el1",
1290 "pmintenclr_el1",
1291 "pmcr_el0",
1292 "pmcntenset_el0",
1293 "pmcntenclr_el0",
1294 "pmovsclr_el0",
1295 "pmswinc_el0",
1296 "pmselr_el0",
1297 "pmceid0_el0",
1298 "pmceid1_el0",
1299 "pmccntr_el0",
1300 "pmxevtyper_el0",
1301 "pmccfiltr_el0",
1302 "pmxevcntr_el0",
1303 "pmuserenr_el0",
1304 "pmovsset_el0",
1305 "mair_el1",
1306 "amair_el1",
1307 "mair_el2",
1308 "amair_el2",
1309 "mair_el3",
1310 "amair_el3",
1311 "l2ctlr_el1",
1312 "l2ectlr_el1",
1313 "vbar_el1",
1314 "rvbar_el1",
1315 "isr_el1",
1316 "vbar_el2",
1317 "rvbar_el2",
1318 "vbar_el3",
1319 "rvbar_el3",
1320 "rmr_el3",
1321 "contextidr_el1",
1322 "tpidr_el1",
1323 "tpidr_el0",
1324 "tpidrro_el0",
1325 "tpidr_el2",
1326 "tpidr_el3",
1327 "cntkctl_el1",
1328 "cntfrq_el0",
1329 "cntpct_el0",
1330 "cntvct_el0",
1331 "cntp_tval_el0",
1332 "cntp_ctl_el0",
1333 "cntp_cval_el0",
1334 "cntv_tval_el0",
1335 "cntv_ctl_el0",
1336 "cntv_cval_el0",
1337 "pmevcntr0_el0",
1338 "pmevcntr1_el0",
1339 "pmevcntr2_el0",
1340 "pmevcntr3_el0",
1341 "pmevcntr4_el0",
1342 "pmevcntr5_el0",
1343 "pmevtyper0_el0",
1344 "pmevtyper1_el0",
1345 "pmevtyper2_el0",
1346 "pmevtyper3_el0",
1347 "pmevtyper4_el0",
1348 "pmevtyper5_el0",
1349 "cntvoff_el2",
1350 "cnthctl_el2",
1351 "cnthp_tval_el2",
1352 "cnthp_ctl_el2",
1353 "cnthp_cval_el2",
1354 "cntps_tval_el1",
1355 "cntps_ctl_el1",
1356 "cntps_cval_el1",
1357 "il1data0_el1",
1358 "il1data1_el1",
1359 "il1data2_el1",
1360 "il1data3_el1",
1361 "dl1data0_el1",
1362 "dl1data1_el1",
1363 "dl1data2_el1",
1364 "dl1data3_el1",
1365 "dl1data4_el1",
1366 "l2actlr_el1",
1367 "cpuactlr_el1",
1368 "cpuectlr_el1",
1369 "cpumerrsr_el1",
1370 "l2merrsr_el1",
1371 "cbar_el1",
1372 "contextidr_el2",
1373
1374 "ttbr1_el2",
1375 "freeslot1",
1376 "freeslot2",
1377 "freeslot3",
1378 "freeslot4",
1379 "freeslot5",
1380
1381 "num_phys_regs",
1382
1383 // Dummy registers
1384 "nop",
1385 "raz",
1386 "cp14_unimpl",
1387 "cp15_unimpl",
1388 "unknown",
1389 "impl_defined"
1390 };
1391
1392 static_assert(sizeof(miscRegName) / sizeof(*miscRegName) == NUM_MISCREGS,
1393 "The miscRegName array and NUM_MISCREGS are inconsistent.");
1394
1395 BitUnion32(CPSR)
1396 Bitfield<31, 30> nz;
1397 Bitfield<29> c;
1398 Bitfield<28> v;
1399 Bitfield<27> q;
1400 Bitfield<26, 25> it1;
1401 Bitfield<24> j;
1402 Bitfield<23, 22> res0_23_22;
1403 Bitfield<21> ss; // AArch64
1404 Bitfield<20> il; // AArch64
1405 Bitfield<19, 16> ge;
1406 Bitfield<15, 10> it2;
1407 Bitfield<9> d; // AArch64
1408 Bitfield<9> e;
1409 Bitfield<8> a;
1410 Bitfield<7> i;
1411 Bitfield<6> f;
1412 Bitfield<8, 6> aif;
1413 Bitfield<9, 6> daif; // AArch64
1414 Bitfield<5> t;
1415 Bitfield<4> width; // AArch64
1416 Bitfield<3, 2> el; // AArch64
1417 Bitfield<4, 0> mode;
1418 Bitfield<0> sp; // AArch64
1419 EndBitUnion(CPSR)
1420
1421 // This mask selects bits of the CPSR that actually go in the CondCodes
1422 // integer register to allow renaming.
1423 static const uint32_t CondCodesMask = 0xF00F0000;
1424 static const uint32_t CpsrMaskQ = 0x08000000;
1425
1426 // APSR (Application Program Status Register Mask). It is the user level
1427 // alias for the CPSR. The APSR is a subset of the CPSR. Although
1428 // bits[15:0] are UNKNOWN on reads, it is permitted that, on a read of
1429 // APSR:
1430 // Bit[9] returns the value of CPSR.E.
1431 // Bits[8:6] return the value of CPSR.{A,I, F}, the mask bits.
1432 static const uint32_t ApsrMask = CpsrMaskQ | CondCodesMask | 0x000001D0;
1433
1434 // CPSR (Current Program Status Register Mask).
1435 static const uint32_t CpsrMask = ApsrMask | 0x00F003DF;
1436
1437 BitUnion32(HDCR)
1438 Bitfield<11> tdra;
1439 Bitfield<10> tdosa;
1440 Bitfield<9> tda;
1441 Bitfield<8> tde;
1442 Bitfield<7> hpme;
1443 Bitfield<6> tpm;
1444 Bitfield<5> tpmcr;
1445 Bitfield<4, 0> hpmn;
1446 EndBitUnion(HDCR)
1447
1448 BitUnion32(HCPTR)
1449 Bitfield<31> tcpac;
1450 Bitfield<20> tta;
1451 Bitfield<15> tase;
1452 Bitfield<13> tcp13;
1453 Bitfield<12> tcp12;
1454 Bitfield<11> tcp11;
1455 Bitfield<10> tcp10;
1456 Bitfield<10> tfp; // AArch64
1457 Bitfield<9> tcp9;
1458 Bitfield<8> tcp8;
1459 Bitfield<7> tcp7;
1460 Bitfield<6> tcp6;
1461 Bitfield<5> tcp5;
1462 Bitfield<4> tcp4;
1463 Bitfield<3> tcp3;
1464 Bitfield<2> tcp2;
1465 Bitfield<1> tcp1;
1466 Bitfield<0> tcp0;
1467 EndBitUnion(HCPTR)
1468
1469 BitUnion32(HSTR)
1470 Bitfield<17> tjdbx;
1471 Bitfield<16> ttee;
1472 Bitfield<15> t15;
1473 Bitfield<13> t13;
1474 Bitfield<12> t12;
1475 Bitfield<11> t11;
1476 Bitfield<10> t10;
1477 Bitfield<9> t9;
1478 Bitfield<8> t8;
1479 Bitfield<7> t7;
1480 Bitfield<6> t6;
1481 Bitfield<5> t5;
1482 Bitfield<4> t4;
1483 Bitfield<3> t3;
1484 Bitfield<2> t2;
1485 Bitfield<1> t1;
1486 Bitfield<0> t0;
1487 EndBitUnion(HSTR)
1488
1489 BitUnion64(HCR)
1490 Bitfield<34> e2h; // AArch64
1491 Bitfield<33> id; // AArch64
1492 Bitfield<32> cd; // AArch64
1493 Bitfield<31> rw; // AArch64
1494 Bitfield<30> trvm; // AArch64
1495 Bitfield<29> hcd; // AArch64
1496 Bitfield<28> tdz; // AArch64
1497
1498 Bitfield<27> tge;
1499 Bitfield<26> tvm;
1500 Bitfield<25> ttlb;
1501 Bitfield<24> tpu;
1502 Bitfield<23> tpc;
1503 Bitfield<22> tsw;
1504 Bitfield<21> tac;
1505 Bitfield<21> tacr; // AArch64
1506 Bitfield<20> tidcp;
1507 Bitfield<19> tsc;
1508 Bitfield<18> tid3;
1509 Bitfield<17> tid2;
1510 Bitfield<16> tid1;
1511 Bitfield<15> tid0;
1512 Bitfield<14> twe;
1513 Bitfield<13> twi;
1514 Bitfield<12> dc;
1515 Bitfield<11, 10> bsu;
1516 Bitfield<9> fb;
1517 Bitfield<8> va;
1518 Bitfield<8> vse; // AArch64
1519 Bitfield<7> vi;
1520 Bitfield<6> vf;
1521 Bitfield<5> amo;
1522 Bitfield<4> imo;
1523 Bitfield<3> fmo;
1524 Bitfield<2> ptw;
1525 Bitfield<1> swio;
1526 Bitfield<0> vm;
1527 EndBitUnion(HCR)
1528
1529 BitUnion32(NSACR)
1530 Bitfield<20> nstrcdis;
1531 Bitfield<19> rfr;
1532 Bitfield<15> nsasedis;
1533 Bitfield<14> nsd32dis;
1534 Bitfield<13> cp13;
1535 Bitfield<12> cp12;
1536 Bitfield<11> cp11;
1537 Bitfield<10> cp10;
1538 Bitfield<9> cp9;
1539 Bitfield<8> cp8;
1540 Bitfield<7> cp7;
1541 Bitfield<6> cp6;
1542 Bitfield<5> cp5;
1543 Bitfield<4> cp4;
1544 Bitfield<3> cp3;
1545 Bitfield<2> cp2;
1546 Bitfield<1> cp1;
1547 Bitfield<0> cp0;
1548 EndBitUnion(NSACR)
1549
1550 BitUnion32(SCR)
1551 Bitfield<13> twe;
1552 Bitfield<12> twi;
1553 Bitfield<11> st; // AArch64
1554 Bitfield<10> rw; // AArch64
1555 Bitfield<9> sif;
1556 Bitfield<8> hce;
1557 Bitfield<7> scd;
1558 Bitfield<7> smd; // AArch64
1559 Bitfield<6> nEt;
1560 Bitfield<5> aw;
1561 Bitfield<4> fw;
1562 Bitfield<3> ea;
1563 Bitfield<2> fiq;
1564 Bitfield<1> irq;
1565 Bitfield<0> ns;
1566 EndBitUnion(SCR)
1567
1568 BitUnion32(SCTLR)
1569 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
1570 Bitfield<29> afe; // Access flag enable (AArch32 only)
1571 Bitfield<28> tre; // TEX remap enable (AArch32 only)
1572 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
1573 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
1574 // DC CVAC and IC IVAU instructions
1575 // (AArch64 SCTLR_EL1 only)
1576 Bitfield<25> ee; // Exception Endianness
1577 Bitfield<24> ve; // Interrupt Vectors Enable (ARMv7 only)
1578 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
1579 // (AArch64 SCTLR_EL1 only)
1580 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
1581 Bitfield<22> u; // Alignment (dropped in ARMv7)
1582 Bitfield<21> fi; // Fast interrupts configuration enable
1583 // (ARMv7 only)
1584 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
1585 // (AArch32 only)
1586 Bitfield<19> dz; // Divide by Zero fault enable
1587 // (dropped in ARMv7)
1588 Bitfield<19> wxn; // Write permission implies XN
1589 Bitfield<18> ntwe; // Not trap WFE
1590 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1591 Bitfield<18> rao2; // Read as one
1592 Bitfield<16> ntwi; // Not trap WFI
1593 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1594 Bitfield<16> rao3; // Read as one
1595 Bitfield<15> uct; // Enable EL0 access to CTR_EL0
1596 // (AArch64 SCTLR_EL1 only)
1597 Bitfield<14> rr; // Round Robin select (ARMv7 only)
1598 Bitfield<14> dze; // Enable EL0 access to DC ZVA
1599 // (AArch64 SCTLR_EL1 only)
1600 Bitfield<13> v; // Vectors bit (AArch32 only)
1601 Bitfield<12> i; // Instruction cache enable
1602 Bitfield<11> z; // Branch prediction enable (ARMv7 only)
1603 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
1604 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
1605 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
1606 Bitfield<8> sed; // SETEND disable
1607 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1608 Bitfield<7> b; // Endianness support (dropped in ARMv7)
1609 Bitfield<7> itd; // IT disable
1610 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1611 Bitfield<6, 3> rao4; // Read as one
1612 Bitfield<6> thee; // ThumbEE enable
1613 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
1614 Bitfield<5> cp15ben; // CP15 barrier enable
1615 // (AArch32 and AArch64 SCTLR_EL1 only)
1616 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
1617 // (AArch64 SCTLR_EL1 only)
1618 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
1619 Bitfield<2> c; // Cache enable
1620 Bitfield<1> a; // Alignment check enable
1621 Bitfield<0> m; // MMU enable
1622 EndBitUnion(SCTLR)
1623
1624 BitUnion32(CPACR)
1625 Bitfield<1, 0> cp0;
1626 Bitfield<3, 2> cp1;
1627 Bitfield<5, 4> cp2;
1628 Bitfield<7, 6> cp3;
1629 Bitfield<9, 8> cp4;
1630 Bitfield<11, 10> cp5;
1631 Bitfield<13, 12> cp6;
1632 Bitfield<15, 14> cp7;
1633 Bitfield<17, 16> cp8;
1634 Bitfield<19, 18> cp9;
1635 Bitfield<21, 20> cp10;
1636 Bitfield<21, 20> fpen; // AArch64
1637 Bitfield<23, 22> cp11;
1638 Bitfield<25, 24> cp12;
1639 Bitfield<27, 26> cp13;
1640 Bitfield<29, 28> rsvd;
1641 Bitfield<28> tta; // AArch64
1642 Bitfield<30> d32dis;
1643 Bitfield<31> asedis;
1644 EndBitUnion(CPACR)
1645
1646 BitUnion32(FSR)
1647 Bitfield<3, 0> fsLow;
1648 Bitfield<5, 0> status; // LPAE
1649 Bitfield<7, 4> domain;
1650 Bitfield<9> lpae;
1651 Bitfield<10> fsHigh;
1652 Bitfield<11> wnr;
1653 Bitfield<12> ext;
1654 Bitfield<13> cm; // LPAE
1655 EndBitUnion(FSR)
1656
1657 BitUnion32(FPSCR)
1658 Bitfield<0> ioc;
1659 Bitfield<1> dzc;
1660 Bitfield<2> ofc;
1661 Bitfield<3> ufc;
1662 Bitfield<4> ixc;
1663 Bitfield<7> idc;
1664 Bitfield<8> ioe;
1665 Bitfield<9> dze;
1666 Bitfield<10> ofe;
1667 Bitfield<11> ufe;
1668 Bitfield<12> ixe;
1669 Bitfield<15> ide;
1670 Bitfield<18, 16> len;
1671 Bitfield<21, 20> stride;
1672 Bitfield<23, 22> rMode;
1673 Bitfield<24> fz;
1674 Bitfield<25> dn;
1675 Bitfield<26> ahp;
1676 Bitfield<27> qc;
1677 Bitfield<28> v;
1678 Bitfield<29> c;
1679 Bitfield<30> z;
1680 Bitfield<31> n;
1681 EndBitUnion(FPSCR)
1682
1683 // This mask selects bits of the FPSCR that actually go in the FpCondCodes
1684 // integer register to allow renaming.
1685 static const uint32_t FpCondCodesMask = 0xF0000000;
1686 // This mask selects the cumulative FP exception flags of the FPSCR.
1687 static const uint32_t FpscrExcMask = 0x0000009F;
1688 // This mask selects the cumulative saturation flag of the FPSCR.
1689 static const uint32_t FpscrQcMask = 0x08000000;
1690
1691 BitUnion32(FPEXC)
1692 Bitfield<31> ex;
1693 Bitfield<30> en;
1694 Bitfield<29, 0> subArchDefined;
1695 EndBitUnion(FPEXC)
1696
1697 BitUnion32(MVFR0)
1698 Bitfield<3, 0> advSimdRegisters;
1699 Bitfield<7, 4> singlePrecision;
1700 Bitfield<11, 8> doublePrecision;
1701 Bitfield<15, 12> vfpExceptionTrapping;
1702 Bitfield<19, 16> divide;
1703 Bitfield<23, 20> squareRoot;
1704 Bitfield<27, 24> shortVectors;
1705 Bitfield<31, 28> roundingModes;
1706 EndBitUnion(MVFR0)
1707
1708 BitUnion32(MVFR1)
1709 Bitfield<3, 0> flushToZero;
1710 Bitfield<7, 4> defaultNaN;
1711 Bitfield<11, 8> advSimdLoadStore;
1712 Bitfield<15, 12> advSimdInteger;
1713 Bitfield<19, 16> advSimdSinglePrecision;
1714 Bitfield<23, 20> advSimdHalfPrecision;
1715 Bitfield<27, 24> vfpHalfPrecision;
1716 Bitfield<31, 28> raz;
1717 EndBitUnion(MVFR1)
1718
1719 BitUnion64(TTBCR)
1720 // Short-descriptor translation table format
1721 Bitfield<2, 0> n;
1722 Bitfield<4> pd0;
1723 Bitfield<5> pd1;
1724 // Long-descriptor translation table format
1725 Bitfield<2, 0> t0sz;
1726 Bitfield<7> epd0;
1727 Bitfield<9, 8> irgn0;
1728 Bitfield<11, 10> orgn0;
1729 Bitfield<13, 12> sh0;
1730 Bitfield<14> tg0;
1731 Bitfield<18, 16> t1sz;
1732 Bitfield<22> a1;
1733 Bitfield<23> epd1;
1734 Bitfield<25, 24> irgn1;
1735 Bitfield<27, 26> orgn1;
1736 Bitfield<29, 28> sh1;
1737 Bitfield<30> tg1;
1738 Bitfield<34, 32> ips;
1739 Bitfield<36> as;
1740 Bitfield<37> tbi0;
1741 Bitfield<38> tbi1;
1742 // Common
1743 Bitfield<31> eae;
1744 // TCR_EL2/3 (AArch64)
1745 Bitfield<18, 16> ps;
1746 Bitfield<20> tbi;
1747 EndBitUnion(TTBCR)
1748
1749 // Fields of TCR_EL{1,2,3} (mostly overlapping)
1750 // TCR_EL1 is natively 64 bits, the others are 32 bits
1751 BitUnion64(TCR)
1752 Bitfield<5, 0> t0sz;
1753 Bitfield<7> epd0; // EL1
1754 Bitfield<9, 8> irgn0;
1755 Bitfield<11, 10> orgn0;
1756 Bitfield<13, 12> sh0;
1757 Bitfield<15, 14> tg0;
1758 Bitfield<18, 16> ps;
1759 Bitfield<20> tbi; // EL2/EL3
1760 Bitfield<21, 16> t1sz; // EL1
1761 Bitfield<22> a1; // EL1
1762 Bitfield<23> epd1; // EL1
1763 Bitfield<25, 24> irgn1; // EL1
1764 Bitfield<27, 26> orgn1; // EL1
1765 Bitfield<29, 28> sh1; // EL1
1766 Bitfield<31, 30> tg1; // EL1
1767 Bitfield<34, 32> ips; // EL1
1768 Bitfield<36> as; // EL1
1769 Bitfield<37> tbi0; // EL1
1770 Bitfield<38> tbi1; // EL1
1771 EndBitUnion(TCR)
1772
1773 BitUnion32(HTCR)
1774 Bitfield<2, 0> t0sz;
1775 Bitfield<9, 8> irgn0;
1776 Bitfield<11, 10> orgn0;
1777 Bitfield<13, 12> sh0;
1778 EndBitUnion(HTCR)
1779
1780 BitUnion32(VTCR_t)
1781 Bitfield<3, 0> t0sz;
1782 Bitfield<4> s;
1783 Bitfield<5, 0> t0sz64;
1784 Bitfield<7, 6> sl0;
1785 Bitfield<9, 8> irgn0;
1786 Bitfield<11, 10> orgn0;
1787 Bitfield<13, 12> sh0;
1788 Bitfield<15, 14> tg0;
1789 EndBitUnion(VTCR_t)
1790
1791 BitUnion32(PRRR)
1792 Bitfield<1,0> tr0;
1793 Bitfield<3,2> tr1;
1794 Bitfield<5,4> tr2;
1795 Bitfield<7,6> tr3;
1796 Bitfield<9,8> tr4;
1797 Bitfield<11,10> tr5;
1798 Bitfield<13,12> tr6;
1799 Bitfield<15,14> tr7;
1800 Bitfield<16> ds0;
1801 Bitfield<17> ds1;
1802 Bitfield<18> ns0;
1803 Bitfield<19> ns1;
1804 Bitfield<24> nos0;
1805 Bitfield<25> nos1;
1806 Bitfield<26> nos2;
1807 Bitfield<27> nos3;
1808 Bitfield<28> nos4;
1809 Bitfield<29> nos5;
1810 Bitfield<30> nos6;
1811 Bitfield<31> nos7;
1812 EndBitUnion(PRRR)
1813
1814 BitUnion32(NMRR)
1815 Bitfield<1,0> ir0;
1816 Bitfield<3,2> ir1;
1817 Bitfield<5,4> ir2;
1818 Bitfield<7,6> ir3;
1819 Bitfield<9,8> ir4;
1820 Bitfield<11,10> ir5;
1821 Bitfield<13,12> ir6;
1822 Bitfield<15,14> ir7;
1823 Bitfield<17,16> or0;
1824 Bitfield<19,18> or1;
1825 Bitfield<21,20> or2;
1826 Bitfield<23,22> or3;
1827 Bitfield<25,24> or4;
1828 Bitfield<27,26> or5;
1829 Bitfield<29,28> or6;
1830 Bitfield<31,30> or7;
1831 EndBitUnion(NMRR)
1832
1833 BitUnion32(CONTEXTIDR)
1834 Bitfield<7,0> asid;
1835 Bitfield<31,8> procid;
1836 EndBitUnion(CONTEXTIDR)
1837
1838 BitUnion32(L2CTLR)
1839 Bitfield<2,0> sataRAMLatency;
1840 Bitfield<4,3> reserved_4_3;
1841 Bitfield<5> dataRAMSetup;
1842 Bitfield<8,6> tagRAMLatency;
1843 Bitfield<9> tagRAMSetup;
1844 Bitfield<11,10> dataRAMSlice;
1845 Bitfield<12> tagRAMSlice;
1846 Bitfield<20,13> reserved_20_13;
1847 Bitfield<21> eccandParityEnable;
1848 Bitfield<22> reserved_22;
1849 Bitfield<23> interptCtrlPresent;
1850 Bitfield<25,24> numCPUs;
1851 Bitfield<30,26> reserved_30_26;
1852 Bitfield<31> l2rstDISABLE_monitor;
1853 EndBitUnion(L2CTLR)
1854
1855 BitUnion32(CTR)
1856 Bitfield<3,0> iCacheLineSize;
1857 Bitfield<13,4> raz_13_4;
1858 Bitfield<15,14> l1IndexPolicy;
1859 Bitfield<19,16> dCacheLineSize;
1860 Bitfield<23,20> erg;
1861 Bitfield<27,24> cwg;
1862 Bitfield<28> raz_28;
1863 Bitfield<31,29> format;
1864 EndBitUnion(CTR)
1865
1866 BitUnion32(PMSELR)
1867 Bitfield<4, 0> sel;
1868 EndBitUnion(PMSELR)
1869
1870 BitUnion64(PAR)
1871 // 64-bit format
1872 Bitfield<63, 56> attr;
1873 Bitfield<39, 12> pa;
1874 Bitfield<11> lpae;
1875 Bitfield<9> ns;
1876 Bitfield<8, 7> sh;
1877 Bitfield<0> f;
1878 EndBitUnion(PAR)
1879
1880 BitUnion32(ESR)
1881 Bitfield<31, 26> ec;
1882 Bitfield<25> il;
1883 Bitfield<15, 0> imm16;
1884 EndBitUnion(ESR)
1885
1886 BitUnion32(CPTR)
1887 Bitfield<31> tcpac;
1888 Bitfield<20> tta;
1889 Bitfield<13, 12> res1_13_12_el2;
1890 Bitfield<10> tfp;
1891 Bitfield<9, 0> res1_9_0_el2;
1892 EndBitUnion(CPTR)
1893
1894
1895 /**
1896 * Check for permission to read coprocessor registers.
1897 *
1898 * Checks whether an instruction at the current program mode has
1899 * permissions to read the coprocessor registers. This function
1900 * returns whether the check is undefined and if not whether the
1901 * read access is permitted.
1902 *
1903 * @param the misc reg indicating the coprocessor
1904 * @param the SCR
1905 * @param the CPSR
1906 * @return a tuple of booleans: can_read, undefined
1907 */
1908 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr,
1909 CPSR cpsr);
1910
1911 /**
1912 * Check for permission to write coprocessor registers.
1913 *
1914 * Checks whether an instruction at the current program mode has
1915 * permissions to write the coprocessor registers. This function
1916 * returns whether the check is undefined and if not whether the
1917 * write access is permitted.
1918 *
1919 * @param the misc reg indicating the coprocessor
1920 * @param the SCR
1921 * @param the CPSR
1922 * @return a tuple of booleans: can_write, undefined
1923 */
1924 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr,
1925 CPSR cpsr);
1926
1927 // Checks read access permissions to AArch64 system registers
1928 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1929 ThreadContext *tc);
1930
1931 // Checks write access permissions to AArch64 system registers
1932 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr,
1933 ThreadContext *tc);
1934
1935 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
1936 // for MCR/MRC instructions
1937 int
1938 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc);
1939
1940 // Flattens a misc reg index using the specified security state. This is
1941 // used for opperations (eg address translations) where the security
1942 // state of the register access may differ from the current state of the
1943 // processor
1944 int
1945 snsBankedIndex(MiscRegIndex reg, ThreadContext *tc, bool ns);
1946
1947 // Takes a misc reg index and returns the root reg if its one of a set of
1948 // banked registers
1949 void
1950 preUnflattenMiscReg();
1951
1952 int
1953 unflattenMiscReg(int reg);
1954
1955 }
1956
1957 #endif // __ARCH_ARM_MISCREGS_HH__