src/arch/arm/miscregs_types.hh

   1 /*
   2  * Copyright (c) 2010-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_MISCREGS_TYPES_HH__
  42 #define __ARCH_ARM_MISCREGS_TYPES_HH__
  43
  44 #include "base/bitunion.hh"
  45
  46 namespace ArmISA
  47 {
  48     BitUnion32(CPSR)
  49         Bitfield<31, 30> nz;
  50         Bitfield<29> c;
  51         Bitfield<28> v;
  52         Bitfield<27> q;
  53         Bitfield<26, 25> it1;
  54         Bitfield<24> j;
  55         Bitfield<22> pan;
  56         Bitfield<21> ss;        // AArch64
  57         Bitfield<20> il;        // AArch64
  58         Bitfield<19, 16> ge;
  59         Bitfield<15, 10> it2;
  60         Bitfield<9> d;          // AArch64
  61         Bitfield<9> e;
  62         Bitfield<8> a;
  63         Bitfield<7> i;
  64         Bitfield<6> f;
  65         Bitfield<8, 6> aif;
  66         Bitfield<9, 6> daif;    // AArch64
  67         Bitfield<5> t;
  68         Bitfield<4> width;      // AArch64
  69         Bitfield<3, 2> el;      // AArch64
  70         Bitfield<4, 0> mode;
  71         Bitfield<0> sp;         // AArch64
  72     EndBitUnion(CPSR)
  73
  74     BitUnion64(AA64DFR0)
  75         Bitfield<43, 40> tracefilt;
  76         Bitfield<39, 36> doublelock;
  77         Bitfield<35, 32> pmsver;
  78         Bitfield<31, 28> ctx_cmps;
  79         Bitfield<23, 20> wrps;
  80         Bitfield<15, 12> brps;
  81         Bitfield<11, 8> pmuver;
  82         Bitfield<7, 4> tracever;
  83         Bitfield<3, 0> debugver;
  84     EndBitUnion(AA64DFR0)
  85
  86     BitUnion64(AA64ISAR0)
  87         Bitfield<63, 60> rndr;
  88         Bitfield<59, 56> tlb;
  89         Bitfield<55, 52> ts;
  90         Bitfield<51, 48> fhm;
  91         Bitfield<47, 44> dp;
  92         Bitfield<43, 40> sm4;
  93         Bitfield<39, 36> sm3;
  94         Bitfield<35, 32> sha3;
  95         Bitfield<31, 28> rdm;
  96         Bitfield<23, 20> atomic;
  97         Bitfield<19, 16> crc32;
  98         Bitfield<15, 12> sha2;
  99         Bitfield<11, 8> sha1;
 100         Bitfield<3, 0> aes;
 101     EndBitUnion(AA64ISAR0)
 102
 103     BitUnion64(AA64ISAR1)
 104         Bitfield<43, 40> specres;
 105         Bitfield<39, 36> sb;
 106         Bitfield<35, 32> frintts;
 107         Bitfield<31, 28> gpi;
 108         Bitfield<27, 24> gpa;
 109         Bitfield<23, 20> lrcpc;
 110         Bitfield<19, 16> fcma;
 111         Bitfield<15, 12> jscvt;
 112         Bitfield<11, 8> api;
 113         Bitfield<7, 4> apa;
 114         Bitfield<3, 0> dpb;
 115     EndBitUnion(AA64ISAR1)
 116
 117     BitUnion64(AA64MMFR0)
 118         Bitfield<47, 44> exs;
 119         Bitfield<43, 40> tgran4_2;
 120         Bitfield<39, 36> tgran64_2;
 121         Bitfield<35, 32> tgran16_2;
 122         Bitfield<31, 28> tgran4;
 123         Bitfield<27, 24> tgran64;
 124         Bitfield<23, 20> tgran16;
 125         Bitfield<19, 16> bigendEL0;
 126         Bitfield<15, 12> snsmem;
 127         Bitfield<11, 8> bigend;
 128         Bitfield<7, 4> asidbits;
 129         Bitfield<3, 0> parange;
 130     EndBitUnion(AA64MMFR0)
 131
 132     BitUnion64(AA64MMFR1)
 133         Bitfield<31, 28> xnx;
 134         Bitfield<27, 24> specsei;
 135         Bitfield<23, 20> pan;
 136         Bitfield<19, 16> lo;
 137         Bitfield<15, 12> hpds;
 138         Bitfield<11, 8> vh;
 139         Bitfield<7, 4> vmidbits;
 140         Bitfield<3, 0> hafdbs;
 141     EndBitUnion(AA64MMFR1)
 142
 143     BitUnion64(AA64MMFR2)
 144         Bitfield<63, 60> e0pd;
 145         Bitfield<59, 56> evt;
 146         Bitfield<55, 52> bbm;
 147         Bitfield<51, 48> ttl;
 148         Bitfield<43, 40> fwb;
 149         Bitfield<39, 36> ids;
 150         Bitfield<35, 32> at;
 151         Bitfield<31, 28> st;
 152         Bitfield<27, 24> nv;
 153         Bitfield<23, 20> ccidx;
 154         Bitfield<19, 16> varange;
 155         Bitfield<15, 12> iesb;
 156         Bitfield<11, 8> lsm;
 157         Bitfield<7, 4> uao;
 158         Bitfield<3, 0> cnp;
 159     EndBitUnion(AA64MMFR2)
 160
 161     BitUnion64(AA64PFR0)
 162         Bitfield<63, 60> csv3;
 163         Bitfield<59, 56> csv2;
 164         Bitfield<51, 48> dit;
 165         Bitfield<47, 44> amu;
 166         Bitfield<43, 40> mpam;
 167         Bitfield<39, 36> sel2;
 168         Bitfield<35, 32> sve;
 169         Bitfield<31, 28> ras;
 170         Bitfield<27, 24> gic;
 171         Bitfield<23, 20> advsimd;
 172         Bitfield<19, 16> fp;
 173         Bitfield<15, 12> el3;
 174         Bitfield<11, 8> el2;
 175         Bitfield<7, 4> el1;
 176         Bitfield<3, 0> el0;
 177     EndBitUnion(AA64PFR0)
 178
 179     BitUnion32(HDCR)
 180         Bitfield<11>   tdra;
 181         Bitfield<10>   tdosa;
 182         Bitfield<9>    tda;
 183         Bitfield<8>    tde;
 184         Bitfield<7>    hpme;
 185         Bitfield<6>    tpm;
 186         Bitfield<5>    tpmcr;
 187         Bitfield<4, 0> hpmn;
 188     EndBitUnion(HDCR)
 189
 190     BitUnion32(HCPTR)
 191         Bitfield<31> tcpac;
 192         Bitfield<20> tta;
 193         Bitfield<15> tase;
 194         Bitfield<13> tcp13;
 195         Bitfield<12> tcp12;
 196         Bitfield<11> tcp11;
 197         Bitfield<10> tcp10;
 198         Bitfield<10> tfp;  // AArch64
 199         Bitfield<9>  tcp9;
 200         Bitfield<8>  tcp8;
 201         Bitfield<8>  tz;  // SVE
 202         Bitfield<7>  tcp7;
 203         Bitfield<6>  tcp6;
 204         Bitfield<5>  tcp5;
 205         Bitfield<4>  tcp4;
 206         Bitfield<3>  tcp3;
 207         Bitfield<2>  tcp2;
 208         Bitfield<1>  tcp1;
 209         Bitfield<0>  tcp0;
 210     EndBitUnion(HCPTR)
 211
 212     BitUnion32(HSTR)
 213         Bitfield<17> tjdbx;
 214         Bitfield<16> ttee;
 215         Bitfield<15> t15;
 216         Bitfield<13> t13;
 217         Bitfield<12> t12;
 218         Bitfield<11> t11;
 219         Bitfield<10> t10;
 220         Bitfield<9>  t9;
 221         Bitfield<8>  t8;
 222         Bitfield<7>  t7;
 223         Bitfield<6>  t6;
 224         Bitfield<5>  t5;
 225         Bitfield<4>  t4;
 226         Bitfield<3>  t3;
 227         Bitfield<2>  t2;
 228         Bitfield<1>  t1;
 229         Bitfield<0>  t0;
 230     EndBitUnion(HSTR)
 231
 232     BitUnion64(HCR)
 233         Bitfield<47>     fien;
 234         Bitfield<46>     fwb;
 235         Bitfield<45>     nv2;
 236         Bitfield<44>     at;
 237         Bitfield<43>     nv1;
 238         Bitfield<42>     nv;
 239         Bitfield<41>     api;
 240         Bitfield<40>     apk;
 241         Bitfield<38>     miocnce;
 242         Bitfield<37>     tea;
 243         Bitfield<36>     terr;
 244         Bitfield<35>     tlor;
 245         Bitfield<34>     e2h;   // AArch64
 246         Bitfield<33>     id;
 247         Bitfield<32>     cd;
 248         Bitfield<31>     rw;    // AArch64
 249         Bitfield<30>     trvm;  // AArch64
 250         Bitfield<29>     hcd;   // AArch64
 251         Bitfield<28>     tdz;   // AArch64
 252         Bitfield<27>     tge;
 253         Bitfield<26>     tvm;
 254         Bitfield<25>     ttlb;
 255         Bitfield<24>     tpu;
 256         Bitfield<23>     tpc;
 257         Bitfield<22>     tsw;
 258         Bitfield<21>     tac;
 259         Bitfield<21>     tacr;  // AArch64
 260         Bitfield<20>     tidcp;
 261         Bitfield<19>     tsc;
 262         Bitfield<18>     tid3;
 263         Bitfield<17>     tid2;
 264         Bitfield<16>     tid1;
 265         Bitfield<15>     tid0;
 266         Bitfield<14>     twe;
 267         Bitfield<13>     twi;
 268         Bitfield<12>     dc;
 269         Bitfield<11, 10> bsu;
 270         Bitfield<9>      fb;
 271         Bitfield<8>      va;
 272         Bitfield<8>      vse;   // AArch64
 273         Bitfield<7>      vi;
 274         Bitfield<6>      vf;
 275         Bitfield<5>      amo;
 276         Bitfield<4>      imo;
 277         Bitfield<3>      fmo;
 278         Bitfield<2>      ptw;
 279         Bitfield<1>      swio;
 280         Bitfield<0>      vm;
 281     EndBitUnion(HCR)
 282
 283     BitUnion32(NSACR)
 284         Bitfield<20> nstrcdis;
 285         Bitfield<19> rfr;
 286         Bitfield<15> nsasedis;
 287         Bitfield<14> nsd32dis;
 288         Bitfield<13> cp13;
 289         Bitfield<12> cp12;
 290         Bitfield<11> cp11;
 291         Bitfield<10> cp10;
 292         Bitfield<9>  cp9;
 293         Bitfield<8>  cp8;
 294         Bitfield<7>  cp7;
 295         Bitfield<6>  cp6;
 296         Bitfield<5>  cp5;
 297         Bitfield<4>  cp4;
 298         Bitfield<3>  cp3;
 299         Bitfield<2>  cp2;
 300         Bitfield<1>  cp1;
 301         Bitfield<0>  cp0;
 302     EndBitUnion(NSACR)
 303
 304     BitUnion32(SCR)
 305         Bitfield<21> fien;
 306         Bitfield<20> nmea;
 307         Bitfield<19> ease;
 308         Bitfield<18> eel2; // AArch64 (Armv8.4-SecEL2)
 309         Bitfield<17> api;
 310         Bitfield<16> apk;
 311         Bitfield<15> teer;
 312         Bitfield<14> tlor;
 313         Bitfield<13> twe;
 314         Bitfield<12> twi;
 315         Bitfield<11> st;   // AArch64
 316         Bitfield<10> rw;   // AArch64
 317         Bitfield<9> sif;
 318         Bitfield<8> hce;
 319         Bitfield<7> scd;
 320         Bitfield<7> smd;   // AArch64
 321         Bitfield<6> nEt;
 322         Bitfield<5> aw;
 323         Bitfield<4> fw;
 324         Bitfield<3> ea;
 325         Bitfield<2> fiq;
 326         Bitfield<1> irq;
 327         Bitfield<0> ns;
 328     EndBitUnion(SCR)
 329
 330     BitUnion32(SCTLR)
 331         Bitfield<31>   enia;    // ARMv8.3 PAuth
 332         Bitfield<30>   enib;    // ARMv8.3 PAuth
 333         Bitfield<30>   te;      // Thumb Exception Enable (AArch32 only)
 334         Bitfield<29>   afe;     // Access flag enable (AArch32 only)
 335         Bitfield<28>   tre;     // TEX remap enable (AArch32 only)
 336         Bitfield<27>   nmfi;    // Non-maskable FIQ support (ARMv7 only)
 337         Bitfield<27>   enda;    // ARMv8.3 PAuth
 338         Bitfield<26>   uci;     // Enable EL0 access to DC CVAU, DC CIVAC,
 339                                 // DC CVAC and IC IVAU instructions
 340                                 // (AArch64 SCTLR_EL1 only)
 341         Bitfield<25>   ee;      // Exception Endianness
 342         Bitfield<24>   e0e;     // Endianness of explicit data accesses at EL0
 343                                 // (AArch64 SCTLR_EL1 only)
 344         Bitfield<23>   span;    // Set Priviledge Access Never on taking
 345                                 // an exception
 346         Bitfield<23>   xp;      // Extended page table enable (dropped in ARMv7)
 347         Bitfield<22>   u;       // Alignment (dropped in ARMv7)
 348         Bitfield<21>   fi;      // Fast interrupts configuration enable
 349                                 // (ARMv7 only)
 350         Bitfield<20>   uwxn;    // Unprivileged write permission implies EL1 XN
 351                                 // (AArch32 only)
 352         Bitfield<19>   dz;      // Divide by Zero fault enable
 353                                 // (dropped in ARMv7)
 354         Bitfield<19>   wxn;     // Write permission implies XN
 355         Bitfield<18>   ntwe;    // Not trap WFE
 356                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 357         Bitfield<18>   rao2;    // Read as one
 358         Bitfield<16>   ntwi;    // Not trap WFI
 359                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 360         Bitfield<16>   rao3;    // Read as one
 361         Bitfield<15>   uct;     // Enable EL0 access to CTR_EL0
 362                                 // (AArch64 SCTLR_EL1 only)
 363         Bitfield<14>   rr;      // Round Robin select (ARMv7 only)
 364         Bitfield<14>   dze;     // Enable EL0 access to DC ZVA
 365                                 // (AArch64 SCTLR_EL1 only)
 366         Bitfield<13>   v;       // Vectors bit (AArch32 only)
 367         Bitfield<13>   endb;    // ARMv8.3 PAuth
 368         Bitfield<12>   i;       // Instruction cache enable
 369         Bitfield<11>   z;       // Branch prediction enable (ARMv7 only)
 370         Bitfield<10>   sw;      // SWP/SWPB enable (ARMv7 only)
 371         Bitfield<9, 8> rs;      // Deprecated protection bits (dropped in ARMv7)
 372         Bitfield<9>    uma;     // User mask access (AArch64 SCTLR_EL1 only)
 373         Bitfield<8>    sed;     // SETEND disable
 374                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 375         Bitfield<7>    b;       // Endianness support (dropped in ARMv7)
 376         Bitfield<7>    itd;     // IT disable
 377                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 378         Bitfield<6, 3> rao4;    // Read as one
 379         Bitfield<6>    thee;    // ThumbEE enable
 380                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 381         Bitfield<5>    cp15ben; // CP15 barrier enable
 382                                 // (AArch32 and AArch64 SCTLR_EL1 only)
 383         Bitfield<4>    sa0;     // Stack Alignment Check Enable for EL0
 384                                 // (AArch64 SCTLR_EL1 only)
 385         Bitfield<3>    sa;      // Stack Alignment Check Enable (AArch64 only)
 386         Bitfield<2>    c;       // Cache enable
 387         Bitfield<1>    a;       // Alignment check enable
 388         Bitfield<0>    m;       // MMU enable
 389     EndBitUnion(SCTLR)
 390
 391     BitUnion32(CPACR)
 392         Bitfield<1, 0> cp0;
 393         Bitfield<3, 2> cp1;
 394         Bitfield<5, 4> cp2;
 395         Bitfield<7, 6> cp3;
 396         Bitfield<9, 8> cp4;
 397         Bitfield<11, 10> cp5;
 398         Bitfield<13, 12> cp6;
 399         Bitfield<15, 14> cp7;
 400         Bitfield<17, 16> cp8;
 401         Bitfield<17, 16> zen;  // SVE
 402         Bitfield<19, 18> cp9;
 403         Bitfield<21, 20> cp10;
 404         Bitfield<21, 20> fpen;  // AArch64
 405         Bitfield<23, 22> cp11;
 406         Bitfield<25, 24> cp12;
 407         Bitfield<27, 26> cp13;
 408         Bitfield<29, 28> rsvd;
 409         Bitfield<28> tta;  // AArch64
 410         Bitfield<30> d32dis;
 411         Bitfield<31> asedis;
 412     EndBitUnion(CPACR)
 413
 414     BitUnion32(FSR)
 415         Bitfield<3, 0> fsLow;
 416         Bitfield<5, 0> status;  // LPAE
 417         Bitfield<7, 4> domain;
 418         Bitfield<9> lpae;
 419         Bitfield<10> fsHigh;
 420         Bitfield<11> wnr;
 421         Bitfield<12> ext;
 422         Bitfield<13> cm;  // LPAE
 423     EndBitUnion(FSR)
 424
 425     BitUnion32(FPSCR)
 426         Bitfield<0> ioc;
 427         Bitfield<1> dzc;
 428         Bitfield<2> ofc;
 429         Bitfield<3> ufc;
 430         Bitfield<4> ixc;
 431         Bitfield<7> idc;
 432         Bitfield<8> ioe;
 433         Bitfield<9> dze;
 434         Bitfield<10> ofe;
 435         Bitfield<11> ufe;
 436         Bitfield<12> ixe;
 437         Bitfield<15> ide;
 438         Bitfield<18, 16> len;
 439         Bitfield<19> fz16;
 440         Bitfield<21, 20> stride;
 441         Bitfield<23, 22> rMode;
 442         Bitfield<24> fz;
 443         Bitfield<25> dn;
 444         Bitfield<26> ahp;
 445         Bitfield<27> qc;
 446         Bitfield<28> v;
 447         Bitfield<29> c;
 448         Bitfield<30> z;
 449         Bitfield<31> n;
 450     EndBitUnion(FPSCR)
 451
 452     BitUnion32(FPEXC)
 453         Bitfield<31> ex;
 454         Bitfield<30> en;
 455         Bitfield<29, 0> subArchDefined;
 456     EndBitUnion(FPEXC)
 457
 458     BitUnion32(MVFR0)
 459         Bitfield<3, 0> advSimdRegisters;
 460         Bitfield<7, 4> singlePrecision;
 461         Bitfield<11, 8> doublePrecision;
 462         Bitfield<15, 12> vfpExceptionTrapping;
 463         Bitfield<19, 16> divide;
 464         Bitfield<23, 20> squareRoot;
 465         Bitfield<27, 24> shortVectors;
 466         Bitfield<31, 28> roundingModes;
 467     EndBitUnion(MVFR0)
 468
 469     BitUnion32(MVFR1)
 470         Bitfield<3, 0> flushToZero;
 471         Bitfield<7, 4> defaultNaN;
 472         Bitfield<11, 8> advSimdLoadStore;
 473         Bitfield<15, 12> advSimdInteger;
 474         Bitfield<19, 16> advSimdSinglePrecision;
 475         Bitfield<23, 20> advSimdHalfPrecision;
 476         Bitfield<27, 24> vfpHalfPrecision;
 477         Bitfield<31, 28> raz;
 478     EndBitUnion(MVFR1)
 479
 480     BitUnion64(TTBCR)
 481         // Short-descriptor translation table format
 482         Bitfield<2, 0> n;
 483         Bitfield<4> pd0;
 484         Bitfield<5> pd1;
 485         // Long-descriptor translation table format
 486         Bitfield<2, 0> t0sz;
 487         Bitfield<6> t2e;
 488         Bitfield<7> epd0;
 489         Bitfield<9, 8> irgn0;
 490         Bitfield<11, 10> orgn0;
 491         Bitfield<13, 12> sh0;
 492         Bitfield<14> tg0;
 493         Bitfield<18, 16> t1sz;
 494         Bitfield<22> a1;
 495         Bitfield<23> epd1;
 496         Bitfield<25, 24> irgn1;
 497         Bitfield<27, 26> orgn1;
 498         Bitfield<29, 28> sh1;
 499         Bitfield<30> tg1;
 500         Bitfield<34, 32> ips;
 501         Bitfield<36> as;
 502         Bitfield<37> tbi0;
 503         Bitfield<38> tbi1;
 504         // Common
 505         Bitfield<31> eae;
 506         // TCR_EL2/3 (AArch64)
 507         Bitfield<18, 16> ps;
 508         Bitfield<20> tbi;
 509         Bitfield<41> hpd0;
 510         Bitfield<42> hpd1;
 511     EndBitUnion(TTBCR)
 512
 513     // Fields of TCR_EL{1,2,3} (mostly overlapping)
 514     // TCR_EL1 is natively 64 bits, the others are 32 bits
 515     BitUnion64(TCR)
 516         Bitfield<5, 0> t0sz;
 517         Bitfield<7> epd0; // EL1
 518         Bitfield<9, 8> irgn0;
 519         Bitfield<11, 10> orgn0;
 520         Bitfield<13, 12> sh0;
 521         Bitfield<15, 14> tg0;
 522         Bitfield<18, 16> ps;
 523         Bitfield<20> tbi; // EL2/EL3
 524         Bitfield<21, 16> t1sz; // EL1
 525         Bitfield<22> a1; // EL1
 526         Bitfield<23> epd1; // EL1
 527         Bitfield<24> hpd; // EL2/EL3, E2H=0
 528         Bitfield<25, 24> irgn1; // EL1
 529         Bitfield<27, 26> orgn1; // EL1
 530         Bitfield<29, 28> sh1; // EL1
 531         Bitfield<29> tbid; // EL2
 532         Bitfield<31, 30> tg1; // EL1
 533         Bitfield<34, 32> ips; // EL1
 534         Bitfield<36> as; // EL1
 535         Bitfield<37> tbi0; // EL1
 536         Bitfield<38> tbi1; // EL1
 537         Bitfield<39> ha;
 538         Bitfield<40> hd;
 539         Bitfield<41> hpd0;
 540         Bitfield<42> hpd1;
 541         Bitfield<51> tbid0; // EL1
 542         Bitfield<52> tbid1; // EL1
 543     EndBitUnion(TCR)
 544
 545     BitUnion32(HTCR)
 546         Bitfield<2, 0> t0sz;
 547         Bitfield<9, 8> irgn0;
 548         Bitfield<11, 10> orgn0;
 549         Bitfield<13, 12> sh0;
 550         Bitfield<24> hpd;
 551     EndBitUnion(HTCR)
 552
 553     BitUnion32(VTCR_t)
 554         Bitfield<3, 0> t0sz;
 555         Bitfield<4> s;
 556         Bitfield<5, 0> t0sz64;
 557         Bitfield<7, 6> sl0;
 558         Bitfield<9, 8> irgn0;
 559         Bitfield<11, 10> orgn0;
 560         Bitfield<13, 12> sh0;
 561         Bitfield<15, 14> tg0;
 562         Bitfield<18, 16> ps; // Only defined for VTCR_EL2
 563         Bitfield<21> ha;     // Only defined for VTCR_EL2
 564         Bitfield<22> hd;     // Only defined for VTCR_EL2
 565     EndBitUnion(VTCR_t)
 566
 567     BitUnion32(PRRR)
 568        Bitfield<1,0> tr0;
 569        Bitfield<3,2> tr1;
 570        Bitfield<5,4> tr2;
 571        Bitfield<7,6> tr3;
 572        Bitfield<9,8> tr4;
 573        Bitfield<11,10> tr5;
 574        Bitfield<13,12> tr6;
 575        Bitfield<15,14> tr7;
 576        Bitfield<16> ds0;
 577        Bitfield<17> ds1;
 578        Bitfield<18> ns0;
 579        Bitfield<19> ns1;
 580        Bitfield<24> nos0;
 581        Bitfield<25> nos1;
 582        Bitfield<26> nos2;
 583        Bitfield<27> nos3;
 584        Bitfield<28> nos4;
 585        Bitfield<29> nos5;
 586        Bitfield<30> nos6;
 587        Bitfield<31> nos7;
 588    EndBitUnion(PRRR)
 589
 590    BitUnion32(NMRR)
 591        Bitfield<1,0> ir0;
 592        Bitfield<3,2> ir1;
 593        Bitfield<5,4> ir2;
 594        Bitfield<7,6> ir3;
 595        Bitfield<9,8> ir4;
 596        Bitfield<11,10> ir5;
 597        Bitfield<13,12> ir6;
 598        Bitfield<15,14> ir7;
 599        Bitfield<17,16> or0;
 600        Bitfield<19,18> or1;
 601        Bitfield<21,20> or2;
 602        Bitfield<23,22> or3;
 603        Bitfield<25,24> or4;
 604        Bitfield<27,26> or5;
 605        Bitfield<29,28> or6;
 606        Bitfield<31,30> or7;
 607    EndBitUnion(NMRR)
 608
 609    BitUnion32(CONTEXTIDR)
 610       Bitfield<7,0>  asid;
 611       Bitfield<31,8> procid;
 612    EndBitUnion(CONTEXTIDR)
 613
 614    BitUnion32(L2CTLR)
 615       Bitfield<2,0>   sataRAMLatency;
 616       Bitfield<4,3>   reserved_4_3;
 617       Bitfield<5>     dataRAMSetup;
 618       Bitfield<8,6>   tagRAMLatency;
 619       Bitfield<9>     tagRAMSetup;
 620       Bitfield<11,10> dataRAMSlice;
 621       Bitfield<12>    tagRAMSlice;
 622       Bitfield<20,13> reserved_20_13;
 623       Bitfield<21>    eccandParityEnable;
 624       Bitfield<22>    reserved_22;
 625       Bitfield<23>    interptCtrlPresent;
 626       Bitfield<25,24> numCPUs;
 627       Bitfield<30,26> reserved_30_26;
 628       Bitfield<31>    l2rstDISABLE_monitor;
 629    EndBitUnion(L2CTLR)
 630
 631    BitUnion32(CTR)
 632       Bitfield<3,0>   iCacheLineSize;
 633       Bitfield<13,4>  raz_13_4;
 634       Bitfield<15,14> l1IndexPolicy;
 635       Bitfield<19,16> dCacheLineSize;
 636       Bitfield<23,20> erg;
 637       Bitfield<27,24> cwg;
 638       Bitfield<28>    raz_28;
 639       Bitfield<31,29> format;
 640    EndBitUnion(CTR)
 641
 642    BitUnion32(PMSELR)
 643       Bitfield<4, 0> sel;
 644    EndBitUnion(PMSELR)
 645
 646     BitUnion64(PAR)
 647         // 64-bit format
 648         Bitfield<63, 56> attr;
 649         Bitfield<39, 12> pa;
 650         Bitfield<11>     lpae;
 651         Bitfield<9>      ns;
 652         Bitfield<8, 7>   sh;
 653         Bitfield<0>      f;
 654    EndBitUnion(PAR)
 655
 656    BitUnion32(ESR)
 657         Bitfield<31, 26> ec;
 658         Bitfield<25> il;
 659         Bitfield<15, 0> imm16;
 660    EndBitUnion(ESR)
 661
 662    BitUnion32(CPTR)
 663         Bitfield<31> tcpac;
 664         Bitfield<20> tta;
 665         Bitfield<13, 12> res1_13_12_el2;
 666         Bitfield<10> tfp;
 667         Bitfield<9> res1_9_el2;
 668         Bitfield<8> res1_8_el2;
 669         Bitfield<8> ez;  // SVE (CPTR_EL3)
 670         Bitfield<8> tz;  // SVE (CPTR_EL2)
 671         Bitfield<7, 0> res1_7_0_el2;
 672    EndBitUnion(CPTR)
 673
 674     BitUnion64(ZCR)
 675         Bitfield<3, 0> len;
 676     EndBitUnion(ZCR)
 677
 678 }
 679
 680 #endif // __ARCH_ARM_MISCREGS_TYPES_HH__