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44 #ifndef __ARCH_ARM_MISCREGS_TYPES_HH__
45 #define __ARCH_ARM_MISCREGS_TYPES_HH__
47 #include "base/bitunion.hh"
59 Bitfield<21> ss; // AArch64
60 Bitfield<20> il; // AArch64
63 Bitfield<9> d; // AArch64
69 Bitfield<9, 6> daif; // AArch64
71 Bitfield<4> width; // AArch64
72 Bitfield<3, 2> el; // AArch64
74 Bitfield<0> sp; // AArch64
78 Bitfield<43, 40> tracefilt;
79 Bitfield<39, 36> doublelock;
80 Bitfield<35, 32> pmsver;
81 Bitfield<31, 28> ctx_cmps;
82 Bitfield<23, 20> wrps;
83 Bitfield<15, 12> brps;
84 Bitfield<11, 8> pmuver;
85 Bitfield<7, 4> tracever;
86 Bitfield<3, 0> debugver;
90 Bitfield<63, 60> rndr;
97 Bitfield<35, 32> sha3;
99 Bitfield<23, 20> atomic;
100 Bitfield<19, 16> crc32;
101 Bitfield<15, 12> sha2;
102 Bitfield<11, 8> sha1;
104 EndBitUnion(AA64ISAR0)
106 BitUnion64(AA64ISAR1)
107 Bitfield<43, 40> specres;
109 Bitfield<35, 32> frintts;
110 Bitfield<31, 28> gpi;
111 Bitfield<27, 24> gpa;
112 Bitfield<23, 20> lrcpc;
113 Bitfield<19, 16> fcma;
114 Bitfield<15, 12> jscvt;
118 EndBitUnion(AA64ISAR1)
120 BitUnion64(AA64MMFR0)
121 Bitfield<47, 44> exs;
122 Bitfield<43, 40> tgran4_2;
123 Bitfield<39, 36> tgran64_2;
124 Bitfield<35, 32> tgran16_2;
125 Bitfield<31, 28> tgran4;
126 Bitfield<27, 24> tgran64;
127 Bitfield<23, 20> tgran16;
128 Bitfield<19, 16> bigendEL0;
129 Bitfield<15, 12> snsmem;
130 Bitfield<11, 8> bigend;
131 Bitfield<7, 4> asidbits;
132 Bitfield<3, 0> parange;
133 EndBitUnion(AA64MMFR0)
135 BitUnion64(AA64MMFR1)
136 Bitfield<31, 28> xnx;
137 Bitfield<27, 24> specsei;
138 Bitfield<23, 20> pan;
140 Bitfield<15, 12> hpds;
142 Bitfield<7, 4> vmidbits;
143 Bitfield<3, 0> hafdbs;
144 EndBitUnion(AA64MMFR1)
146 BitUnion64(AA64MMFR2)
147 Bitfield<63, 60> e0pd;
148 Bitfield<59, 56> evt;
149 Bitfield<55, 52> bbm;
150 Bitfield<51, 48> ttl;
151 Bitfield<43, 40> fwb;
152 Bitfield<39, 36> ids;
156 Bitfield<23, 20> ccidx;
157 Bitfield<19, 16> varange;
158 Bitfield<15, 12> iesb;
162 EndBitUnion(AA64MMFR2)
165 Bitfield<63, 60> csv3;
166 Bitfield<59, 56> csv2;
167 Bitfield<51, 48> dit;
168 Bitfield<47, 44> amu;
169 Bitfield<43, 40> mpam;
170 Bitfield<39, 36> sel2;
171 Bitfield<35, 32> sve;
172 Bitfield<31, 28> ras;
173 Bitfield<27, 24> gic;
174 Bitfield<23, 20> advsimd;
176 Bitfield<15, 12> el3;
180 EndBitUnion(AA64PFR0)
201 Bitfield<10> tfp; // AArch64
204 Bitfield<8> tz; // SVE
236 Bitfield<34> e2h; // AArch64
239 Bitfield<31> rw; // AArch64
240 Bitfield<30> trvm; // AArch64
241 Bitfield<29> hcd; // AArch64
242 Bitfield<28> tdz; // AArch64
251 Bitfield<21> tacr; // AArch64
261 Bitfield<11, 10> bsu;
264 Bitfield<8> vse; // AArch64
276 Bitfield<20> nstrcdis;
278 Bitfield<15> nsasedis;
279 Bitfield<14> nsd32dis;
299 Bitfield<11> st; // AArch64
300 Bitfield<10> rw; // AArch64
304 Bitfield<7> smd; // AArch64
315 Bitfield<30> te; // Thumb Exception Enable (AArch32 only)
316 Bitfield<29> afe; // Access flag enable (AArch32 only)
317 Bitfield<28> tre; // TEX remap enable (AArch32 only)
318 Bitfield<27> nmfi; // Non-maskable FIQ support (ARMv7 only)
319 Bitfield<26> uci; // Enable EL0 access to DC CVAU, DC CIVAC,
320 // DC CVAC and IC IVAU instructions
321 // (AArch64 SCTLR_EL1 only)
322 Bitfield<25> ee; // Exception Endianness
323 Bitfield<24> e0e; // Endianness of explicit data accesses at EL0
324 // (AArch64 SCTLR_EL1 only)
325 Bitfield<23> span; // Set Priviledge Access Never on taking
327 Bitfield<23> xp; // Extended page table enable (dropped in ARMv7)
328 Bitfield<22> u; // Alignment (dropped in ARMv7)
329 Bitfield<21> fi; // Fast interrupts configuration enable
331 Bitfield<20> uwxn; // Unprivileged write permission implies EL1 XN
333 Bitfield<19> dz; // Divide by Zero fault enable
334 // (dropped in ARMv7)
335 Bitfield<19> wxn; // Write permission implies XN
336 Bitfield<18> ntwe; // Not trap WFE
337 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
338 Bitfield<18> rao2; // Read as one
339 Bitfield<16> ntwi; // Not trap WFI
340 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
341 Bitfield<16> rao3; // Read as one
342 Bitfield<15> uct; // Enable EL0 access to CTR_EL0
343 // (AArch64 SCTLR_EL1 only)
344 Bitfield<14> rr; // Round Robin select (ARMv7 only)
345 Bitfield<14> dze; // Enable EL0 access to DC ZVA
346 // (AArch64 SCTLR_EL1 only)
347 Bitfield<13> v; // Vectors bit (AArch32 only)
348 Bitfield<12> i; // Instruction cache enable
349 Bitfield<11> z; // Branch prediction enable (ARMv7 only)
350 Bitfield<10> sw; // SWP/SWPB enable (ARMv7 only)
351 Bitfield<9, 8> rs; // Deprecated protection bits (dropped in ARMv7)
352 Bitfield<9> uma; // User mask access (AArch64 SCTLR_EL1 only)
353 Bitfield<8> sed; // SETEND disable
354 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
355 Bitfield<7> b; // Endianness support (dropped in ARMv7)
356 Bitfield<7> itd; // IT disable
357 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
358 Bitfield<6, 3> rao4; // Read as one
359 Bitfield<6> thee; // ThumbEE enable
360 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
361 Bitfield<5> cp15ben; // CP15 barrier enable
362 // (AArch32 and AArch64 SCTLR_EL1 only)
363 Bitfield<4> sa0; // Stack Alignment Check Enable for EL0
364 // (AArch64 SCTLR_EL1 only)
365 Bitfield<3> sa; // Stack Alignment Check Enable (AArch64 only)
366 Bitfield<2> c; // Cache enable
367 Bitfield<1> a; // Alignment check enable
368 Bitfield<0> m; // MMU enable
377 Bitfield<11, 10> cp5;
378 Bitfield<13, 12> cp6;
379 Bitfield<15, 14> cp7;
380 Bitfield<17, 16> cp8;
381 Bitfield<17, 16> zen; // SVE
382 Bitfield<19, 18> cp9;
383 Bitfield<21, 20> cp10;
384 Bitfield<21, 20> fpen; // AArch64
385 Bitfield<23, 22> cp11;
386 Bitfield<25, 24> cp12;
387 Bitfield<27, 26> cp13;
388 Bitfield<29, 28> rsvd;
389 Bitfield<28> tta; // AArch64
395 Bitfield<3, 0> fsLow;
396 Bitfield<5, 0> status; // LPAE
397 Bitfield<7, 4> domain;
402 Bitfield<13> cm; // LPAE
418 Bitfield<18, 16> len;
420 Bitfield<21, 20> stride;
421 Bitfield<23, 22> rMode;
435 Bitfield<29, 0> subArchDefined;
439 Bitfield<3, 0> advSimdRegisters;
440 Bitfield<7, 4> singlePrecision;
441 Bitfield<11, 8> doublePrecision;
442 Bitfield<15, 12> vfpExceptionTrapping;
443 Bitfield<19, 16> divide;
444 Bitfield<23, 20> squareRoot;
445 Bitfield<27, 24> shortVectors;
446 Bitfield<31, 28> roundingModes;
450 Bitfield<3, 0> flushToZero;
451 Bitfield<7, 4> defaultNaN;
452 Bitfield<11, 8> advSimdLoadStore;
453 Bitfield<15, 12> advSimdInteger;
454 Bitfield<19, 16> advSimdSinglePrecision;
455 Bitfield<23, 20> advSimdHalfPrecision;
456 Bitfield<27, 24> vfpHalfPrecision;
457 Bitfield<31, 28> raz;
461 // Short-descriptor translation table format
465 // Long-descriptor translation table format
469 Bitfield<9, 8> irgn0;
470 Bitfield<11, 10> orgn0;
471 Bitfield<13, 12> sh0;
473 Bitfield<18, 16> t1sz;
476 Bitfield<25, 24> irgn1;
477 Bitfield<27, 26> orgn1;
478 Bitfield<29, 28> sh1;
480 Bitfield<34, 32> ips;
486 // TCR_EL2/3 (AArch64)
493 // Fields of TCR_EL{1,2,3} (mostly overlapping)
494 // TCR_EL1 is natively 64 bits, the others are 32 bits
497 Bitfield<7> epd0; // EL1
498 Bitfield<9, 8> irgn0;
499 Bitfield<11, 10> orgn0;
500 Bitfield<13, 12> sh0;
501 Bitfield<15, 14> tg0;
503 Bitfield<20> tbi; // EL2/EL3
504 Bitfield<21, 16> t1sz; // EL1
505 Bitfield<22> a1; // EL1
506 Bitfield<23> epd1; // EL1
507 Bitfield<24> hpd; // EL2/EL3, E2H=0
508 Bitfield<25, 24> irgn1; // EL1
509 Bitfield<27, 26> orgn1; // EL1
510 Bitfield<29, 28> sh1; // EL1
511 Bitfield<31, 30> tg1; // EL1
512 Bitfield<34, 32> ips; // EL1
513 Bitfield<36> as; // EL1
514 Bitfield<37> tbi0; // EL1
515 Bitfield<38> tbi1; // EL1
524 Bitfield<9, 8> irgn0;
525 Bitfield<11, 10> orgn0;
526 Bitfield<13, 12> sh0;
533 Bitfield<5, 0> t0sz64;
535 Bitfield<9, 8> irgn0;
536 Bitfield<11, 10> orgn0;
537 Bitfield<13, 12> sh0;
538 Bitfield<15, 14> tg0;
539 Bitfield<18, 16> ps; // Only defined for VTCR_EL2
540 Bitfield<21> ha; // Only defined for VTCR_EL2
541 Bitfield<22> hd; // Only defined for VTCR_EL2
586 BitUnion32(CONTEXTIDR)
588 Bitfield<31,8> procid;
589 EndBitUnion(CONTEXTIDR)
592 Bitfield<2,0> sataRAMLatency;
593 Bitfield<4,3> reserved_4_3;
594 Bitfield<5> dataRAMSetup;
595 Bitfield<8,6> tagRAMLatency;
596 Bitfield<9> tagRAMSetup;
597 Bitfield<11,10> dataRAMSlice;
598 Bitfield<12> tagRAMSlice;
599 Bitfield<20,13> reserved_20_13;
600 Bitfield<21> eccandParityEnable;
601 Bitfield<22> reserved_22;
602 Bitfield<23> interptCtrlPresent;
603 Bitfield<25,24> numCPUs;
604 Bitfield<30,26> reserved_30_26;
605 Bitfield<31> l2rstDISABLE_monitor;
609 Bitfield<3,0> iCacheLineSize;
610 Bitfield<13,4> raz_13_4;
611 Bitfield<15,14> l1IndexPolicy;
612 Bitfield<19,16> dCacheLineSize;
616 Bitfield<31,29> format;
625 Bitfield<63, 56> attr;
636 Bitfield<15, 0> imm16;
642 Bitfield<13, 12> res1_13_12_el2;
644 Bitfield<9> res1_9_el2;
645 Bitfield<8> res1_8_el2;
646 Bitfield<8> ez; // SVE (CPTR_EL3)
647 Bitfield<8> tz; // SVE (CPTR_EL2)
648 Bitfield<7, 0> res1_7_0_el2;
657 #endif // __ARCH_ARM_MISCREGS_TYPES_HH__