src/arch/arm/miscregs_types.hh

   1 /*
   2  * Copyright (c) 2010-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2009 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_MISCREGS_TYPES_HH__
  42 #define __ARCH_ARM_MISCREGS_TYPES_HH__
  43
  44 #include "base/bitunion.hh"
  45
  46 namespace ArmISA
  47 {
  48     BitUnion32(CPSR)
  49         Bitfield<31, 30> nz;
  50         Bitfield<29> c;
  51         Bitfield<28> v;
  52         Bitfield<27> q;
  53         Bitfield<26, 25> it1;
  54         Bitfield<24> j;
  55         Bitfield<22> pan;
  56         Bitfield<21> ss;        // AArch64
  57         Bitfield<20> il;        // AArch64
  58         Bitfield<19, 16> ge;
  59         Bitfield<15, 10> it2;
  60         Bitfield<9> d;          // AArch64
  61         Bitfield<9> e;
  62         Bitfield<8> a;
  63         Bitfield<7> i;
  64         Bitfield<6> f;
  65         Bitfield<8, 6> aif;
  66         Bitfield<9, 6> daif;    // AArch64
  67         Bitfield<5> t;
  68         Bitfield<4> width;      // AArch64
  69         Bitfield<3, 2> el;      // AArch64
  70         Bitfield<4, 0> mode;
  71         Bitfield<0> sp;         // AArch64
  72     EndBitUnion(CPSR)
  73
  74     BitUnion64(AA64DFR0)
  75         Bitfield<43, 40> tracefilt;
  76         Bitfield<39, 36> doublelock;
  77         Bitfield<35, 32> pmsver;
  78         Bitfield<31, 28> ctx_cmps;
  79         Bitfield<23, 20> wrps;
  80         Bitfield<15, 12> brps;
  81         Bitfield<11, 8> pmuver;
  82         Bitfield<7, 4> tracever;
  83         Bitfield<3, 0> debugver;
  84     EndBitUnion(AA64DFR0)
  85
  86     BitUnion64(AA64ISAR0)
  87         Bitfield<63, 60> rndr;
  88         Bitfield<59, 56> tlb;
  89         Bitfield<55, 52> ts;
  90         Bitfield<51, 48> fhm;
  91         Bitfield<47, 44> dp;
  92         Bitfield<43, 40> sm4;
  93         Bitfield<39, 36> sm3;
  94         Bitfield<35, 32> sha3;
  95         Bitfield<31, 28> rdm;
  96         Bitfield<23, 20> atomic;
  97         Bitfield<19, 16> crc32;
  98         Bitfield<15, 12> sha2;
  99         Bitfield<11, 8> sha1;
 100         Bitfield<3, 0> aes;
 101     EndBitUnion(AA64ISAR0)
 102
 103     BitUnion64(AA64ISAR1)
 104         Bitfield<43, 40> specres;
 105         Bitfield<39, 36> sb;
 106         Bitfield<35, 32> frintts;
 107         Bitfield<31, 28> gpi;
 108         Bitfield<27, 24> gpa;
 109         Bitfield<23, 20> lrcpc;
 110         Bitfield<19, 16> fcma;
 111         Bitfield<15, 12> jscvt;
 112         Bitfield<11, 8> api;
 113         Bitfield<7, 4> apa;
 114         Bitfield<3, 0> dpb;
 115     EndBitUnion(AA64ISAR1)
 116
 117     BitUnion64(AA64MMFR0)
 118         Bitfield<63, 60> ecv;
 119         Bitfield<47, 44> exs;
 120         Bitfield<43, 40> tgran4_2;
 121         Bitfield<39, 36> tgran64_2;
 122         Bitfield<35, 32> tgran16_2;
 123         Bitfield<31, 28> tgran4;
 124         Bitfield<27, 24> tgran64;
 125         Bitfield<23, 20> tgran16;
 126         Bitfield<19, 16> bigendEL0;
 127         Bitfield<15, 12> snsmem;
 128         Bitfield<11, 8> bigend;
 129         Bitfield<7, 4> asidbits;
 130         Bitfield<3, 0> parange;
 131     EndBitUnion(AA64MMFR0)
 132
 133     BitUnion64(AA64MMFR1)
 134         Bitfield<31, 28> xnx;
 135         Bitfield<27, 24> specsei;
 136         Bitfield<23, 20> pan;
 137         Bitfield<19, 16> lo;
 138         Bitfield<15, 12> hpds;
 139         Bitfield<11, 8> vh;
 140         Bitfield<7, 4> vmidbits;
 141         Bitfield<3, 0> hafdbs;
 142     EndBitUnion(AA64MMFR1)
 143
 144     BitUnion64(AA64MMFR2)
 145         Bitfield<63, 60> e0pd;
 146         Bitfield<59, 56> evt;
 147         Bitfield<55, 52> bbm;
 148         Bitfield<51, 48> ttl;
 149         Bitfield<43, 40> fwb;
 150         Bitfield<39, 36> ids;
 151         Bitfield<35, 32> at;
 152         Bitfield<31, 28> st;
 153         Bitfield<27, 24> nv;
 154         Bitfield<23, 20> ccidx;
 155         Bitfield<19, 16> varange;
 156         Bitfield<15, 12> iesb;
 157         Bitfield<11, 8> lsm;
 158         Bitfield<7, 4> uao;
 159         Bitfield<3, 0> cnp;
 160     EndBitUnion(AA64MMFR2)
 161
 162     BitUnion64(AA64PFR0)
 163         Bitfield<63, 60> csv3;
 164         Bitfield<59, 56> csv2;
 165         Bitfield<51, 48> dit;
 166         Bitfield<47, 44> amu;
 167         Bitfield<43, 40> mpam;
 168         Bitfield<39, 36> sel2;
 169         Bitfield<35, 32> sve;
 170         Bitfield<31, 28> ras;
 171         Bitfield<27, 24> gic;
 172         Bitfield<23, 20> advsimd;
 173         Bitfield<19, 16> fp;
 174         Bitfield<15, 12> el3;
 175         Bitfield<11, 8> el2;
 176         Bitfield<7, 4> el1;
 177         Bitfield<3, 0> el0;
 178     EndBitUnion(AA64PFR0)
 179
 180     BitUnion32(HDCR)
 181         Bitfield<11>   tdra;
 182         Bitfield<10>   tdosa;
 183         Bitfield<9>    tda;
 184         Bitfield<8>    tde;
 185         Bitfield<7>    hpme;
 186         Bitfield<6>    tpm;
 187         Bitfield<5>    tpmcr;
 188         Bitfield<4, 0> hpmn;
 189     EndBitUnion(HDCR)
 190
 191     BitUnion32(HCPTR)
 192         Bitfield<31> tcpac;
 193         Bitfield<20> tta;
 194         Bitfield<15> tase;
 195         Bitfield<13> tcp13;
 196         Bitfield<12> tcp12;
 197         Bitfield<11> tcp11;
 198         Bitfield<10> tcp10;
 199         Bitfield<10> tfp;  // AArch64
 200         Bitfield<9>  tcp9;
 201         Bitfield<8>  tcp8;
 202         Bitfield<8>  tz;  // SVE
 203         Bitfield<7>  tcp7;
 204         Bitfield<6>  tcp6;
 205         Bitfield<5>  tcp5;
 206         Bitfield<4>  tcp4;
 207         Bitfield<3>  tcp3;
 208         Bitfield<2>  tcp2;
 209         Bitfield<1>  tcp1;
 210         Bitfield<0>  tcp0;
 211     EndBitUnion(HCPTR)
 212
 213     BitUnion32(HSTR)
 214         Bitfield<17> tjdbx;
 215         Bitfield<16> ttee;
 216         Bitfield<15> t15;
 217         Bitfield<13> t13;
 218         Bitfield<12> t12;
 219         Bitfield<11> t11;
 220         Bitfield<10> t10;
 221         Bitfield<9>  t9;
 222         Bitfield<8>  t8;
 223         Bitfield<7>  t7;
 224         Bitfield<6>  t6;
 225         Bitfield<5>  t5;
 226         Bitfield<4>  t4;
 227         Bitfield<3>  t3;
 228         Bitfield<2>  t2;
 229         Bitfield<1>  t1;
 230         Bitfield<0>  t0;
 231     EndBitUnion(HSTR)
 232
 233     BitUnion64(HCR)
 234         Bitfield<47>     fien;
 235         Bitfield<46>     fwb;
 236         Bitfield<45>     nv2;
 237         Bitfield<44>     at;
 238         Bitfield<43>     nv1;
 239         Bitfield<42>     nv;
 240         Bitfield<41>     api;
 241         Bitfield<40>     apk;
 242         Bitfield<38>     miocnce;
 243         Bitfield<37>     tea;
 244         Bitfield<36>     terr;
 245         Bitfield<35>     tlor;
 246         Bitfield<34>     e2h;   // AArch64
 247         Bitfield<33>     id;
 248         Bitfield<32>     cd;
 249         Bitfield<31>     rw;    // AArch64
 250         Bitfield<30>     trvm;  // AArch64
 251         Bitfield<29>     hcd;   // AArch64
 252         Bitfield<28>     tdz;   // AArch64
 253         Bitfield<27>     tge;
 254         Bitfield<26>     tvm;
 255         Bitfield<25>     ttlb;
 256         Bitfield<24>     tpu;
 257         Bitfield<23>     tpc;
 258         Bitfield<22>     tsw;
 259         Bitfield<21>     tac;
 260         Bitfield<21>     tacr;  // AArch64
 261         Bitfield<20>     tidcp;
 262         Bitfield<19>     tsc;
 263         Bitfield<18>     tid3;
 264         Bitfield<17>     tid2;
 265         Bitfield<16>     tid1;
 266         Bitfield<15>     tid0;
 267         Bitfield<14>     twe;
 268         Bitfield<13>     twi;
 269         Bitfield<12>     dc;
 270         Bitfield<11, 10> bsu;
 271         Bitfield<9>      fb;
 272         Bitfield<8>      va;
 273         Bitfield<8>      vse;   // AArch64
 274         Bitfield<7>      vi;
 275         Bitfield<6>      vf;
 276         Bitfield<5>      amo;
 277         Bitfield<4>      imo;
 278         Bitfield<3>      fmo;
 279         Bitfield<2>      ptw;
 280         Bitfield<1>      swio;
 281         Bitfield<0>      vm;
 282     EndBitUnion(HCR)
 283
 284     BitUnion32(NSACR)
 285         Bitfield<20> nstrcdis;
 286         Bitfield<19> rfr;
 287         Bitfield<15> nsasedis;
 288         Bitfield<14> nsd32dis;
 289         Bitfield<13> cp13;
 290         Bitfield<12> cp12;
 291         Bitfield<11> cp11;
 292         Bitfield<10> cp10;
 293         Bitfield<9>  cp9;
 294         Bitfield<8>  cp8;
 295         Bitfield<7>  cp7;
 296         Bitfield<6>  cp6;
 297         Bitfield<5>  cp5;
 298         Bitfield<4>  cp4;
 299         Bitfield<3>  cp3;
 300         Bitfield<2>  cp2;
 301         Bitfield<1>  cp1;
 302         Bitfield<0>  cp0;
 303     EndBitUnion(NSACR)
 304
 305     BitUnion32(SCR)
 306         Bitfield<21> fien;
 307         Bitfield<20> nmea;
 308         Bitfield<19> ease;
 309         Bitfield<18> eel2; // AArch64 (Armv8.4-SecEL2)
 310         Bitfield<17> api;
 311         Bitfield<16> apk;
 312         Bitfield<15> teer;
 313         Bitfield<14> tlor;
 314         Bitfield<13> twe;
 315         Bitfield<12> twi;
 316         Bitfield<11> st;   // AArch64
 317         Bitfield<10> rw;   // AArch64
 318         Bitfield<9> sif;
 319         Bitfield<8> hce;
 320         Bitfield<7> scd;
 321         Bitfield<7> smd;   // AArch64
 322         Bitfield<6> nEt;
 323         Bitfield<5> aw;
 324         Bitfield<4> fw;
 325         Bitfield<3> ea;
 326         Bitfield<2> fiq;
 327         Bitfield<1> irq;
 328         Bitfield<0> ns;
 329     EndBitUnion(SCR)
 330
 331     BitUnion32(SCTLR)
 332         Bitfield<31>   enia;    // ARMv8.3 PAuth
 333         Bitfield<30>   enib;    // ARMv8.3 PAuth
 334         Bitfield<30>   te;      // Thumb Exception Enable (AArch32 only)
 335         Bitfield<29>   afe;     // Access flag enable (AArch32 only)
 336         Bitfield<28>   tre;     // TEX remap enable (AArch32 only)
 337         Bitfield<27>   nmfi;    // Non-maskable FIQ support (ARMv7 only)
 338         Bitfield<27>   enda;    // ARMv8.3 PAuth
 339         Bitfield<26>   uci;     // Enable EL0 access to DC CVAU, DC CIVAC,
 340                                 // DC CVAC and IC IVAU instructions
 341                                 // (AArch64 SCTLR_EL1 only)
 342         Bitfield<25>   ee;      // Exception Endianness
 343         Bitfield<24>   e0e;     // Endianness of explicit data accesses at EL0
 344                                 // (AArch64 SCTLR_EL1 only)
 345         Bitfield<23>   span;    // Set Priviledge Access Never on taking
 346                                 // an exception
 347         Bitfield<23>   xp;      // Extended page table enable (dropped in ARMv7)
 348         Bitfield<22>   u;       // Alignment (dropped in ARMv7)
 349         Bitfield<21>   fi;      // Fast interrupts configuration enable
 350                                 // (ARMv7 only)
 351         Bitfield<20>   uwxn;    // Unprivileged write permission implies EL1 XN
 352                                 // (AArch32 only)
 353         Bitfield<19>   dz;      // Divide by Zero fault enable
 354                                 // (dropped in ARMv7)
 355         Bitfield<19>   wxn;     // Write permission implies XN
 356         Bitfield<18>   ntwe;    // Not trap WFE
 357                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 358         Bitfield<18>   rao2;    // Read as one
 359         Bitfield<16>   ntwi;    // Not trap WFI
 360                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 361         Bitfield<16>   rao3;    // Read as one
 362         Bitfield<15>   uct;     // Enable EL0 access to CTR_EL0
 363                                 // (AArch64 SCTLR_EL1 only)
 364         Bitfield<14>   rr;      // Round Robin select (ARMv7 only)
 365         Bitfield<14>   dze;     // Enable EL0 access to DC ZVA
 366                                 // (AArch64 SCTLR_EL1 only)
 367         Bitfield<13>   v;       // Vectors bit (AArch32 only)
 368         Bitfield<13>   endb;    // ARMv8.3 PAuth
 369         Bitfield<12>   i;       // Instruction cache enable
 370         Bitfield<11>   z;       // Branch prediction enable (ARMv7 only)
 371         Bitfield<10>   sw;      // SWP/SWPB enable (ARMv7 only)
 372         Bitfield<9, 8> rs;      // Deprecated protection bits (dropped in ARMv7)
 373         Bitfield<9>    uma;     // User mask access (AArch64 SCTLR_EL1 only)
 374         Bitfield<8>    sed;     // SETEND disable
 375                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 376         Bitfield<7>    b;       // Endianness support (dropped in ARMv7)
 377         Bitfield<7>    itd;     // IT disable
 378                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 379         Bitfield<6, 3> rao4;    // Read as one
 380         Bitfield<6>    thee;    // ThumbEE enable
 381                                 // (ARMv8 AArch32 and AArch64 SCTLR_EL1 only)
 382         Bitfield<5>    cp15ben; // CP15 barrier enable
 383                                 // (AArch32 and AArch64 SCTLR_EL1 only)
 384         Bitfield<4>    sa0;     // Stack Alignment Check Enable for EL0
 385                                 // (AArch64 SCTLR_EL1 only)
 386         Bitfield<3>    sa;      // Stack Alignment Check Enable (AArch64 only)
 387         Bitfield<2>    c;       // Cache enable
 388         Bitfield<1>    a;       // Alignment check enable
 389         Bitfield<0>    m;       // MMU enable
 390     EndBitUnion(SCTLR)
 391
 392     BitUnion32(CPACR)
 393         Bitfield<1, 0> cp0;
 394         Bitfield<3, 2> cp1;
 395         Bitfield<5, 4> cp2;
 396         Bitfield<7, 6> cp3;
 397         Bitfield<9, 8> cp4;
 398         Bitfield<11, 10> cp5;
 399         Bitfield<13, 12> cp6;
 400         Bitfield<15, 14> cp7;
 401         Bitfield<17, 16> cp8;
 402         Bitfield<17, 16> zen;  // SVE
 403         Bitfield<19, 18> cp9;
 404         Bitfield<21, 20> cp10;
 405         Bitfield<21, 20> fpen;  // AArch64
 406         Bitfield<23, 22> cp11;
 407         Bitfield<25, 24> cp12;
 408         Bitfield<27, 26> cp13;
 409         Bitfield<29, 28> rsvd;
 410         Bitfield<28> tta;  // AArch64
 411         Bitfield<30> d32dis;
 412         Bitfield<31> asedis;
 413     EndBitUnion(CPACR)
 414
 415     BitUnion32(FSR)
 416         Bitfield<3, 0> fsLow;
 417         Bitfield<5, 0> status;  // LPAE
 418         Bitfield<7, 4> domain;
 419         Bitfield<9> lpae;
 420         Bitfield<10> fsHigh;
 421         Bitfield<11> wnr;
 422         Bitfield<12> ext;
 423         Bitfield<13> cm;  // LPAE
 424     EndBitUnion(FSR)
 425
 426     BitUnion32(FPSCR)
 427         Bitfield<0> ioc;
 428         Bitfield<1> dzc;
 429         Bitfield<2> ofc;
 430         Bitfield<3> ufc;
 431         Bitfield<4> ixc;
 432         Bitfield<7> idc;
 433         Bitfield<8> ioe;
 434         Bitfield<9> dze;
 435         Bitfield<10> ofe;
 436         Bitfield<11> ufe;
 437         Bitfield<12> ixe;
 438         Bitfield<15> ide;
 439         Bitfield<18, 16> len;
 440         Bitfield<19> fz16;
 441         Bitfield<21, 20> stride;
 442         Bitfield<23, 22> rMode;
 443         Bitfield<24> fz;
 444         Bitfield<25> dn;
 445         Bitfield<26> ahp;
 446         Bitfield<27> qc;
 447         Bitfield<28> v;
 448         Bitfield<29> c;
 449         Bitfield<30> z;
 450         Bitfield<31> n;
 451     EndBitUnion(FPSCR)
 452
 453     BitUnion32(FPEXC)
 454         Bitfield<31> ex;
 455         Bitfield<30> en;
 456         Bitfield<29, 0> subArchDefined;
 457     EndBitUnion(FPEXC)
 458
 459     BitUnion32(MVFR0)
 460         Bitfield<3, 0> advSimdRegisters;
 461         Bitfield<7, 4> singlePrecision;
 462         Bitfield<11, 8> doublePrecision;
 463         Bitfield<15, 12> vfpExceptionTrapping;
 464         Bitfield<19, 16> divide;
 465         Bitfield<23, 20> squareRoot;
 466         Bitfield<27, 24> shortVectors;
 467         Bitfield<31, 28> roundingModes;
 468     EndBitUnion(MVFR0)
 469
 470     BitUnion32(MVFR1)
 471         Bitfield<3, 0> flushToZero;
 472         Bitfield<7, 4> defaultNaN;
 473         Bitfield<11, 8> advSimdLoadStore;
 474         Bitfield<15, 12> advSimdInteger;
 475         Bitfield<19, 16> advSimdSinglePrecision;
 476         Bitfield<23, 20> advSimdHalfPrecision;
 477         Bitfield<27, 24> vfpHalfPrecision;
 478         Bitfield<31, 28> raz;
 479     EndBitUnion(MVFR1)
 480
 481     BitUnion64(TTBCR)
 482         // Short-descriptor translation table format
 483         Bitfield<2, 0> n;
 484         Bitfield<4> pd0;
 485         Bitfield<5> pd1;
 486         // Long-descriptor translation table format
 487         Bitfield<2, 0> t0sz;
 488         Bitfield<6> t2e;
 489         Bitfield<7> epd0;
 490         Bitfield<9, 8> irgn0;
 491         Bitfield<11, 10> orgn0;
 492         Bitfield<13, 12> sh0;
 493         Bitfield<14> tg0;
 494         Bitfield<18, 16> t1sz;
 495         Bitfield<22> a1;
 496         Bitfield<23> epd1;
 497         Bitfield<25, 24> irgn1;
 498         Bitfield<27, 26> orgn1;
 499         Bitfield<29, 28> sh1;
 500         Bitfield<30> tg1;
 501         Bitfield<34, 32> ips;
 502         Bitfield<36> as;
 503         Bitfield<37> tbi0;
 504         Bitfield<38> tbi1;
 505         // Common
 506         Bitfield<31> eae;
 507         // TCR_EL2/3 (AArch64)
 508         Bitfield<18, 16> ps;
 509         Bitfield<20> tbi;
 510         Bitfield<41> hpd0;
 511         Bitfield<42> hpd1;
 512     EndBitUnion(TTBCR)
 513
 514     // Fields of TCR_EL{1,2,3} (mostly overlapping)
 515     // TCR_EL1 is natively 64 bits, the others are 32 bits
 516     BitUnion64(TCR)
 517         Bitfield<5, 0> t0sz;
 518         Bitfield<7> epd0; // EL1
 519         Bitfield<9, 8> irgn0;
 520         Bitfield<11, 10> orgn0;
 521         Bitfield<13, 12> sh0;
 522         Bitfield<15, 14> tg0;
 523         Bitfield<18, 16> ps;
 524         Bitfield<20> tbi; // EL2/EL3
 525         Bitfield<21, 16> t1sz; // EL1
 526         Bitfield<22> a1; // EL1
 527         Bitfield<23> epd1; // EL1
 528         Bitfield<24> hpd; // EL2/EL3, E2H=0
 529         Bitfield<25, 24> irgn1; // EL1
 530         Bitfield<27, 26> orgn1; // EL1
 531         Bitfield<29, 28> sh1; // EL1
 532         Bitfield<29> tbid; // EL2
 533         Bitfield<31, 30> tg1; // EL1
 534         Bitfield<34, 32> ips; // EL1
 535         Bitfield<36> as; // EL1
 536         Bitfield<37> tbi0; // EL1
 537         Bitfield<38> tbi1; // EL1
 538         Bitfield<39> ha;
 539         Bitfield<40> hd;
 540         Bitfield<41> hpd0;
 541         Bitfield<42> hpd1;
 542         Bitfield<51> tbid0; // EL1
 543         Bitfield<52> tbid1; // EL1
 544     EndBitUnion(TCR)
 545
 546     BitUnion32(HTCR)
 547         Bitfield<2, 0> t0sz;
 548         Bitfield<9, 8> irgn0;
 549         Bitfield<11, 10> orgn0;
 550         Bitfield<13, 12> sh0;
 551         Bitfield<24> hpd;
 552     EndBitUnion(HTCR)
 553
 554     BitUnion32(VTCR_t)
 555         Bitfield<3, 0> t0sz;
 556         Bitfield<4> s;
 557         Bitfield<5, 0> t0sz64;
 558         Bitfield<7, 6> sl0;
 559         Bitfield<9, 8> irgn0;
 560         Bitfield<11, 10> orgn0;
 561         Bitfield<13, 12> sh0;
 562         Bitfield<15, 14> tg0;
 563         Bitfield<18, 16> ps; // Only defined for VTCR_EL2
 564         Bitfield<21> ha;     // Only defined for VTCR_EL2
 565         Bitfield<22> hd;     // Only defined for VTCR_EL2
 566     EndBitUnion(VTCR_t)
 567
 568     BitUnion32(PRRR)
 569        Bitfield<1,0> tr0;
 570        Bitfield<3,2> tr1;
 571        Bitfield<5,4> tr2;
 572        Bitfield<7,6> tr3;
 573        Bitfield<9,8> tr4;
 574        Bitfield<11,10> tr5;
 575        Bitfield<13,12> tr6;
 576        Bitfield<15,14> tr7;
 577        Bitfield<16> ds0;
 578        Bitfield<17> ds1;
 579        Bitfield<18> ns0;
 580        Bitfield<19> ns1;
 581        Bitfield<24> nos0;
 582        Bitfield<25> nos1;
 583        Bitfield<26> nos2;
 584        Bitfield<27> nos3;
 585        Bitfield<28> nos4;
 586        Bitfield<29> nos5;
 587        Bitfield<30> nos6;
 588        Bitfield<31> nos7;
 589    EndBitUnion(PRRR)
 590
 591    BitUnion32(NMRR)
 592        Bitfield<1,0> ir0;
 593        Bitfield<3,2> ir1;
 594        Bitfield<5,4> ir2;
 595        Bitfield<7,6> ir3;
 596        Bitfield<9,8> ir4;
 597        Bitfield<11,10> ir5;
 598        Bitfield<13,12> ir6;
 599        Bitfield<15,14> ir7;
 600        Bitfield<17,16> or0;
 601        Bitfield<19,18> or1;
 602        Bitfield<21,20> or2;
 603        Bitfield<23,22> or3;
 604        Bitfield<25,24> or4;
 605        Bitfield<27,26> or5;
 606        Bitfield<29,28> or6;
 607        Bitfield<31,30> or7;
 608    EndBitUnion(NMRR)
 609
 610    BitUnion32(CONTEXTIDR)
 611       Bitfield<7,0>  asid;
 612       Bitfield<31,8> procid;
 613    EndBitUnion(CONTEXTIDR)
 614
 615    BitUnion32(L2CTLR)
 616       Bitfield<2,0>   sataRAMLatency;
 617       Bitfield<4,3>   reserved_4_3;
 618       Bitfield<5>     dataRAMSetup;
 619       Bitfield<8,6>   tagRAMLatency;
 620       Bitfield<9>     tagRAMSetup;
 621       Bitfield<11,10> dataRAMSlice;
 622       Bitfield<12>    tagRAMSlice;
 623       Bitfield<20,13> reserved_20_13;
 624       Bitfield<21>    eccandParityEnable;
 625       Bitfield<22>    reserved_22;
 626       Bitfield<23>    interptCtrlPresent;
 627       Bitfield<25,24> numCPUs;
 628       Bitfield<30,26> reserved_30_26;
 629       Bitfield<31>    l2rstDISABLE_monitor;
 630    EndBitUnion(L2CTLR)
 631
 632    BitUnion32(CTR)
 633       Bitfield<3,0>   iCacheLineSize;
 634       Bitfield<13,4>  raz_13_4;
 635       Bitfield<15,14> l1IndexPolicy;
 636       Bitfield<19,16> dCacheLineSize;
 637       Bitfield<23,20> erg;
 638       Bitfield<27,24> cwg;
 639       Bitfield<28>    raz_28;
 640       Bitfield<31,29> format;
 641    EndBitUnion(CTR)
 642
 643    BitUnion32(PMSELR)
 644       Bitfield<4, 0> sel;
 645    EndBitUnion(PMSELR)
 646
 647     BitUnion64(PAR)
 648         // 64-bit format
 649         Bitfield<63, 56> attr;
 650         Bitfield<39, 12> pa;
 651         Bitfield<11>     lpae;
 652         Bitfield<9>      ns;
 653         Bitfield<9>      s;
 654         Bitfield<8, 7>   sh;
 655         Bitfield<8>      ptw;
 656         Bitfield<6, 1>   fst;
 657         Bitfield<6>      fs5;
 658         Bitfield<5, 1>   fs4_0;
 659         Bitfield<0>      f;
 660    EndBitUnion(PAR)
 661
 662    BitUnion32(ESR)
 663         Bitfield<31, 26> ec;
 664         Bitfield<25> il;
 665         Bitfield<15, 0> imm16;
 666    EndBitUnion(ESR)
 667
 668    BitUnion32(CPTR)
 669         Bitfield<31> tcpac;
 670         Bitfield<30> tam;
 671         Bitfield<28> tta_e2h;
 672         Bitfield<21, 20> fpen;
 673         Bitfield<20> tta;
 674         Bitfield<17, 16> zen;
 675         Bitfield<13, 12> res1_13_12_el2;
 676         Bitfield<10> tfp;
 677         Bitfield<9> res1_9_el2;
 678         Bitfield<8> res1_8_el2;
 679         Bitfield<8> ez;  // SVE (CPTR_EL3)
 680         Bitfield<8> tz;  // SVE (CPTR_EL2)
 681         Bitfield<7, 0> res1_7_0_el2;
 682    EndBitUnion(CPTR)
 683
 684     BitUnion64(ZCR)
 685         Bitfield<3, 0> len;
 686     EndBitUnion(ZCR)
 687
 688    BitUnion32(OSL)
 689         Bitfield<64, 4> res0;
 690         Bitfield<3> oslm_3;
 691         Bitfield<2> nTT;
 692         Bitfield<1> oslk;
 693         Bitfield<0> oslm_0;
 694    EndBitUnion(OSL)
 695
 696    BitUnion64(DBGBCR)
 697         Bitfield<63, 24> res0_2;
 698         Bitfield<23, 20> bt;
 699         Bitfield<19, 16> lbn;
 700         Bitfield<15, 14> ssc;
 701         Bitfield<13> hmc;
 702         Bitfield<12, 9> res0_1;
 703         Bitfield<8, 5> bas;
 704         Bitfield<4, 3> res0_0;
 705         Bitfield<2, 1> pmc;
 706         Bitfield<0> e;
 707    EndBitUnion(DBGBCR)
 708
 709     BitUnion64(DBGWCR)
 710         Bitfield<63, 29> res0_2;
 711         Bitfield<28, 24> mask;
 712         Bitfield<23, 21> res0_1;
 713         Bitfield<20> wt;
 714         Bitfield<19, 16> lbn;
 715         Bitfield<15, 14> ssc;
 716         Bitfield<13> hmc;
 717         Bitfield<12, 5> bas;
 718         Bitfield<4, 3> lsv;
 719         Bitfield<2, 1> pac;
 720         Bitfield<0> e;
 721    EndBitUnion(DBGWCR)
 722
 723    BitUnion32(DBGDS32)
 724         Bitfield<31> tfo;
 725         Bitfield<30> rxfull;
 726         Bitfield<29> txfull;
 727         Bitfield<28> res0_5;
 728         Bitfield<27> rxo;
 729         Bitfield<26> txu;
 730         Bitfield<25, 24> res0_4;
 731         Bitfield<23, 22> intdis;
 732         Bitfield<21> tda;
 733         Bitfield<20> res0_3;
 734         Bitfield<19> sc2;
 735         Bitfield<18> ns;
 736         Bitfield<17> spniddis;
 737         Bitfield<16> spiddis;
 738         Bitfield<15> mdbgen;
 739         Bitfield<14> hde;
 740         Bitfield<13> res0_;
 741         Bitfield<12> udccdis;
 742         Bitfield<12> tdcc;
 743         Bitfield<11, 7> res0_2;
 744         Bitfield<6> err;
 745         Bitfield<5, 2> moe;
 746         Bitfield<1, 0> res0_1;
 747    EndBitUnion(DBGDS32)
 748
 749    BitUnion32(DBGVCR)
 750         Bitfield<31> nsf;
 751         Bitfield<30> nsi;
 752         Bitfield<29> res0_5;
 753         Bitfield<28> nsd;
 754         Bitfield<27> nsp;
 755         Bitfield<26> nss;
 756         Bitfield<25> nsu;
 757         Bitfield<24, 16> res0_4;
 758         Bitfield<15> mf;
 759         Bitfield<14> mi;
 760         Bitfield<13> res0_3;
 761         Bitfield<12> md;
 762         Bitfield<11> mp;
 763         Bitfield<10> ms;
 764         Bitfield<9,8> res0_2;
 765         Bitfield<7> sf;
 766         Bitfield<6> si;
 767         Bitfield<5> res0_1;
 768         Bitfield<4> sd;
 769         Bitfield<3> sp;
 770         Bitfield<2> ss;
 771         Bitfield<1> su;
 772         Bitfield<0> res0_0;
 773    EndBitUnion(DBGVCR)
 774
 775    BitUnion32(DEVID)
 776         Bitfield<31,28> cidmask;
 777         Bitfield<27,24> auxregs;
 778         Bitfield<23,20> doublelock;
 779         Bitfield<19,16> virtextns;
 780         Bitfield<15,12> vectorcatch;
 781         Bitfield<11,8>  bpaddremask;
 782         Bitfield<7,4>   wpaddrmask;
 783         Bitfield<3,0>   pcsample;
 784    EndBitUnion(DEVID)
 785
 786 }
 787
 788 #endif // __ARCH_ARM_MISCREGS_TYPES_HH__