src/arch/arm/mmapped_ipr.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * Copyright (c) 2007-2008 The Florida State University
   4  * All rights reserved.
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions are
   8  * met: redistributions of source code must retain the above copyright
   9  * notice, this list of conditions and the following disclaimer;
  10  * redistributions in binary form must reproduce the above copyright
  11  * notice, this list of conditions and the following disclaimer in the
  12  * documentation and/or other materials provided with the distribution;
  13  * neither the name of the copyright holders nor the names of its
  14  * contributors may be used to endorse or promote products derived from
  15  * this software without specific prior written permission.
  16  *
  17  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28  *
  29  * Authors: Ali Saidi
  30  *          Stephen Hines
  31  */
  32
  33 #ifndef __ARCH_ARM_MMAPPED_IPR_HH__
  34 #define __ARCH_ARM_MMAPPED_IPR_HH__
  35
  36 /**
  37  * @file
  38  *
  39  * ISA-specific helper functions for memory mapped IPR accesses.
  40  */
  41
  42 #include "base/types.hh"
  43 #include "mem/packet.hh"
  44 #include "mem/packet_access.hh"
  45 #include "sim/pseudo_inst.hh"
  46 #include "sim/system.hh"
  47
  48 class ThreadContext;
  49
  50 namespace ArmISA
  51 {
  52
  53 inline Cycles
  54 handleIprRead(ThreadContext *tc, Packet *pkt)
  55 {
  56     Addr addr = pkt->getAddr();
  57     auto m5opRange = tc->getSystemPtr()->m5opRange();
  58     if (m5opRange.contains(addr)) {
  59         uint8_t func;
  60         PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
  61         uint64_t ret = PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
  62         pkt->setLE(ret);
  63     }
  64     return Cycles(1);
  65 }
  66
  67 inline Cycles
  68 handleIprWrite(ThreadContext *tc, Packet *pkt)
  69 {
  70     Addr addr = pkt->getAddr();
  71     auto m5opRange = tc->getSystemPtr()->m5opRange();
  72     if (m5opRange.contains(addr)) {
  73         uint8_t func;
  74         PseudoInst::decodeAddrOffset(addr - m5opRange.start(), func);
  75         PseudoInst::pseudoInst<PseudoInstABI>(tc, func);
  76     }
  77     return Cycles(1);
  78 }
  79
  80 } // namespace ArmISA
  81
  82 #endif