src/arch/arm/mmu.hh

   1 /*
   2  * Copyright (c) 2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __ARCH_ARM_MMU_HH__
  39 #define __ARCH_ARM_MMU_HH__
  40
  41 #include "arch/arm/tlb.hh"
  42 #include "arch/generic/mmu.hh"
  43
  44 #include "params/ArmMMU.hh"
  45
  46 namespace ArmISA {
  47
  48 class MMU : public BaseMMU
  49 {
  50   protected:
  51     ArmISA::TLB *
  52     getDTBPtr() const
  53     {
  54         return static_cast<ArmISA::TLB *>(dtb);
  55     }
  56
  57     ArmISA::TLB *
  58     getITBPtr() const
  59     {
  60         return static_cast<ArmISA::TLB *>(itb);
  61     }
  62
  63   public:
  64     enum TLBType
  65     {
  66         I_TLBS = 0x01,
  67         D_TLBS = 0x10,
  68         ALL_TLBS = 0x11
  69     };
  70
  71     MMU(const ArmMMUParams &p)
  72       : BaseMMU(p)
  73     {}
  74
  75     bool translateFunctional(ThreadContext *tc, Addr vaddr, Addr &paddr);
  76
  77     Fault translateFunctional(const RequestPtr &req, ThreadContext *tc,
  78         BaseTLB::Mode mode, TLB::ArmTranslationType tran_type);
  79
  80     void invalidateMiscReg(TLBType type = ALL_TLBS);
  81
  82     template <typename OP>
  83     void
  84     flush(const OP &tlbi_op)
  85     {
  86         getITBPtr()->flush(tlbi_op);
  87         getDTBPtr()->flush(tlbi_op);
  88     }
  89
  90     template <typename OP>
  91     void
  92     iflush(const OP &tlbi_op)
  93     {
  94         getITBPtr()->flush(tlbi_op);
  95     }
  96
  97     template <typename OP>
  98     void
  99     dflush(const OP &tlbi_op)
 100     {
 101         getDTBPtr()->flush(tlbi_op);
 102     }
 103
 104     uint64_t
 105     getAttr() const
 106     {
 107         return getDTBPtr()->getAttr();
 108     }
 109 };
 110
 111 template<typename T>
 112 MMU *
 113 getMMUPtr(T *tc)
 114 {
 115     auto mmu = static_cast<MMU *>(tc->getMMUPtr());
 116     assert(mmu);
 117     return mmu;
 118 }
 119
 120
 121 } // namespace ArmISA
 122
 123 #endif // __ARCH_ARM_MMU_HH__