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31 #include "arch/arm/isa_traits.hh"
32 #include "arch/arm/miscregs.hh"
33 #include "arch/arm/nativetrace.hh"
34 #include "cpu/thread_context.hh"
35 #include "params/ArmNativeTrace.hh"
40 static const char *regNames
[] = {
41 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
42 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
48 Trace::ArmNativeTrace::ThreadState::update(NativeTrace
*parent
)
50 oldState
= state
[current
];
51 current
= (current
+ 1) % 2;
52 newState
= state
[current
];
54 memcpy(newState
, oldState
, sizeof(state
[0]));
57 parent
->read(&diffVector
, sizeof(diffVector
));
58 diffVector
= ArmISA::gtoh(diffVector
);
61 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
62 if (diffVector
& 0x1) {
71 uint32_t values
[changes
];
72 parent
->read(values
, sizeof(values
));
74 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
76 newState
[i
] = ArmISA::gtoh(values
[pos
++]);
77 changed
[i
] = (newState
[i
] != oldState
[i
]);
83 Trace::ArmNativeTrace::ThreadState::update(ThreadContext
*tc
)
85 oldState
= state
[current
];
86 current
= (current
+ 1) % 2;
87 newState
= state
[current
];
90 for (int i
= 0; i
< 15; i
++) {
91 newState
[i
] = tc
->readIntReg(i
);
92 changed
[i
] = (oldState
[i
] != newState
[i
]);
95 //R15, aliased with the PC
96 newState
[STATE_PC
] = tc
->readNextPC();
97 changed
[STATE_PC
] = (newState
[STATE_PC
] != oldState
[STATE_PC
]);
100 newState
[STATE_CPSR
] = tc
->readMiscReg(MISCREG_CPSR
);
101 changed
[STATE_CPSR
] = (newState
[STATE_CPSR
] != oldState
[STATE_CPSR
]);
105 Trace::ArmNativeTrace::check(NativeTraceRecord
*record
)
107 ThreadContext
*tc
= record
->getThread();
108 // This area is read only on the target. It can't stop there to tell us
109 // what's going on, so we should skip over anything there also.
110 if (tc
->readNextPC() > 0xffff0000)
115 bool errorFound
= false;
117 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
118 if (nState
.changed
[i
] || mState
.changed
[i
]) {
119 const char *vergence
= " ";
120 bool oldMatch
= (mState
.oldState
[i
] == nState
.oldState
[i
]);
121 bool newMatch
= (mState
.newState
[i
] == nState
.newState
[i
]);
122 if (oldMatch
&& newMatch
) {
123 // The more things change, the more they stay the same.
125 } else if (oldMatch
&& !newMatch
) {
127 } else if (!oldMatch
&& newMatch
) {
131 if (!nState
.changed
[i
]) {
132 DPRINTF(ExecRegDelta
, "%s [%5s] "\
134 "M5: %#010x => %#010x\n",
135 vergence
, regNames
[i
],
137 mState
.oldState
[i
], mState
.newState
[i
]);
138 } else if (!mState
.changed
[i
]) {
139 DPRINTF(ExecRegDelta
, "%s [%5s] "\
140 "Native: %#010x => %#010x "\
142 vergence
, regNames
[i
],
143 nState
.oldState
[i
], nState
.newState
[i
],
146 DPRINTF(ExecRegDelta
, "%s [%5s] "\
147 "Native: %#010x => %#010x "\
148 "M5: %#010x => %#010x\n",
149 vergence
, regNames
[i
],
150 nState
.oldState
[i
], nState
.newState
[i
],
151 mState
.oldState
[i
], mState
.newState
[i
]);
156 StaticInstPtr inst
= record
->getStaticInst();
159 if (inst
->isMicroop()) {
161 inst
= record
->getMacroStaticInst();
164 record
->traceInst(inst
, ran
);
166 bool pcError
= (mState
.newState
[STATE_PC
] !=
167 nState
.newState
[STATE_PC
]);
168 if (stopOnPCError
&& pcError
)
169 panic("Native trace detected an error in control flow!");
173 } /* namespace Trace */
175 ////////////////////////////////////////////////////////////////////////
177 // ExeTracer Simulation Object
179 Trace::ArmNativeTrace
*
180 ArmNativeTraceParams::create()
182 return new Trace::ArmNativeTrace(this);