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43 #include "arch/arm/isa_traits.hh"
44 #include "arch/arm/miscregs.hh"
45 #include "arch/arm/nativetrace.hh"
46 #include "cpu/thread_context.hh"
47 #include "debug/ExecRegDelta.hh"
48 #include "params/ArmNativeTrace.hh"
49 #include "sim/byteswap.hh"
54 static const char *regNames
[] = {
55 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
56 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
57 "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
58 "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
59 "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
60 "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
66 Trace::ArmNativeTrace::ThreadState::update(NativeTrace
*parent
)
68 oldState
= state
[current
];
69 current
= (current
+ 1) % 2;
70 newState
= state
[current
];
72 memcpy(newState
, oldState
, sizeof(state
[0]));
75 parent
->read(&diffVector
, sizeof(diffVector
));
76 diffVector
= ArmISA::gtoh(diffVector
);
79 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
80 if (diffVector
& 0x1) {
89 uint64_t values
[changes
];
90 parent
->read(values
, sizeof(values
));
92 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
94 newState
[i
] = ArmISA::gtoh(values
[pos
++]);
95 changed
[i
] = (newState
[i
] != oldState
[i
]);
101 Trace::ArmNativeTrace::ThreadState::update(ThreadContext
*tc
)
103 oldState
= state
[current
];
104 current
= (current
+ 1) % 2;
105 newState
= state
[current
];
108 for (int i
= 0; i
< 15; i
++) {
109 newState
[i
] = tc
->readIntReg(i
);
110 changed
[i
] = (oldState
[i
] != newState
[i
]);
113 //R15, aliased with the PC
114 newState
[STATE_PC
] = tc
->pcState().npc();
115 changed
[STATE_PC
] = (newState
[STATE_PC
] != oldState
[STATE_PC
]);
118 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
119 cpsr
.nz
= tc
->readIntReg(INTREG_CONDCODES_NZ
);
120 cpsr
.c
= tc
->readIntReg(INTREG_CONDCODES_C
);
121 cpsr
.v
= tc
->readIntReg(INTREG_CONDCODES_V
);
122 cpsr
.ge
= tc
->readIntReg(INTREG_CONDCODES_GE
);
124 newState
[STATE_CPSR
] = cpsr
;
125 changed
[STATE_CPSR
] = (newState
[STATE_CPSR
] != oldState
[STATE_CPSR
]);
127 for (int i
= 0; i
< NumFloatArchRegs
; i
+= 2) {
128 newState
[STATE_F0
+ (i
>> 1)] =
129 static_cast<uint64_t>(tc
->readFloatRegBits(i
+ 1)) << 32 |
130 tc
->readFloatRegBits(i
);
132 newState
[STATE_FPSCR
] = tc
->readMiscRegNoEffect(MISCREG_FPSCR
) |
133 tc
->readIntReg(INTREG_FPCONDCODES
);
137 Trace::ArmNativeTrace::check(NativeTraceRecord
*record
)
139 ThreadContext
*tc
= record
->getThread();
140 // This area is read only on the target. It can't stop there to tell us
141 // what's going on, so we should skip over anything there also.
142 if (tc
->nextInstAddr() > 0xffff0000)
147 // If a syscall just happened native trace needs another tick
148 if ((mState
.oldState
[STATE_PC
] == nState
.oldState
[STATE_PC
]) &&
149 (mState
.newState
[STATE_PC
] - 4 == nState
.newState
[STATE_PC
])) {
150 DPRINTF(ExecRegDelta
, "Advancing to match PCs after syscall\n");
155 bool errorFound
= false;
157 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
158 if (nState
.changed
[i
] || mState
.changed
[i
]) {
159 bool oldMatch
= (mState
.oldState
[i
] == nState
.oldState
[i
]);
160 bool newMatch
= (mState
.newState
[i
] == nState
.newState
[i
]);
161 if (oldMatch
&& newMatch
) {
162 // The more things change, the more they stay the same.
169 const char *vergence
= " ";
170 if (oldMatch
&& !newMatch
) {
172 } else if (!oldMatch
&& newMatch
) {
176 if (!nState
.changed
[i
]) {
177 DPRINTF(ExecRegDelta
, "%s [%5s] "\
179 "M5: %#010x => %#010x\n",
180 vergence
, regNames
[i
],
182 mState
.oldState
[i
], mState
.newState
[i
]);
183 } else if (!mState
.changed
[i
]) {
184 DPRINTF(ExecRegDelta
, "%s [%5s] "\
185 "Native: %#010x => %#010x "\
187 vergence
, regNames
[i
],
188 nState
.oldState
[i
], nState
.newState
[i
],
191 DPRINTF(ExecRegDelta
, "%s [%5s] "\
192 "Native: %#010x => %#010x "\
193 "M5: %#010x => %#010x\n",
194 vergence
, regNames
[i
],
195 nState
.oldState
[i
], nState
.newState
[i
],
196 mState
.oldState
[i
], mState
.newState
[i
]);
202 StaticInstPtr inst
= record
->getStaticInst();
205 if (inst
->isMicroop()) {
207 inst
= record
->getMacroStaticInst();
210 record
->traceInst(inst
, ran
);
212 bool pcError
= (mState
.newState
[STATE_PC
] !=
213 nState
.newState
[STATE_PC
]);
214 if (stopOnPCError
&& pcError
)
215 panic("Native trace detected an error in control flow!");
221 ////////////////////////////////////////////////////////////////////////
223 // ExeTracer Simulation Object
225 Trace::ArmNativeTrace
*
226 ArmNativeTraceParams::create()
228 return new Trace::ArmNativeTrace(this);