src/arch/arm/nativetrace.cc

   1 /*
   2  * Copyright (c) 2010-2011, 2014, 2016-2017 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42
  43 #include "arch/arm/nativetrace.hh"
  44
  45 #include "arch/arm/isa_traits.hh"
  46 #include "arch/arm/miscregs.hh"
  47 #include "cpu/thread_context.hh"
  48 #include "debug/ExecRegDelta.hh"
  49 #include "params/ArmNativeTrace.hh"
  50 #include "sim/byteswap.hh"
  51
  52 namespace Trace {
  53
  54 #if TRACING_ON
  55 static const char *regNames[] = {
  56     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  57     "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
  58     "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
  59     "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
  60     "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
  61     "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
  62     "f31", "fpscr"
  63 };
  64 #endif
  65
  66 void
  67 Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
  68 {
  69     oldState = state[current];
  70     current = (current + 1) % 2;
  71     newState = state[current];
  72
  73     memcpy(newState, oldState, sizeof(state[0]));
  74
  75     uint64_t diffVector;
  76     parent->read(&diffVector, sizeof(diffVector));
  77     diffVector = letoh(diffVector);
  78
  79     int changes = 0;
  80     for (int i = 0; i < STATE_NUMVALS; i++) {
  81         if (diffVector & 0x1) {
  82             changed[i] = true;
  83             changes++;
  84         } else {
  85             changed[i] = false;
  86         }
  87         diffVector >>= 1;
  88     }
  89
  90     uint64_t values[changes];
  91     parent->read(values, sizeof(values));
  92     int pos = 0;
  93     for (int i = 0; i < STATE_NUMVALS; i++) {
  94         if (changed[i]) {
  95             newState[i] = letoh(values[pos++]);
  96             changed[i] = (newState[i] != oldState[i]);
  97         }
  98     }
  99 }
 100
 101 void
 102 Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
 103 {
 104     oldState = state[current];
 105     current = (current + 1) % 2;
 106     newState = state[current];
 107
 108     // Regular int regs
 109     for (int i = 0; i < 15; i++) {
 110         newState[i] = tc->readIntReg(i);
 111         changed[i] = (oldState[i] != newState[i]);
 112     }
 113
 114     //R15, aliased with the PC
 115     newState[STATE_PC] = tc->pcState().npc();
 116     changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
 117
 118     //CPSR
 119     CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 120     cpsr.nz = tc->readCCReg(CCREG_NZ);
 121     cpsr.c = tc->readCCReg(CCREG_C);
 122     cpsr.v = tc->readCCReg(CCREG_V);
 123     cpsr.ge = tc->readCCReg(CCREG_GE);
 124
 125     newState[STATE_CPSR] = cpsr;
 126     changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
 127
 128     for (int i = 0; i < NumVecV7ArchRegs; i++) {
 129         auto vec(tc->readVecReg(RegId(VecRegClass,i))
 130             .as<uint64_t, MaxSveVecLenInDWords>());
 131         newState[STATE_F0 + 2*i] = vec[0];
 132         newState[STATE_F0 + 2*i + 1] = vec[1];
 133     }
 134     newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
 135                             tc->readCCReg(CCREG_FP);
 136 }
 137
 138 void
 139 Trace::ArmNativeTrace::check(NativeTraceRecord *record)
 140 {
 141     ThreadContext *tc = record->getThread();
 142     // This area is read only on the target. It can't stop there to tell us
 143     // what's going on, so we should skip over anything there also.
 144     if (tc->nextInstAddr() > 0xffff0000)
 145         return;
 146     nState.update(this);
 147     mState.update(tc);
 148
 149     // If a syscall just happened native trace needs another tick
 150     if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
 151             (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
 152             DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
 153             nState.update(this);
 154
 155     }
 156
 157     bool errorFound = false;
 158     // Regular int regs
 159     for (int i = 0; i < STATE_NUMVALS; i++) {
 160         if (nState.changed[i] || mState.changed[i]) {
 161             bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
 162             bool newMatch = (mState.newState[i] == nState.newState[i]);
 163             if (oldMatch && newMatch) {
 164                 // The more things change, the more they stay the same.
 165                 continue;
 166             }
 167
 168             errorFound = true;
 169
 170 #ifndef NDEBUG
 171             const char *vergence = "  ";
 172             if (oldMatch && !newMatch) {
 173                 vergence = "<>";
 174             } else if (!oldMatch && newMatch) {
 175                 vergence = "><";
 176             }
 177
 178             if (!nState.changed[i]) {
 179                 DPRINTF(ExecRegDelta, "%s [%5s] "\
 180                                       "Native:         %#010x         "\
 181                                       "M5:     %#010x => %#010x\n",
 182                                       vergence, regNames[i],
 183                                       nState.newState[i],
 184                                       mState.oldState[i], mState.newState[i]);
 185             } else if (!mState.changed[i]) {
 186                 DPRINTF(ExecRegDelta, "%s [%5s] "\
 187                                       "Native: %#010x => %#010x "\
 188                                       "M5:             %#010x        \n",
 189                                       vergence, regNames[i],
 190                                       nState.oldState[i], nState.newState[i],
 191                                       mState.newState[i]);
 192             } else {
 193                 DPRINTF(ExecRegDelta, "%s [%5s] "\
 194                                       "Native: %#010x => %#010x "\
 195                                       "M5:     %#010x => %#010x\n",
 196                                       vergence, regNames[i],
 197                                       nState.oldState[i], nState.newState[i],
 198                                       mState.oldState[i], mState.newState[i]);
 199             }
 200 #endif
 201         }
 202     }
 203     if (errorFound) {
 204         StaticInstPtr inst = record->getStaticInst();
 205         assert(inst);
 206         bool ran = true;
 207         if (inst->isMicroop()) {
 208             ran = false;
 209             inst = record->getMacroStaticInst();
 210         }
 211         assert(inst);
 212         record->traceInst(inst, ran);
 213
 214         bool pcError = (mState.newState[STATE_PC] !=
 215                         nState.newState[STATE_PC]);
 216         if (stopOnPCError && pcError)
 217             panic("Native trace detected an error in control flow!");
 218     }
 219 }
 220
 221 } // namespace Trace
 222
 223 ////////////////////////////////////////////////////////////////////////
 224 //
 225 //  ExeTracer Simulation Object
 226 //
 227 Trace::ArmNativeTrace *
 228 ArmNativeTraceParams::create()
 229 {
 230     return new Trace::ArmNativeTrace(this);
 231 }