src/arch/arm/nativetrace.cc

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42
  43 #include "arch/arm/isa_traits.hh"
  44 #include "arch/arm/miscregs.hh"
  45 #include "arch/arm/nativetrace.hh"
  46 #include "cpu/thread_context.hh"
  47 #include "debug/ExecRegDelta.hh"
  48 #include "params/ArmNativeTrace.hh"
  49 #include "sim/byteswap.hh"
  50
  51 namespace Trace {
  52
  53 #if TRACING_ON
  54 static const char *regNames[] = {
  55     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  56     "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
  57     "cpsr"
  58 };
  59 #endif
  60
  61 void
  62 Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
  63 {
  64     oldState = state[current];
  65     current = (current + 1) % 2;
  66     newState = state[current];
  67
  68     memcpy(newState, oldState, sizeof(state[0]));
  69
  70     uint32_t diffVector;
  71     parent->read(&diffVector, sizeof(diffVector));
  72     diffVector = ArmISA::gtoh(diffVector);
  73
  74     int changes = 0;
  75     for (int i = 0; i < STATE_NUMVALS; i++) {
  76         if (diffVector & 0x1) {
  77             changed[i] = true;
  78             changes++;
  79         } else {
  80             changed[i] = false;
  81         }
  82         diffVector >>= 1;
  83     }
  84
  85     uint32_t values[changes];
  86     parent->read(values, sizeof(values));
  87     int pos = 0;
  88     for (int i = 0; i < STATE_NUMVALS; i++) {
  89         if (changed[i]) {
  90             newState[i] = ArmISA::gtoh(values[pos++]);
  91             changed[i] = (newState[i] != oldState[i]);
  92         }
  93     }
  94 }
  95
  96 void
  97 Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
  98 {
  99     oldState = state[current];
 100     current = (current + 1) % 2;
 101     newState = state[current];
 102
 103     // Regular int regs
 104     for (int i = 0; i < 15; i++) {
 105         newState[i] = tc->readIntReg(i);
 106         changed[i] = (oldState[i] != newState[i]);
 107     }
 108
 109     //R15, aliased with the PC
 110     newState[STATE_PC] = tc->pcState().npc();
 111     changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
 112
 113     //CPSR
 114     newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) |
 115                            tc->readIntReg(INTREG_CONDCODES);
 116     changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
 117 }
 118
 119 void
 120 Trace::ArmNativeTrace::check(NativeTraceRecord *record)
 121 {
 122     ThreadContext *tc = record->getThread();
 123     // This area is read only on the target. It can't stop there to tell us
 124     // what's going on, so we should skip over anything there also.
 125     if (tc->nextInstAddr() > 0xffff0000)
 126         return;
 127     nState.update(this);
 128     mState.update(tc);
 129
 130     // If a syscall just happened native trace needs another tick
 131     if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
 132             (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
 133             DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
 134             nState.update(this);
 135
 136     }
 137
 138     bool errorFound = false;
 139     // Regular int regs
 140     for (int i = 0; i < STATE_NUMVALS; i++) {
 141         if (nState.changed[i] || mState.changed[i]) {
 142             const char *vergence = "  ";
 143             bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
 144             bool newMatch = (mState.newState[i] == nState.newState[i]);
 145             if (oldMatch && newMatch) {
 146                 // The more things change, the more they stay the same.
 147                 continue;
 148             } else if (oldMatch && !newMatch) {
 149                 vergence = "<>";
 150             } else if (!oldMatch && newMatch) {
 151                 vergence = "><";
 152             }
 153             errorFound = true;
 154             if (!nState.changed[i]) {
 155                 DPRINTF(ExecRegDelta, "%s [%5s] "\
 156                                       "Native:         %#010x         "\
 157                                       "M5:     %#010x => %#010x\n",
 158                                       vergence, regNames[i],
 159                                       nState.newState[i],
 160                                       mState.oldState[i], mState.newState[i]);
 161             } else if (!mState.changed[i]) {
 162                 DPRINTF(ExecRegDelta, "%s [%5s] "\
 163                                       "Native: %#010x => %#010x "\
 164                                       "M5:             %#010x        \n",
 165                                       vergence, regNames[i],
 166                                       nState.oldState[i], nState.newState[i],
 167                                       mState.newState[i]);
 168             } else {
 169                 DPRINTF(ExecRegDelta, "%s [%5s] "\
 170                                       "Native: %#010x => %#010x "\
 171                                       "M5:     %#010x => %#010x\n",
 172                                       vergence, regNames[i],
 173                                       nState.oldState[i], nState.newState[i],
 174                                       mState.oldState[i], mState.newState[i]);
 175             }
 176         }
 177     }
 178     if (errorFound) {
 179         StaticInstPtr inst = record->getStaticInst();
 180         assert(inst);
 181         bool ran = true;
 182         if (inst->isMicroop()) {
 183             ran = false;
 184             inst = record->getMacroStaticInst();
 185         }
 186         assert(inst);
 187         record->traceInst(inst, ran);
 188
 189         bool pcError = (mState.newState[STATE_PC] !=
 190                         nState.newState[STATE_PC]);
 191         if (stopOnPCError && pcError)
 192             panic("Native trace detected an error in control flow!");
 193     }
 194 }
 195
 196 } // namespace Trace
 197
 198 ////////////////////////////////////////////////////////////////////////
 199 //
 200 //  ExeTracer Simulation Object
 201 //
 202 Trace::ArmNativeTrace *
 203 ArmNativeTraceParams::create()
 204 {
 205     return new Trace::ArmNativeTrace(this);
 206 };