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41 #include "arch/arm/nativetrace.hh"
43 #include "arch/arm/isa_traits.hh"
44 #include "arch/arm/miscregs.hh"
45 #include "cpu/thread_context.hh"
46 #include "debug/ExecRegDelta.hh"
47 #include "params/ArmNativeTrace.hh"
48 #include "sim/byteswap.hh"
50 using namespace ArmISA
;
55 static const char *regNames
[] = {
56 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
57 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
58 "cpsr", "f0", "f1", "f2", "f3", "f4", "f5", "f6",
59 "f7", "f8", "f9", "f10", "f11", "f12", "f13", "f14",
60 "f15", "f16", "f17", "f18", "f19", "f20", "f21", "f22",
61 "f23", "f24", "f25", "f26", "f27", "f28", "f29", "f30",
67 Trace::ArmNativeTrace::ThreadState::update(NativeTrace
*parent
)
69 oldState
= state
[current
];
70 current
= (current
+ 1) % 2;
71 newState
= state
[current
];
73 memcpy(newState
, oldState
, sizeof(state
[0]));
76 parent
->read(&diffVector
, sizeof(diffVector
));
77 diffVector
= letoh(diffVector
);
80 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
81 if (diffVector
& 0x1) {
90 uint64_t values
[changes
];
91 parent
->read(values
, sizeof(values
));
93 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
95 newState
[i
] = letoh(values
[pos
++]);
96 changed
[i
] = (newState
[i
] != oldState
[i
]);
102 Trace::ArmNativeTrace::ThreadState::update(ThreadContext
*tc
)
104 oldState
= state
[current
];
105 current
= (current
+ 1) % 2;
106 newState
= state
[current
];
109 for (int i
= 0; i
< 15; i
++) {
110 newState
[i
] = tc
->readIntReg(i
);
111 changed
[i
] = (oldState
[i
] != newState
[i
]);
114 //R15, aliased with the PC
115 newState
[STATE_PC
] = tc
->pcState().npc();
116 changed
[STATE_PC
] = (newState
[STATE_PC
] != oldState
[STATE_PC
]);
119 CPSR cpsr
= tc
->readMiscReg(MISCREG_CPSR
);
120 cpsr
.nz
= tc
->readCCReg(CCREG_NZ
);
121 cpsr
.c
= tc
->readCCReg(CCREG_C
);
122 cpsr
.v
= tc
->readCCReg(CCREG_V
);
123 cpsr
.ge
= tc
->readCCReg(CCREG_GE
);
125 newState
[STATE_CPSR
] = cpsr
;
126 changed
[STATE_CPSR
] = (newState
[STATE_CPSR
] != oldState
[STATE_CPSR
]);
128 for (int i
= 0; i
< NumVecV7ArchRegs
; i
++) {
129 auto vec(tc
->readVecReg(RegId(VecRegClass
,i
))
130 .as
<uint64_t, MaxSveVecLenInDWords
>());
131 newState
[STATE_F0
+ 2*i
] = vec
[0];
132 newState
[STATE_F0
+ 2*i
+ 1] = vec
[1];
134 newState
[STATE_FPSCR
] = tc
->readMiscRegNoEffect(MISCREG_FPSCR
) |
135 tc
->readCCReg(CCREG_FP
);
139 Trace::ArmNativeTrace::check(NativeTraceRecord
*record
)
141 ThreadContext
*tc
= record
->getThread();
142 // This area is read only on the target. It can't stop there to tell us
143 // what's going on, so we should skip over anything there also.
144 if (tc
->nextInstAddr() > 0xffff0000)
149 // If a syscall just happened native trace needs another tick
150 if ((mState
.oldState
[STATE_PC
] == nState
.oldState
[STATE_PC
]) &&
151 (mState
.newState
[STATE_PC
] - 4 == nState
.newState
[STATE_PC
])) {
152 DPRINTF(ExecRegDelta
, "Advancing to match PCs after syscall\n");
157 bool errorFound
= false;
159 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
160 if (nState
.changed
[i
] || mState
.changed
[i
]) {
161 bool oldMatch
= (mState
.oldState
[i
] == nState
.oldState
[i
]);
162 bool newMatch
= (mState
.newState
[i
] == nState
.newState
[i
]);
163 if (oldMatch
&& newMatch
) {
164 // The more things change, the more they stay the same.
171 const char *vergence
= " ";
172 if (oldMatch
&& !newMatch
) {
174 } else if (!oldMatch
&& newMatch
) {
178 if (!nState
.changed
[i
]) {
179 DPRINTF(ExecRegDelta
, "%s [%5s] "\
181 "M5: %#010x => %#010x\n",
182 vergence
, regNames
[i
],
184 mState
.oldState
[i
], mState
.newState
[i
]);
185 } else if (!mState
.changed
[i
]) {
186 DPRINTF(ExecRegDelta
, "%s [%5s] "\
187 "Native: %#010x => %#010x "\
189 vergence
, regNames
[i
],
190 nState
.oldState
[i
], nState
.newState
[i
],
193 DPRINTF(ExecRegDelta
, "%s [%5s] "\
194 "Native: %#010x => %#010x "\
195 "M5: %#010x => %#010x\n",
196 vergence
, regNames
[i
],
197 nState
.oldState
[i
], nState
.newState
[i
],
198 mState
.oldState
[i
], mState
.newState
[i
]);
204 StaticInstPtr inst
= record
->getStaticInst();
207 if (inst
->isMicroop()) {
209 inst
= record
->getMacroStaticInst();
212 record
->traceInst(inst
, ran
);
214 bool pcError
= (mState
.newState
[STATE_PC
] !=
215 nState
.newState
[STATE_PC
]);
216 if (stopOnPCError
&& pcError
)
217 panic("Native trace detected an error in control flow!");