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43 #include "arch/arm/isa_traits.hh"
44 #include "arch/arm/miscregs.hh"
45 #include "arch/arm/nativetrace.hh"
46 #include "cpu/thread_context.hh"
47 #include "params/ArmNativeTrace.hh"
48 #include "sim/byteswap.hh"
53 static const char *regNames
[] = {
54 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
55 "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
61 Trace::ArmNativeTrace::ThreadState::update(NativeTrace
*parent
)
63 oldState
= state
[current
];
64 current
= (current
+ 1) % 2;
65 newState
= state
[current
];
67 memcpy(newState
, oldState
, sizeof(state
[0]));
70 parent
->read(&diffVector
, sizeof(diffVector
));
71 diffVector
= ArmISA::gtoh(diffVector
);
74 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
75 if (diffVector
& 0x1) {
84 uint32_t values
[changes
];
85 parent
->read(values
, sizeof(values
));
87 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
89 newState
[i
] = ArmISA::gtoh(values
[pos
++]);
90 changed
[i
] = (newState
[i
] != oldState
[i
]);
96 Trace::ArmNativeTrace::ThreadState::update(ThreadContext
*tc
)
98 oldState
= state
[current
];
99 current
= (current
+ 1) % 2;
100 newState
= state
[current
];
103 for (int i
= 0; i
< 15; i
++) {
104 newState
[i
] = tc
->readIntReg(i
);
105 changed
[i
] = (oldState
[i
] != newState
[i
]);
108 //R15, aliased with the PC
109 newState
[STATE_PC
] = tc
->readNextPC();
110 changed
[STATE_PC
] = (newState
[STATE_PC
] != oldState
[STATE_PC
]);
113 newState
[STATE_CPSR
] = tc
->readMiscReg(MISCREG_CPSR
) |
114 tc
->readIntReg(INTREG_CONDCODES
);
115 changed
[STATE_CPSR
] = (newState
[STATE_CPSR
] != oldState
[STATE_CPSR
]);
119 Trace::ArmNativeTrace::check(NativeTraceRecord
*record
)
121 ThreadContext
*tc
= record
->getThread();
122 // This area is read only on the target. It can't stop there to tell us
123 // what's going on, so we should skip over anything there also.
124 if (tc
->readNextPC() > 0xffff0000)
129 // If a syscall just happened native trace needs another tick
130 if ((mState
.oldState
[STATE_PC
] == nState
.oldState
[STATE_PC
]) &&
131 (mState
.newState
[STATE_PC
] - 4 == nState
.newState
[STATE_PC
])) {
132 DPRINTF(ExecRegDelta
, "Advancing to match PCs after syscall\n");
137 bool errorFound
= false;
139 for (int i
= 0; i
< STATE_NUMVALS
; i
++) {
140 if (nState
.changed
[i
] || mState
.changed
[i
]) {
141 const char *vergence
= " ";
142 bool oldMatch
= (mState
.oldState
[i
] == nState
.oldState
[i
]);
143 bool newMatch
= (mState
.newState
[i
] == nState
.newState
[i
]);
144 if (oldMatch
&& newMatch
) {
145 // The more things change, the more they stay the same.
147 } else if (oldMatch
&& !newMatch
) {
149 } else if (!oldMatch
&& newMatch
) {
153 if (!nState
.changed
[i
]) {
154 DPRINTF(ExecRegDelta
, "%s [%5s] "\
156 "M5: %#010x => %#010x\n",
157 vergence
, regNames
[i
],
159 mState
.oldState
[i
], mState
.newState
[i
]);
160 } else if (!mState
.changed
[i
]) {
161 DPRINTF(ExecRegDelta
, "%s [%5s] "\
162 "Native: %#010x => %#010x "\
164 vergence
, regNames
[i
],
165 nState
.oldState
[i
], nState
.newState
[i
],
168 DPRINTF(ExecRegDelta
, "%s [%5s] "\
169 "Native: %#010x => %#010x "\
170 "M5: %#010x => %#010x\n",
171 vergence
, regNames
[i
],
172 nState
.oldState
[i
], nState
.newState
[i
],
173 mState
.oldState
[i
], mState
.newState
[i
]);
178 StaticInstPtr inst
= record
->getStaticInst();
181 if (inst
->isMicroop()) {
183 inst
= record
->getMacroStaticInst();
186 record
->traceInst(inst
, ran
);
188 bool pcError
= (mState
.newState
[STATE_PC
] !=
189 nState
.newState
[STATE_PC
]);
190 if (stopOnPCError
&& pcError
)
191 panic("Native trace detected an error in control flow!");
195 } /* namespace Trace */
197 ////////////////////////////////////////////////////////////////////////
199 // ExeTracer Simulation Object
201 Trace::ArmNativeTrace
*
202 ArmNativeTraceParams::create()
204 return new Trace::ArmNativeTrace(this);