src/arch/arm/nativetrace.cc

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Gabe Black
  41  */
  42
  43 #include "arch/arm/isa_traits.hh"
  44 #include "arch/arm/miscregs.hh"
  45 #include "arch/arm/nativetrace.hh"
  46 #include "cpu/thread_context.hh"
  47 #include "params/ArmNativeTrace.hh"
  48
  49 namespace Trace {
  50
  51 #if TRACING_ON
  52 static const char *regNames[] = {
  53     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  54     "r8", "r9", "r10", "fp", "r12", "sp", "lr", "pc",
  55     "cpsr"
  56 };
  57 #endif
  58
  59 void
  60 Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
  61 {
  62     oldState = state[current];
  63     current = (current + 1) % 2;
  64     newState = state[current];
  65
  66     memcpy(newState, oldState, sizeof(state[0]));
  67
  68     uint32_t diffVector;
  69     parent->read(&diffVector, sizeof(diffVector));
  70     diffVector = ArmISA::gtoh(diffVector);
  71
  72     int changes = 0;
  73     for (int i = 0; i < STATE_NUMVALS; i++) {
  74         if (diffVector & 0x1) {
  75             changed[i] = true;
  76             changes++;
  77         } else {
  78             changed[i] = false;
  79         }
  80         diffVector >>= 1;
  81     }
  82
  83     uint32_t values[changes];
  84     parent->read(values, sizeof(values));
  85     int pos = 0;
  86     for (int i = 0; i < STATE_NUMVALS; i++) {
  87         if (changed[i]) {
  88             newState[i] = ArmISA::gtoh(values[pos++]);
  89             changed[i] = (newState[i] != oldState[i]);
  90         }
  91     }
  92 }
  93
  94 void
  95 Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
  96 {
  97     oldState = state[current];
  98     current = (current + 1) % 2;
  99     newState = state[current];
 100
 101     // Regular int regs
 102     for (int i = 0; i < 15; i++) {
 103         newState[i] = tc->readIntReg(i);
 104         changed[i] = (oldState[i] != newState[i]);
 105     }
 106
 107     //R15, aliased with the PC
 108     newState[STATE_PC] = tc->readNextPC();
 109     changed[STATE_PC] = (newState[STATE_PC] != oldState[STATE_PC]);
 110
 111     //CPSR
 112     newState[STATE_CPSR] = tc->readMiscReg(MISCREG_CPSR) |
 113                            tc->readIntReg(INTREG_CONDCODES);
 114     changed[STATE_CPSR] = (newState[STATE_CPSR] != oldState[STATE_CPSR]);
 115 }
 116
 117 void
 118 Trace::ArmNativeTrace::check(NativeTraceRecord *record)
 119 {
 120     ThreadContext *tc = record->getThread();
 121     // This area is read only on the target. It can't stop there to tell us
 122     // what's going on, so we should skip over anything there also.
 123     if (tc->readNextPC() > 0xffff0000)
 124         return;
 125     nState.update(this);
 126     mState.update(tc);
 127
 128     // If a syscall just happened native trace needs another tick
 129     if ((mState.oldState[STATE_PC] == nState.oldState[STATE_PC]) &&
 130             (mState.newState[STATE_PC] - 4 == nState.newState[STATE_PC])) {
 131             DPRINTF(ExecRegDelta, "Advancing to match PCs after syscall\n");
 132             nState.update(this);
 133
 134     }
 135
 136     bool errorFound = false;
 137     // Regular int regs
 138     for (int i = 0; i < STATE_NUMVALS; i++) {
 139         if (nState.changed[i] || mState.changed[i]) {
 140             const char *vergence = "  ";
 141             bool oldMatch = (mState.oldState[i] == nState.oldState[i]);
 142             bool newMatch = (mState.newState[i] == nState.newState[i]);
 143             if (oldMatch && newMatch) {
 144                 // The more things change, the more they stay the same.
 145                 continue;
 146             } else if (oldMatch && !newMatch) {
 147                 vergence = "<>";
 148             } else if (!oldMatch && newMatch) {
 149                 vergence = "><";
 150             }
 151             errorFound = true;
 152             if (!nState.changed[i]) {
 153                 DPRINTF(ExecRegDelta, "%s [%5s] "\
 154                                       "Native:         %#010x         "\
 155                                       "M5:     %#010x => %#010x\n",
 156                                       vergence, regNames[i],
 157                                       nState.newState[i],
 158                                       mState.oldState[i], mState.newState[i]);
 159             } else if (!mState.changed[i]) {
 160                 DPRINTF(ExecRegDelta, "%s [%5s] "\
 161                                       "Native: %#010x => %#010x "\
 162                                       "M5:             %#010x        \n",
 163                                       vergence, regNames[i],
 164                                       nState.oldState[i], nState.newState[i],
 165                                       mState.newState[i]);
 166             } else {
 167                 DPRINTF(ExecRegDelta, "%s [%5s] "\
 168                                       "Native: %#010x => %#010x "\
 169                                       "M5:     %#010x => %#010x\n",
 170                                       vergence, regNames[i],
 171                                       nState.oldState[i], nState.newState[i],
 172                                       mState.oldState[i], mState.newState[i]);
 173             }
 174         }
 175     }
 176     if (errorFound) {
 177         StaticInstPtr inst = record->getStaticInst();
 178         assert(inst);
 179         bool ran = true;
 180         if (inst->isMicroop()) {
 181             ran = false;
 182             inst = record->getMacroStaticInst();
 183         }
 184         assert(inst);
 185         record->traceInst(inst, ran);
 186
 187         bool pcError = (mState.newState[STATE_PC] !=
 188                         nState.newState[STATE_PC]);
 189         if (stopOnPCError && pcError)
 190             panic("Native trace detected an error in control flow!");
 191     }
 192 }
 193
 194 } /* namespace Trace */
 195
 196 ////////////////////////////////////////////////////////////////////////
 197 //
 198 //  ExeTracer Simulation Object
 199 //
 200 Trace::ArmNativeTrace *
 201 ArmNativeTraceParams::create()
 202 {
 203     return new Trace::ArmNativeTrace(this);
 204 };