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43 #ifndef __ARCH_ARM_PAGETABLE_H__
44 #define __ARCH_ARM_PAGETABLE_H__
46 #include "arch/arm/isa_traits.hh"
47 #include "arch/arm/utility.hh"
48 #include "arch/arm/vtophys.hh"
49 #include "config/full_system.hh"
55 VAddr(Addr a) { panic("not implemented yet."); }
59 // ITB/DTB page table entry
62 void serialize(std::ostream &os)
64 panic("Need to implement PTE serialization\n");
67 void unserialize(Checkpoint *cp, const std::string §ion)
69 panic("Need to implement PTE serialization\n");
82 operator<(const TlbRange &r2) const
84 if (!(global || r2.global)) {
85 if (contextId < r2.contextId)
87 else if (contextId > r2.contextId)
97 operator==(const TlbRange &r2) const
101 contextId == r2.contextId &&
107 // ITB/DTB table entry
123 // Matching variables
125 Addr size; // Size of this entry, == Type of TLB Rec
126 Addr vpn; // Virtual Page Number
127 uint32_t asid; // Address Space Identifier
128 uint8_t N; // Number of bits in pagesize
133 bool nonCacheable; // Can we wrap this in mtype?
134 bool sNp; // Section descriptor
141 uint32_t attributes; // Memory attributes formatted for PAR
144 // Access permissions
145 bool xn; // Execute Never
146 uint8_t ap:3; // Access permissions bits
147 uint8_t domain:4; // Access Domain
149 TlbRange range; // For fast TLB searching
151 //Construct an entry that maps to physical address addr for SE mode
152 TlbEntry(Addr _asn, Addr _vaddr, Addr _paddr)
154 pfn = _paddr >> PageShift;
155 size = PageBytes - 1;
160 vpn = _vaddr >> PageShift;
162 nonCacheable = sNp = false;
166 domain = DomainClient; //???
173 updateVaddr(Addr new_vaddr)
175 vpn = new_vaddr >> PageShift;
181 return pfn << PageShift;
185 match(Addr va, uint8_t cid)
188 if (valid && va >= v && va <= v + size && (global || cid == asid))
196 return (pfn << N) | (va & size);
199 void serialize(std::ostream &os) { panic("Need to Implement\n"); }
200 void unserialize(Checkpoint *cp, const std::string §ion)
201 { panic("Need to Implement\n");}
207 #endif // __ARCH_ARM_PAGETABLE_H__