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41 #ifndef __ARCH_ARM_PMU_HH__
42 #define __ARCH_ARM_PMU_HH__
48 #include "arch/arm/isa_device.hh"
49 #include "arch/arm/registers.hh"
50 #include "arch/arm/system.hh"
51 #include "base/cprintf.hh"
52 #include "cpu/base.hh"
53 #include "debug/PMUVerbose.hh"
54 #include "sim/eventq.hh"
55 #include "sim/sim_object.hh"
56 #include "sim/system.hh"
61 class ArmInterruptPin;
67 * Model of an ARM PMU version 3
69 * This class implements a subset of the ARM PMU v3 specification as
70 * described in the ARMv8 reference manual. It supports most of the
71 * features of the PMU, however the following features are known to be
75 * <li>Event filtering (e.g., from different privilege levels).
76 * <li>Access controls (the PMU currently ignores the execution level).
77 * <li>The chain counter (event no. 0x1E) is unimplemented.
80 * The PMU itself does not implement any events, in merely provides an
81 * interface for the configuration scripts to hook up probes that
82 * drive events. Configuration scripts should call addEventProbe() to
83 * configure custom events or high-level methods to configure
84 * architected events. The Python implementation of addEventProbe()
85 * automatically delays event type registration until after
88 * In order to support CPU switching and some combined counters (e.g.,
89 * memory references synthesized from loads and stores), the PMU
90 * allows multiple probes per event type. When creating a system that
91 * switches between CPU models that share the same PMU, PMU events for
92 * all of the CPU models can be registered with the PMU.
94 * @see The ARM Architecture Refererence Manual (DDI 0487A)
97 class PMU : public SimObject, public ArmISA::BaseISADevice {
99 PMU(const ArmPMUParams *p);
102 void addEventProbe(unsigned int id, SimObject *obj, const char *name);
103 void addSoftwareIncrementEvent(unsigned int id);
105 void registerEvent(uint32_t id);
107 public: // SimObject and related interfaces
108 void serialize(CheckpointOut &cp) const override;
109 void unserialize(CheckpointIn &cp) override;
111 void drainResume() override;
113 void regProbeListeners() override;
115 public: // ISA Device interface
116 void setThreadContext(ThreadContext *tc) override;
119 * Set a register within the PMU.
121 * @param misc_reg Register number (see miscregs.hh)
122 * @param val Value to store
124 void setMiscReg(int misc_reg, RegVal val) override;
126 * Read a register within the PMU.
128 * @param misc_reg Register number (see miscregs.hh)
129 * @return Register value.
131 RegVal readMiscReg(int misc_reg) override;
133 protected: // PMU register types and constants
137 // Event counter reset
139 // Cycle counter reset
141 // Cycle counter divider enable
145 // Disable PMCCNTR when event counting is prohibited
147 // Long Cycle counter enable
149 // Number of event counters implemented
152 Bitfield<23, 16> idcode;
154 Bitfield<31, 24> imp;
158 // Performance counter selector
160 EndBitUnion(PMSELR_t)
162 BitUnion32(PMEVTYPER_t)
163 Bitfield<15, 0> evtCount;
165 // Secure EL3 filtering
167 // Non-secure EL2 mode filtering
169 // Non-secure EL0 mode filtering
171 // Non-secure EL1 mode filtering
177 EndBitUnion(PMEVTYPER_t)
180 * Counter ID within the PMU.
182 * This value is typically used to index into various registers
183 * controlling interrupts and overflows. The value normally in the
184 * [0, 31] range, where 31 refers to the cycle counter.
186 typedef unsigned int CounterId;
188 /** Cycle Count Register Number */
189 static const CounterId PMCCNTR = 31;
194 * See the PMU documentation for a list of architected IDs.
196 typedef unsigned int EventTypeId;
198 protected: /* High-level register and interrupt handling */
199 RegVal readMiscRegInt(int misc_reg);
202 * PMCR write handling
204 * The PMCR register needs special handling since writing to it
205 * changes PMU-global state (e.g., resets all counters).
207 * @param val New PMCR value
209 void setControlReg(PMCR_t val);
212 * Reset all event counters excluding the cycle counter to zero.
214 void resetEventCounts();
217 * Deliver a PMU interrupt to the GIC
219 void raiseInterrupt();
222 * Clear a PMU interrupt.
224 void clearInterrupt();
227 * Get the value of a performance counter.
229 * This method returns the value of a general purpose performance
230 * counter or the fixed-function cycle counter. Non-existing
231 * counters are treated as constant '0'.
233 * @return Value of the performance counter, 0 if the counter does
236 uint64_t getCounterValue(CounterId id) const {
237 return isValidCounter(id) ? getCounter(id).getValue() : 0;
241 * Set the value of a performance counter.
243 * This method sets the value of a general purpose performance
244 * counter or the fixed-function cycle counter. Writes to
245 * non-existing counters are ignored.
247 void setCounterValue(CounterId id, uint64_t val);
250 * Get the type and filter settings of a counter (PMEVTYPER)
252 * This method implements a read from a PMEVTYPER register. It
253 * returns the type value and filter settings of a general purpose
254 * performance counter or the cycle counter. Non-existing counters
255 * are treated as constant '0'.
257 * @param id Counter ID within the PMU.
258 * @return Performance counter type ID.
260 PMEVTYPER_t getCounterTypeRegister(CounterId id) const;
263 * Set the type and filter settings of a performance counter
266 * This method implements a write to a PMEVTYPER register. It sets
267 * the type value and filter settings of a general purpose
268 * performance counter or the cycle counter. Writes to
269 * non-existing counters are ignored. The method automatically
270 * updates the probes used by the counter if it is enabled.
272 * @param id Counter ID within the PMU.
273 * @param type Performance counter type and filter configuration..
275 void setCounterTypeRegister(CounterId id, PMEVTYPER_t type);
278 * Used for writing the Overflow Flag Status Register (SET/CLR)
280 * This method implements a write to the PMOVSSET/PMOVSCLR registers.
281 * It is capturing change of state in the register bits so that
282 * the overflow interrupt can be raised/cleared as a side effect
285 * @param new_val New value of the Overflow Status Register
287 void setOverflowStatus(RegVal new_val);
289 protected: /* Probe handling and counter state */
293 * Event definition base class
299 virtual ~PMUEvent() {}
302 * attach this event to a given counter
304 * @param a pointer to the counter where to attach this event
306 void attachEvent(PMU::CounterState *user);
309 * detach this event from a given counter
311 * @param a pointer to the counter where to detach this event from
313 void detachEvent(PMU::CounterState *user);
316 * notify an event increment of val units, all the attached counters'
317 * value is incremented by val units.
319 * @param the quantity by which to increment the attached counter
322 virtual void increment(const uint64_t val);
325 * Enable the current event
327 virtual void enable() = 0;
330 * Disable the current event
332 virtual void disable() = 0;
335 * Method called immediately before a counter access in order for
336 * the associated event to update its state (if required)
338 virtual void updateAttachedCounters() {}
342 /** set of counters using this event **/
343 std::set<PMU::CounterState*> userCounters;
346 struct RegularEvent : public PMUEvent {
347 typedef std::pair<SimObject*, std::string> EventTypeEntry;
349 void addMicroarchitectureProbe(SimObject* object,
352 panic_if(!object,"malformed probe-point"
353 " definition with name %s\n", name);
355 microArchitectureEventSet.emplace(object, name);
359 struct RegularProbe: public ProbeListenerArgBase<uint64_t>
361 RegularProbe(RegularEvent *parent, SimObject* obj,
363 : ProbeListenerArgBase(obj->getProbeManager(), name),
364 parentEvent(parent) {}
366 RegularProbe() = delete;
368 void notify(const uint64_t &val);
371 RegularEvent *parentEvent;
374 /** The set of events driving the event value **/
375 std::set<EventTypeEntry> microArchitectureEventSet;
377 /** Set of probe listeners tapping onto each of the input micro-arch
378 * events which compose this pmu event
380 std::vector<std::unique_ptr<RegularProbe>> attachedProbePointList;
382 void enable() override;
384 void disable() override;
387 class SWIncrementEvent : public PMUEvent
389 void enable() override {}
390 void disable() override {}
395 * write on the sw increment register inducing an increment of the
396 * counters with this event selected according to the bitfield written.
398 * @param the bitfield selecting the counters to increment.
400 void write(uint64_t val);
404 * Obtain the event of a given id
406 * @param the id of the event to obtain
407 * @return a pointer to the event with id eventId
409 PMUEvent* getEvent(uint64_t eventId);
411 /** State of a counter within the PMU. **/
412 struct CounterState : public Serializable {
413 CounterState(PMU &pmuReference, uint64_t counter_id)
414 : eventId(0), filter(0), enabled(false),
415 overflow64(false), sourceEvent(nullptr),
416 counterId(counter_id), value(0), resetValue(false),
419 void serialize(CheckpointOut &cp) const override;
420 void unserialize(CheckpointIn &cp) override;
423 * Add an event count to the counter and check for overflow.
425 * @param delta Number of events to add to the counter.
426 * @return the quantity remaining until a counter overflow occurs.
428 uint64_t add(uint64_t delta);
430 bool isFiltered() const;
433 * Detach the counter from its event
438 * Attach this counter to an event
440 * @param the event to attach the counter to
442 void attach(PMUEvent* event);
445 * Obtain the counter id
447 * @return the pysical counter id
449 uint64_t getCounterId() const{
454 * rReturn the counter value
456 * @return the counter value
458 uint64_t getValue() const;
461 * overwrite the value of the counter
463 * @param the new counter value
465 void setValue(uint64_t val);
467 public: /* Serializable state */
468 /** Counter event ID */
471 /** Filtering settings (evtCount is unused) */
474 /** Is the counter enabled? */
477 /** Is this a 64-bit counter? */
480 protected: /* Configuration */
481 /** PmuEvent currently in use (if any) **/
482 PMUEvent *sourceEvent;
484 /** id of the counter instance **/
487 /** Current value of the counter */
490 /** Flag keeping track if the counter has been reset **/
495 template <typename ...Args>
496 void debugCounter(const char* mainString, Args &...args) const {
498 std::string userString = csprintf(mainString, args...);
500 warn("[counterId = %d, eventId = %d, sourceEvent = 0x%x] %s",
501 counterId, eventId, sourceEvent, userString.c_str());
507 * Is this a valid counter ID?
509 * @param id ID of counter within the PMU.
511 * @return true if counter is within the allowed range or the
512 * cycle counter, false otherwise.
514 bool isValidCounter(CounterId id) const {
515 return id < counters.size() || id == PMCCNTR;
519 * Return the state of a counter.
521 * @param id ID of counter within the PMU.
522 * @return Reference to a CounterState instance representing the
525 CounterState &getCounter(CounterId id) {
526 assert(isValidCounter(id));
527 return id == PMCCNTR ? cycleCounter : counters[id];
531 * Return the state of a counter.
533 * @param id ID of counter within the PMU.
534 * @return Reference to a CounterState instance representing the
537 const CounterState &getCounter(CounterId id) const {
538 assert(isValidCounter(id));
539 return id == PMCCNTR ? cycleCounter : counters[id];
543 * Depending on counter configuration, add or remove the probes
544 * driving the counter.
546 * Look at the state of a counter and (re-)attach the probes
547 * needed to drive a counter if it is currently active. All probes
548 * for the counter are detached if the counter is inactive.
550 * @param id ID of counter within the PMU.
551 * @param ctr Reference to the counter's state
553 void updateCounter(CounterState &ctr);
556 * Check if a counter's settings allow it to be counted.
558 * @param ctr Counter state instance representing this counter.
559 * @return false if the counter is active, true otherwise.
561 bool isFiltered(const CounterState &ctr) const;
564 * Call updateCounter() for each counter in the PMU if the
565 * counter's state has changed..
567 * @see updateCounter()
569 void updateAllCounters();
571 protected: /* State that needs to be serialized */
572 /** Performance Monitor Count Enable Register */
575 /** Performance Monitor Control Register */
578 /** Performance Monitor Selection Register */
581 /** Performance Monitor Interrupt Enable Register */
584 /** Performance Monitor Overflow Status Register */
588 * Performance counter ID register
590 * These registers contain a bitmask of available architected
593 uint64_t reg_pmceid0;
594 uint64_t reg_pmceid1;
596 /** Remainder part when the clock counter is divided by 64 */
597 unsigned clock_remainder;
599 /** The number of regular event counters **/
600 uint64_t maximumCounterCount;
602 /** State of all general-purpose counters supported by PMU */
603 std::vector<CounterState> counters;
605 /** State of the cycle counter */
606 CounterState cycleCounter;
608 /** The id of the counter hardwired to the cpu cycle counter **/
609 const uint64_t cycleCounterEventId;
611 /** The event that implements the software increment **/
612 SWIncrementEvent *swIncrementEvent;
614 protected: /* Configuration and constants */
615 /** Constant (configuration-dependent) part of the PMCR */
616 PMCR_t reg_pmcr_conf;
618 /** PMCR write mask when accessed from the guest */
619 static const RegVal reg_pmcr_wr_mask;
621 /** Performance monitor interrupt number */
622 ArmInterruptPin *interrupt;
625 * List of event types supported by this PMU.
627 std::map<EventTypeId, PMUEvent*> eventMap;
630 } // namespace ArmISA