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41 #ifndef __ARCH_ARM_PMU_HH__
42 #define __ARCH_ARM_PMU_HH__
48 #include "arch/arm/isa_device.hh"
49 #include "arch/arm/registers.hh"
50 #include "sim/probe/probe.hh"
51 #include "sim/sim_object.hh"
61 * Model of an ARM PMU version 3
63 * This class implements a subset of the ARM PMU v3 specification as
64 * described in the ARMv8 reference manual. It supports most of the
65 * features of the PMU, however the following features are known to be
69 * <li>Event filtering (e.g., from different privilege levels).
70 * <li>Access controls (the PMU currently ignores the execution level).
71 * <li>The chain counter (event no. 0x1E) is unimplemented.
74 * The PMU itself does not implement any events, in merely provides an
75 * interface for the configuration scripts to hook up probes that
76 * drive events. Configuration scripts should call addEventProbe() to
77 * configure custom events or high-level methods to configure
78 * architected events. The Python implementation of addEventProbe()
79 * automatically delays event type registration until after
82 * In order to support CPU switching and some combined counters (e.g.,
83 * memory references synthesized from loads and stores), the PMU
84 * allows multiple probes per event type. When creating a system that
85 * switches between CPU models that share the same PMU, PMU events for
86 * all of the CPU models can be registered with the PMU.
88 * @see The ARM Architecture Refererence Manual (DDI 0487A)
91 class PMU : public SimObject, public ArmISA::BaseISADevice {
93 PMU(const ArmPMUParams *p);
96 void addEventProbe(unsigned int id, SimObject *obj, const char *name);
98 public: // SimObject and related interfaces
99 void serialize(std::ostream &os) M5_ATTR_OVERRIDE;
100 void unserialize(Checkpoint *cp, const std::string &sec) M5_ATTR_OVERRIDE;
102 void drainResume() M5_ATTR_OVERRIDE;
105 public: // ISA Device interface
107 * Set a register within the PMU.
109 * @param misc_reg Register number (see miscregs.hh)
110 * @param val Value to store
112 void setMiscReg(int misc_reg, MiscReg val) M5_ATTR_OVERRIDE;
114 * Read a register within the PMU.
116 * @param misc_reg Register number (see miscregs.hh)
117 * @return Register value.
119 MiscReg readMiscReg(int misc_reg) M5_ATTR_OVERRIDE;
121 protected: // PMU register types and constants
125 // Event counter reset
127 // Cycle counter reset
129 // Cycle counter divider enable
133 // Disable PMCCNTR when event counting is prohibited
135 // Long Cycle counter enable
137 // Number of event counters implemented
140 Bitfield<23, 16> idcode;
142 Bitfield<31, 24> imp;
146 // Performance counter selector
148 EndBitUnion(PMSELR_t)
150 BitUnion32(PMEVTYPER_t)
151 Bitfield<9, 0> evtCount;
153 // Secure EL3 filtering
155 // Non-secure EL2 mode filtering
157 // Non-secure EL0 mode filtering
159 // Non-secure EL1 mode filtering
165 EndBitUnion(PMEVTYPER_t)
168 * Counter ID within the PMU.
170 * This value is typically used to index into various registers
171 * controlling interrupts and overflows. The value normally in the
172 * [0, 31] range, where 31 refers to the cycle counter.
174 typedef unsigned int CounterId;
176 /** Cycle Count Register Number */
177 static const CounterId PMCCNTR = 31;
182 * See the PMU documentation for a list of architected IDs.
184 typedef unsigned int EventTypeId;
186 /** ID of the software increment event */
187 static const EventTypeId ARCH_EVENT_SW_INCR = 0x00;
189 protected: /* High-level register and interrupt handling */
190 MiscReg readMiscRegInt(int misc_reg);
193 * PMCR write handling
195 * The PMCR register needs special handling since writing to it
196 * changes PMU-global state (e.g., resets all counters).
198 * @param val New PMCR value
200 void setControlReg(PMCR_t val);
203 * Reset all event counters excluding the cycle counter to zero.
205 void resetEventCounts();
208 * Deliver a PMU interrupt to the GIC
210 void raiseInterrupt();
213 * Get the value of a performance counter.
215 * This method returns the value of a general purpose performance
216 * counter or the fixed-function cycle counter. Non-existing
217 * counters are treated as constant '0'.
219 * @return Value of the performance counter, 0 if the counter does
222 uint64_t getCounterValue(CounterId id) const {
223 return isValidCounter(id) ? getCounter(id).value : 0;
227 * Set the value of a performance counter.
229 * This method sets the value of a general purpose performance
230 * counter or the fixed-function cycle counter. Writes to
231 * non-existing counters are ignored.
233 void setCounterValue(CounterId id, uint64_t val);
236 * Get the type and filter settings of a counter (PMEVTYPER)
238 * This method implements a read from a PMEVTYPER register. It
239 * returns the type value and filter settings of a general purpose
240 * performance counter or the cycle counter. Non-existing counters
241 * are treated as constant '0'.
243 * @param id Counter ID within the PMU.
244 * @return Performance counter type ID.
246 PMEVTYPER_t getCounterTypeRegister(CounterId id) const;
249 * Set the type and filter settings of a performance counter
252 * This method implements a write to a PMEVTYPER register. It sets
253 * the type value and filter settings of a general purpose
254 * performance counter or the cycle counter. Writes to
255 * non-existing counters are ignored. The method automatically
256 * updates the probes used by the counter if it is enabled.
258 * @param id Counter ID within the PMU.
259 * @param type Performance counter type and filter configuration..
261 void setCounterTypeRegister(CounterId id, PMEVTYPER_t type);
263 protected: /* Probe handling and counter state */
264 class ProbeListener : public ProbeListenerArgBase<uint64_t>
267 ProbeListener(PMU &_pmu, CounterId _id,
268 ProbeManager *pm, const std::string &name)
269 : ProbeListenerArgBase(pm, name),
270 pmu(_pmu), id(_id) {}
272 void notify(const uint64_t &val) M5_ATTR_OVERRIDE
274 pmu.handleEvent(id, val);
281 typedef std::unique_ptr<ProbeListener> ProbeListenerUPtr;
284 * Event type configuration
286 * The main purpose of this class is to describe how a PMU event
287 * type is sampled. It is implemented as a probe factory that
288 * returns a probe attached to the object the event is mointoring.
292 * @param _obj Target SimObject
293 * @param _name Probe name
295 EventType(SimObject *_obj, const std::string &_name)
296 : obj(_obj), name(_name) {}
299 * Create and attach a probe used to drive this event.
301 * @param pmu PMU owning the probe.
302 * @param CounterID counter ID within the PMU.
303 * @return Pointer to a probe listener.
305 std::unique_ptr<ProbeListener> create(PMU &pmu, CounterId cid) const
307 std::unique_ptr<ProbeListener> ptr;
308 ptr.reset(new ProbeListener(pmu, cid,
309 obj->getProbeManager(), name));
313 /** SimObject being measured by this probe */
314 SimObject *const obj;
315 /** Probe name within obj */
316 const std::string name;
319 // Disable the default constructor
323 /** State of a counter within the PMU. */
324 struct CounterState {
326 : eventId(0), filter(0), value(0), enabled(false),
329 listeners.reserve(4);
332 void serialize(std::ostream &os);
333 void unserialize(Checkpoint *cp, const std::string §ion);
336 * Add an event count to the counter and check for overflow.
338 * @param delta Number of events to add to the counter.
339 * @return true on overflow, false otherwise.
341 bool add(uint64_t delta);
343 public: /* Serializable state */
344 /** Counter event ID */
347 /** Filtering settings (evtCount is unused) */
350 /** Current value of the counter */
353 /** Is the counter enabled? */
356 /** Is this a 64-bit counter? */
359 public: /* Configuration */
360 /** Probe listeners driving this counter */
361 std::vector<ProbeListenerUPtr> listeners;
365 * Handle an counting event triggered by a probe.
367 * This method is called by the ProbeListener class whenever an
368 * active probe is triggered. Ths method adds the event count from
369 * the probe to the affected counter, checks for overflows, and
370 * delivers an interrupt if needed.
372 * @param id Counter ID affected by the probe.
373 * @param delta Counter increment
375 void handleEvent(CounterId id, uint64_t delta);
378 * Is this a valid counter ID?
380 * @param id ID of counter within the PMU.
382 * @return true if counter is within the allowed range or the
383 * cycle counter, false otherwise.
385 bool isValidCounter(CounterId id) const {
386 return id < counters.size() || id == PMCCNTR;
390 * Return the state of a counter.
392 * @param id ID of counter within the PMU.
393 * @return Reference to a CounterState instance representing the
396 CounterState &getCounter(CounterId id) {
397 assert(isValidCounter(id));
398 return id == PMCCNTR ? cycleCounter : counters[id];
403 * Return the state of a counter.
405 * @param id ID of counter within the PMU.
406 * @return Reference to a CounterState instance representing the
409 const CounterState &getCounter(CounterId id) const {
410 assert(isValidCounter(id));
411 return id == PMCCNTR ? cycleCounter : counters[id];
415 * Depending on counter configuration, add or remove the probes
416 * driving the counter.
418 * Look at the state of a counter and (re-)attach the probes
419 * needed to drive a counter if it is currently active. All probes
420 * for the counter are detached if the counter is inactive.
422 * @param id ID of counter within the PMU.
423 * @param ctr Reference to the counter's state
425 void updateCounter(CounterId id, CounterState &ctr);
428 * Check if a counter's settings allow it to be counted.
430 * @param ctr Counter state instance representing this counter.
431 * @return false if the counter is active, true otherwise.
433 bool isFiltered(const CounterState &ctr) const;
436 * Call updateCounter() for each counter in the PMU if the
437 * counter's state has changed..
439 * @see updateCounter()
441 void updateAllCounters();
443 protected: /* State that needs to be serialized */
444 /** Performance Monitor Count Enable Register */
447 /** Performance Monitor Control Register */
450 /** Performance Monitor Selection Register */
453 /** Performance Monitor Interrupt Enable Register */
456 /** Performance Monitor Overflow Status Register */
460 * Performance counter ID register
462 * This register contains a bitmask of available architected
467 /** Remainder part when the clock counter is divided by 64 */
468 unsigned clock_remainder;
470 /** State of all general-purpose counters supported by PMU */
471 std::vector<CounterState> counters;
472 /** State of the cycle counter */
473 CounterState cycleCounter;
475 protected: /* Configuration and constants */
476 /** Constant (configuration-dependent) part of the PMCR */
477 PMCR_t reg_pmcr_conf;
478 /** PMCR write mask when accessed from the guest */
479 static const MiscReg reg_pmcr_wr_mask;
481 /** Performance monitor interrupt number */
482 const unsigned int pmuInterrupt;
483 /** Platform this device belongs to */
484 Platform *const platform;
487 * Event types supported by this PMU.
489 * Each event type ID can map to multiple EventType structures,
490 * which enables the PMU to use multiple probes for a single
491 * event. This can be useful in the following cases:
493 * <li>Some events can are increment by multiple different probe
494 * points (e.g., the CPU memory access counter gets
495 * incremented for both loads and stores).
497 * <li>A system switching between multiple CPU models can
498 * register events for all models that will execute a thread
499 * and tehreby ensure that the PMU continues to work.
502 std::multimap<EventTypeId, EventType> pmuEventTypes;
505 } // namespace ArmISA