O3: Fix some variable length instruction issues with the O3 CPU and ARM ISA.
[gem5.git] / src / arch / arm / predecoder.cc
1 /*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
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8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
17 *
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19 * modification, are permitted provided that the following conditions are
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21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
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27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Gabe Black
42 */
43
44 #include "arch/arm/isa_traits.hh"
45 #include "arch/arm/predecoder.hh"
46 #include "arch/arm/utility.hh"
47 #include "base/trace.hh"
48 #include "cpu/thread_context.hh"
49
50 namespace ArmISA
51 {
52
53 void
54 Predecoder::advanceThumbCond()
55 {
56 uint8_t condMask = itstate.mask;
57 uint8_t thumbCond = itstate.cond;
58 DPRINTF(Predecoder, "Advancing ITSTATE from %#x, %#x.\n",
59 thumbCond, condMask);
60 condMask = condMask << 1;
61 uint8_t newBit = bits(condMask, 4);
62 condMask &= mask(4);
63 if (condMask == 0) {
64 thumbCond = 0;
65 } else {
66 replaceBits(thumbCond, 0, newBit);
67 }
68 DPRINTF(Predecoder, "Advancing ITSTATE to %#x, %#x.\n",
69 thumbCond, condMask);
70 itstate.mask = condMask;
71 itstate.cond = thumbCond;
72 }
73
74 void
75 Predecoder::process()
76 {
77 // emi is typically ready, with some caveats below...
78 emiReady = true;
79
80 if (!emi.thumb) {
81 emi.instBits = data;
82 emi.sevenAndFour = bits(data, 7) && bits(data, 4);
83 emi.isMisc = (bits(data, 24, 23) == 0x2 &&
84 bits(data, 20) == 0);
85 consumeBytes(4);
86 DPRINTF(Predecoder, "Arm inst: %#x.\n", (uint64_t)emi);
87 } else {
88 uint16_t word = (data >> (offset * 8));
89 if (bigThumb) {
90 // A 32 bit thumb inst is half collected.
91 emi.instBits = emi.instBits | word;
92 bigThumb = false;
93 consumeBytes(2);
94 DPRINTF(Predecoder, "Second half of 32 bit Thumb: %#x.\n",
95 emi.instBits);
96 if (itstate.mask) {
97 emi.itstate = itstate;
98 advanceThumbCond();
99 emi.newItstate = itstate;
100 }
101 } else {
102 uint16_t highBits = word & 0xF800;
103 if (highBits == 0xE800 || highBits == 0xF000 ||
104 highBits == 0xF800) {
105 // The start of a 32 bit thumb inst.
106 emi.bigThumb = 1;
107 if (offset == 0) {
108 // We've got the whole thing.
109 emi.instBits = (data >> 16) | (data << 16);
110 DPRINTF(Predecoder, "All of 32 bit Thumb: %#x.\n",
111 emi.instBits);
112 consumeBytes(4);
113 if (itstate.mask) {
114 emi.itstate = itstate;
115 advanceThumbCond();
116 emi.newItstate = itstate;
117 }
118 } else {
119 // We only have the first half word.
120 DPRINTF(Predecoder,
121 "First half of 32 bit Thumb.\n");
122 emi.instBits = (uint32_t)word << 16;
123 bigThumb = true;
124 consumeBytes(2);
125 // emi not ready yet.
126 emiReady = false;
127 }
128 } else {
129 // A 16 bit thumb inst.
130 consumeBytes(2);
131 emi.instBits = word;
132 // Set the condition code field artificially.
133 emi.condCode = COND_UC;
134 DPRINTF(Predecoder, "16 bit Thumb: %#x.\n",
135 emi.instBits);
136 if (bits(word, 15, 8) == 0xbf &&
137 bits(word, 3, 0) != 0x0) {
138 emi.itstate = itstate;
139 itstate = bits(word, 7, 0);
140 emi.newItstate = itstate;
141 DPRINTF(Predecoder,
142 "IT detected, cond = %#x, mask = %#x\n",
143 itstate.cond, itstate.mask);
144 } else if (itstate.mask) {
145 emi.itstate = itstate;
146 advanceThumbCond();
147 emi.newItstate = itstate;
148 }
149 }
150 }
151 }
152 }
153
154 //Use this to give data to the predecoder. This should be used
155 //when there is control flow.
156 void
157 Predecoder::moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
158 {
159 data = inst;
160 offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
161 emi.thumb = pc.thumb();
162 FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR);
163 emi.fpscrLen = fpscr.len;
164 emi.fpscrStride = fpscr.stride;
165 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
166 itstate.top6 = cpsr.it2;
167 itstate.bottom2 = cpsr.it1;
168 outOfBytes = false;
169 process();
170 }
171
172 }