2 * Copyright (c) 2010 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * Copyright (c) 2007-2008 The Florida State University
16 * All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
45 #ifndef __ARCH_ARM_PREDECODER_HH__
46 #define __ARCH_ARM_PREDECODER_HH__
50 #include "arch/arm/miscregs.hh"
51 #include "arch/arm/types.hh"
52 #include "base/types.hh"
62 //The extended machine instruction being generated
83 Predecoder(ThreadContext * _tc) :
89 ThreadContext * getTC()
95 setTC(ThreadContext * _tc)
102 //Use this to give data to the predecoder. This should be used
103 //when there is control flow.
104 void moreBytes(const PCState &pc, Addr fetchPC, MachInst inst);
106 //Use this to give data to the predecoder. This should be used
107 //when instructions are executed in order.
108 void moreBytes(MachInst machInst)
110 moreBytes(0, 0, machInst);
113 inline void consumeBytes(int numBytes)
116 assert(offset <= sizeof(MachInst));
117 if (offset == sizeof(MachInst))
121 bool needMoreBytes() const
126 bool extMachInstReady() const
131 int getInstSize() const
133 return (!emi.thumb || emi.bigThumb) ? 4 : 2;
136 //This returns a constant reference to the ExtMachInst to avoid a copy
137 ExtMachInst getExtMachInst(PCState &pc)
140 ExtMachInst thisEmi = emi;
141 pc.npc(pc.pc() + getInstSize());
143 pc.nextItstate(itBits);
144 thisEmi.itstate = pc.itstate();
145 pc.size(getInstSize());
154 #endif // __ARCH_ARM_PREDECODER_HH__