src/arch/arm/predecoder.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Gabe Black
  42  *          Stephen Hines
  43  */
  44
  45 #ifndef __ARCH_ARM_PREDECODER_HH__
  46 #define __ARCH_ARM_PREDECODER_HH__
  47
  48 #include "arch/arm/types.hh"
  49 #include "arch/arm/miscregs.hh"
  50 #include "base/types.hh"
  51
  52 class ThreadContext;
  53
  54 namespace ArmISA
  55 {
  56     class Predecoder
  57     {
  58       protected:
  59         ThreadContext * tc;
  60         //The extended machine instruction being generated
  61         ExtMachInst emi;
  62         MachInst data;
  63         bool bigThumb;
  64         int offset;
  65         ITSTATE itstate;
  66
  67       public:
  68         void reset()
  69         {
  70             bigThumb = false;
  71             offset = 0;
  72             emi = 0;
  73         }
  74
  75         Predecoder(ThreadContext * _tc) :
  76             tc(_tc), data(0)
  77         {
  78             reset();
  79         }
  80
  81         ThreadContext * getTC()
  82         {
  83             return tc;
  84         }
  85
  86         void
  87         setTC(ThreadContext * _tc)
  88         {
  89             tc = _tc;
  90         }
  91
  92         void advanceThumbCond();
  93         void process();
  94
  95         //Use this to give data to the predecoder. This should be used
  96         //when there is control flow.
  97         void moreBytes(Addr pc, Addr fetchPC, MachInst inst);
  98
  99         //Use this to give data to the predecoder. This should be used
 100         //when instructions are executed in order.
 101         void moreBytes(MachInst machInst)
 102         {
 103             moreBytes(0, 0, machInst);
 104         }
 105
 106         bool needMoreBytes()
 107         {
 108             return sizeof(MachInst) > offset;
 109         }
 110
 111         bool extMachInstReady()
 112         {
 113             // The only way an instruction wouldn't be ready is if this is a
 114             // 32 bit ARM instruction that's not 32 bit aligned.
 115             return !bigThumb;
 116         }
 117
 118         int getInstSize()
 119         {
 120             return (!emi.thumb || emi.bigThumb) ? 4 : 2;
 121         }
 122
 123         //This returns a constant reference to the ExtMachInst to avoid a copy
 124         ExtMachInst getExtMachInst()
 125         {
 126             ExtMachInst thisEmi = emi;
 127             emi = 0;
 128             return thisEmi;
 129         }
 130     };
 131 };
 132
 133 #endif // __ARCH_ARM_PREDECODER_HH__