src/arch/arm/predecoder.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2006 The Regents of The University of Michigan
  15  * Copyright (c) 2007-2008 The Florida State University
  16  * All rights reserved.
  17  *
  18  * Redistribution and use in source and binary forms, with or without
  19  * modification, are permitted provided that the following conditions are
  20  * met: redistributions of source code must retain the above copyright
  21  * notice, this list of conditions and the following disclaimer;
  22  * redistributions in binary form must reproduce the above copyright
  23  * notice, this list of conditions and the following disclaimer in the
  24  * documentation and/or other materials provided with the distribution;
  25  * neither the name of the copyright holders nor the names of its
  26  * contributors may be used to endorse or promote products derived from
  27  * this software without specific prior written permission.
  28  *
  29  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  30  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  31  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  32  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  33  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  34  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  35  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  36  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  37  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  38  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  39  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  40  *
  41  * Authors: Gabe Black
  42  *          Stephen Hines
  43  */
  44
  45 #ifndef __ARCH_ARM_PREDECODER_HH__
  46 #define __ARCH_ARM_PREDECODER_HH__
  47
  48 #include "arch/arm/types.hh"
  49 #include "base/misc.hh"
  50 #include "base/types.hh"
  51
  52 class ThreadContext;
  53
  54 namespace ArmISA
  55 {
  56     class Predecoder
  57     {
  58       protected:
  59         ThreadContext * tc;
  60         //The extended machine instruction being generated
  61         ExtMachInst emi;
  62         MachInst data;
  63         bool bigThumb;
  64         int offset;
  65         ITSTATE itstate;
  66
  67       public:
  68         void reset()
  69         {
  70             bigThumb = false;
  71             offset = 0;
  72             emi = 0;
  73         }
  74
  75         Predecoder(ThreadContext * _tc) :
  76             tc(_tc), data(0)
  77         {
  78             reset();
  79         }
  80
  81         ThreadContext * getTC()
  82         {
  83             return tc;
  84         }
  85
  86         void setTC(ThreadContext * _tc)
  87         {
  88             tc = _tc;
  89         }
  90
  91         void advanceThumbCond()
  92         {
  93             uint8_t condMask = itstate.mask;
  94             uint8_t thumbCond = itstate.cond;
  95             DPRINTF(Predecoder, "Advancing ITSTATE from %#x, %#x.\n",
  96                     thumbCond, condMask);
  97             condMask = condMask << 1;
  98             uint8_t newBit = bits(condMask, 4);
  99             condMask &= mask(4);
 100             if (condMask == 0) {
 101                 thumbCond = 0;
 102             } else {
 103                 replaceBits(thumbCond, 0, newBit);
 104             }
 105             DPRINTF(Predecoder, "Advancing ITSTATE to %#x, %#x.\n",
 106                     thumbCond, condMask);
 107             itstate.mask = condMask;
 108             itstate.cond = thumbCond;
 109         }
 110
 111         void process()
 112         {
 113             if (!emi.thumb) {
 114                 emi.instBits = data;
 115                 emi.sevenAndFour = bits(data, 7) && bits(data, 4);
 116                 emi.isMisc = (bits(data, 24, 23) == 0x2 &&
 117                               bits(data, 20) == 0);
 118                 DPRINTF(Predecoder, "Arm inst: %#x.\n", (uint64_t)emi);
 119             } else {
 120                 uint16_t word = (data >> (offset * 8));
 121                 if (bigThumb) {
 122                     // A 32 bit thumb inst is half collected.
 123                     emi.instBits = emi.instBits | word;
 124                     bigThumb = false;
 125                     offset += 2;
 126                     DPRINTF(Predecoder, "Second half of 32 bit Thumb: %#x.\n",
 127                             emi.instBits);
 128                     if (itstate.mask) {
 129                         emi.itstate = itstate;
 130                         advanceThumbCond();
 131                         emi.newItstate = itstate;
 132                     }
 133                 } else {
 134                     uint16_t highBits = word & 0xF800;
 135                     if (highBits == 0xE800 || highBits == 0xF000 ||
 136                             highBits == 0xF800) {
 137                         // The start of a 32 bit thumb inst.
 138                         emi.bigThumb = 1;
 139                         if (offset == 0) {
 140                             // We've got the whole thing.
 141                             emi.instBits = (data >> 16) | (data << 16);
 142                             DPRINTF(Predecoder, "All of 32 bit Thumb: %#x.\n",
 143                                     emi.instBits);
 144                             offset += 4;
 145                             if (itstate.mask) {
 146                                 emi.itstate = itstate;
 147                                 advanceThumbCond();
 148                                 emi.newItstate = itstate;
 149                             }
 150                         } else {
 151                             // We only have the first half word.
 152                             DPRINTF(Predecoder,
 153                                     "First half of 32 bit Thumb.\n");
 154                             emi.instBits = (uint32_t)word << 16;
 155                             bigThumb = true;
 156                             offset += 2;
 157                         }
 158                     } else {
 159                         // A 16 bit thumb inst.
 160                         offset += 2;
 161                         emi.instBits = word;
 162                         // Set the condition code field artificially.
 163                         emi.condCode = COND_UC;
 164                         DPRINTF(Predecoder, "16 bit Thumb: %#x.\n",
 165                                 emi.instBits);
 166                         if (bits(word, 15, 8) == 0xbf &&
 167                                 bits(word, 3, 0) != 0x0) {
 168                             emi.itstate = itstate;
 169                             itstate = bits(word, 7, 0);
 170                             emi.newItstate = itstate;
 171                             DPRINTF(Predecoder,
 172                                     "IT detected, cond = %#x, mask = %#x\n",
 173                                     itstate.cond, itstate.mask);
 174                         } else if (itstate.mask) {
 175                             emi.itstate = itstate;
 176                             advanceThumbCond();
 177                             emi.newItstate = itstate;
 178                         }
 179                     }
 180                 }
 181             }
 182         }
 183
 184         //Use this to give data to the predecoder. This should be used
 185         //when there is control flow.
 186         void moreBytes(Addr pc, Addr fetchPC, MachInst inst)
 187         {
 188             data = inst;
 189             offset = (fetchPC >= pc) ? 0 : pc - fetchPC;
 190             emi.thumb = (pc & (ULL(1) << PcTBitShift)) ? 1 : 0;
 191             FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR);
 192             emi.fpscrLen = fpscr.len;
 193             emi.fpscrStride = fpscr.stride;
 194             CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
 195             itstate.top6 = cpsr.it2;
 196             itstate.bottom2 = cpsr.it1;
 197             process();
 198         }
 199
 200         //Use this to give data to the predecoder. This should be used
 201         //when instructions are executed in order.
 202         void moreBytes(MachInst machInst)
 203         {
 204             moreBytes(0, 0, machInst);
 205         }
 206
 207         bool needMoreBytes()
 208         {
 209             return sizeof(MachInst) > offset;
 210         }
 211
 212         bool extMachInstReady()
 213         {
 214             // The only way an instruction wouldn't be ready is if this is a
 215             // 32 bit ARM instruction that's not 32 bit aligned.
 216             return !bigThumb;
 217         }
 218
 219         int getInstSize()
 220         {
 221             return (!emi.thumb || emi.bigThumb) ? 4 : 2;
 222         }
 223
 224         //This returns a constant reference to the ExtMachInst to avoid a copy
 225         ExtMachInst getExtMachInst()
 226         {
 227             ExtMachInst thisEmi = emi;
 228             emi = 0;
 229             return thisEmi;
 230         }
 231     };
 232 };
 233
 234 #endif // __ARCH_ARM_PREDECODER_HH__