src/arch/arm/registers.hh

   1 /*
   2  * Copyright (c) 2010-2011, 2014, 2016-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007-2008 The Florida State University
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Stephen Hines
  41  */
  42
  43 #ifndef __ARCH_ARM_REGISTERS_HH__
  44 #define __ARCH_ARM_REGISTERS_HH__
  45
  46 #include "arch/arm/ccregs.hh"
  47 #include "arch/arm/generated/max_inst_regs.hh"
  48 #include "arch/arm/intregs.hh"
  49 #include "arch/arm/miscregs.hh"
  50 #include "arch/arm/types.hh"
  51 #include "arch/generic/vec_pred_reg.hh"
  52 #include "arch/generic/vec_reg.hh"
  53
  54 namespace ArmISA {
  55
  56
  57 // For a predicated instruction, we need all the
  58 // destination registers to also be sources
  59 const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
  60     ArmISAInst::MaxInstSrcRegs;
  61 using ArmISAInst::MaxInstDestRegs;
  62 using ArmISAInst::MaxMiscDestRegs;
  63
  64 // Number of VecElem per Vector Register considering only pre-SVE
  65 // Advanced SIMD registers.
  66 constexpr unsigned NumVecElemPerNeonVecReg = 4;
  67 // Number of VecElem per Vector Register, computed based on the vector length
  68 constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords;
  69
  70 using VecElem = uint32_t;
  71 using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
  72 using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
  73 using VecRegContainer = VecReg::Container;
  74
  75 using VecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
  76                                  VecPredRegHasPackedRepr, false>;
  77 using ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
  78                                       VecPredRegHasPackedRepr, true>;
  79 using VecPredRegContainer = VecPredReg::Container;
  80
  81 // Constants Related to the number of registers
  82 // Int, Float, CC, Misc
  83 const int NumIntArchRegs = NUM_ARCH_INTREGS;
  84 const int NumIntRegs = NUM_INTREGS;
  85 const int NumFloatRegs = 0; // Float values are stored in the VecRegs
  86 const int NumCCRegs = NUM_CCREGS;
  87 const int NumMiscRegs = NUM_MISCREGS;
  88
  89 // Vec, PredVec
  90 // NumFloatV7ArchRegs: This in theory should be 32.
  91 // However in A32 gem5 is splitting double register accesses in two
  92 // subsequent single register ones. This means we would use a index
  93 // bigger than 31 when accessing D16-D31.
  94 const int NumFloatV7ArchRegs = 64; // S0-S31, D0-D31
  95 const int NumVecV7ArchRegs  = 16; // Q0-Q15
  96 const int NumVecV8ArchRegs  = 32; // V0-V31
  97 const int NumVecSpecialRegs = 8;
  98 const int NumVecIntrlvRegs = 4;
  99 const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs;
 100 const int NumVecPredRegs = 18;  // P0-P15, FFR, UREG0
 101
 102 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
 103     NumVecPredRegs + NumMiscRegs;
 104
 105 // Semantically meaningful register indices
 106 const int ReturnValueReg = 0;
 107 const int ReturnValueReg1 = 1;
 108 const int ReturnValueReg2 = 2;
 109 const int NumArgumentRegs = 4;
 110 const int NumArgumentRegs64 = 8;
 111 const int ArgumentReg0 = 0;
 112 const int ArgumentReg1 = 1;
 113 const int ArgumentReg2 = 2;
 114 const int ArgumentReg3 = 3;
 115 const int FramePointerReg = 11;
 116 const int StackPointerReg = INTREG_SP;
 117 const int ReturnAddressReg = INTREG_LR;
 118 const int PCReg = INTREG_PC;
 119
 120 const int ZeroReg = INTREG_ZERO;
 121
 122 // Vec, PredVec indices
 123 const int VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg;
 124 const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
 125 const int INTRLVREG1 = INTRLVREG0 + 1;
 126 const int INTRLVREG2 = INTRLVREG0 + 2;
 127 const int INTRLVREG3 = INTRLVREG0 + 3;
 128 const int VECREG_UREG0 = 32;
 129 const int PREDREG_FFR = 16;
 130 const int PREDREG_UREG0 = 17;
 131
 132 const int SyscallNumReg = ReturnValueReg;
 133 const int SyscallPseudoReturnReg = ReturnValueReg;
 134 const int SyscallSuccessReg = ReturnValueReg;
 135
 136 } // namespace ArmISA
 137
 138 #endif