src/arch/arm/registers.hh

   1 /*
   2  * Copyright (c) 2010-2011, 2014, 2016-2019 ARM Limited
   3  * All rights reserved
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   5  * The license below extends only to copyright in the software and shall
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   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
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  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2007-2008 The Florida State University
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
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  26  * this software without specific prior written permission.
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  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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  40
  41 #ifndef __ARCH_ARM_REGISTERS_HH__
  42 #define __ARCH_ARM_REGISTERS_HH__
  43
  44 #include "arch/arm/ccregs.hh"
  45 #include "arch/arm/generated/max_inst_regs.hh"
  46 #include "arch/arm/intregs.hh"
  47 #include "arch/arm/miscregs.hh"
  48 #include "arch/arm/types.hh"
  49 #include "arch/generic/vec_pred_reg.hh"
  50 #include "arch/generic/vec_reg.hh"
  51
  52 namespace ArmISA {
  53
  54
  55 // For a predicated instruction, we need all the
  56 // destination registers to also be sources
  57 const int MaxInstSrcRegs = ArmISAInst::MaxInstDestRegs +
  58     ArmISAInst::MaxInstSrcRegs;
  59 using ArmISAInst::MaxInstDestRegs;
  60 using ArmISAInst::MaxMiscDestRegs;
  61
  62 // Number of VecElem per Vector Register considering only pre-SVE
  63 // Advanced SIMD registers.
  64 constexpr unsigned NumVecElemPerNeonVecReg = 4;
  65 // Number of VecElem per Vector Register, computed based on the vector length
  66 constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords;
  67
  68 using VecElem = uint32_t;
  69 using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
  70 using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
  71 using VecRegContainer = VecReg::Container;
  72
  73 using VecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
  74                                  VecPredRegHasPackedRepr, false>;
  75 using ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
  76                                       VecPredRegHasPackedRepr, true>;
  77 using VecPredRegContainer = VecPredReg::Container;
  78
  79 // Constants Related to the number of registers
  80 // Int, Float, CC, Misc
  81 const int NumIntArchRegs = NUM_ARCH_INTREGS;
  82 const int NumIntRegs = NUM_INTREGS;
  83 const int NumFloatRegs = 0; // Float values are stored in the VecRegs
  84 const int NumCCRegs = NUM_CCREGS;
  85 const int NumMiscRegs = NUM_MISCREGS;
  86
  87 // Vec, PredVec
  88 // NumFloatV7ArchRegs: This in theory should be 32.
  89 // However in A32 gem5 is splitting double register accesses in two
  90 // subsequent single register ones. This means we would use a index
  91 // bigger than 31 when accessing D16-D31.
  92 const int NumFloatV7ArchRegs = 64; // S0-S31, D0-D31
  93 const int NumVecV7ArchRegs  = 16; // Q0-Q15
  94 const int NumVecV8ArchRegs  = 32; // V0-V31
  95 const int NumVecSpecialRegs = 8;
  96 const int NumVecIntrlvRegs = 4;
  97 const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs;
  98 const int NumVecPredRegs = 18;  // P0-P15, FFR, UREG0
  99
 100 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
 101     NumVecPredRegs + NumMiscRegs;
 102
 103 // Semantically meaningful register indices
 104 const int ReturnValueReg = 0;
 105 const int ReturnValueReg1 = 1;
 106 const int ReturnValueReg2 = 2;
 107 const int NumArgumentRegs = 4;
 108 const int NumArgumentRegs64 = 8;
 109 const int ArgumentReg0 = 0;
 110 const int ArgumentReg1 = 1;
 111 const int ArgumentReg2 = 2;
 112 const int ArgumentReg3 = 3;
 113 const int FramePointerReg = 11;
 114 const int StackPointerReg = INTREG_SP;
 115 const int ReturnAddressReg = INTREG_LR;
 116 const int PCReg = INTREG_PC;
 117
 118 const int ZeroReg = INTREG_ZERO;
 119
 120 // Vec, PredVec indices
 121 const int VecSpecialElem = NumVecV8ArchRegs * NumVecElemPerNeonVecReg;
 122 const int INTRLVREG0 = NumVecV8ArchRegs + NumVecSpecialRegs;
 123 const int INTRLVREG1 = INTRLVREG0 + 1;
 124 const int INTRLVREG2 = INTRLVREG0 + 2;
 125 const int INTRLVREG3 = INTRLVREG0 + 3;
 126 const int VECREG_UREG0 = 32;
 127 const int PREDREG_FFR = 16;
 128 const int PREDREG_UREG0 = 17;
 129
 130 const int SyscallNumReg = ReturnValueReg;
 131 const int SyscallPseudoReturnReg = ReturnValueReg;
 132 const int SyscallSuccessReg = ReturnValueReg;
 133
 134 } // namespace ArmISA
 135
 136 #endif