src/arch/arm/stage2_mmu.cc

   1 /*
   2  * Copyright (c) 2012-2013, 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
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   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
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  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "arch/arm/stage2_mmu.hh"
  39
  40 #include "arch/arm/faults.hh"
  41 #include "arch/arm/system.hh"
  42 #include "arch/arm/table_walker.hh"
  43 #include "arch/arm/tlb.hh"
  44 #include "cpu/base.hh"
  45 #include "cpu/thread_context.hh"
  46
  47 using namespace ArmISA;
  48
  49 Stage2MMU::Stage2MMU(const Params *p)
  50     : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
  51       port(_stage1Tlb->getTableWalker(), p->sys),
  52       requestorId(p->sys->getRequestorId(_stage1Tlb->getTableWalker()))
  53 {
  54     // we use the stage-one table walker as the parent of the port,
  55     // and to get our requestor id, this is done to keep things
  56     // symmetrical with other ISAs in terms of naming and stats
  57     stage1Tlb()->setMMU(this, requestorId);
  58     stage2Tlb()->setMMU(this, requestorId);
  59 }
  60
  61 Fault
  62 Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
  63     uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional)
  64 {
  65     Fault fault;
  66
  67     // translate to physical address using the second stage MMU
  68     auto req = std::make_shared<Request>();
  69     req->setVirt(descAddr, numBytes, flags | Request::PT_WALK,
  70                 requestorId, 0);
  71     if (isFunctional) {
  72         fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read);
  73     } else {
  74         fault = stage2Tlb()->translateAtomic(req, tc, BaseTLB::Read);
  75     }
  76
  77     // Now do the access.
  78     if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
  79         Packet pkt = Packet(req, MemCmd::ReadReq);
  80         pkt.dataStatic(data);
  81         if (isFunctional) {
  82             port.sendFunctional(&pkt);
  83         } else {
  84             port.sendAtomic(&pkt);
  85         }
  86         assert(!pkt.isError());
  87     }
  88
  89     // If there was a fault annotate it with the flag saying the foult occured
  90     // while doing a translation for a stage 1 page table walk.
  91     if (fault != NoFault) {
  92         ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
  93         armFault->annotate(ArmFault::S1PTW, true);
  94         armFault->annotate(ArmFault::OVA, oVAddr);
  95     }
  96     return fault;
  97 }
  98
  99 void
 100 Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr,
 101                          Stage2Translation *translation, int numBytes,
 102                          Request::Flags flags)
 103 {
 104     // translate to physical address using the second stage MMU
 105     translation->setVirt(
 106             descAddr, numBytes, flags | Request::PT_WALK, requestorId);
 107     translation->translateTiming(tc);
 108 }
 109
 110 Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
 111         uint8_t *_data, Event *_event, Addr _oVAddr)
 112     : data(_data), numBytes(0), event(_event), parent(_parent), oVAddr(_oVAddr),
 113     fault(NoFault)
 114 {
 115     req = std::make_shared<Request>();
 116 }
 117
 118 void
 119 Stage2MMU::Stage2Translation::finish(const Fault &_fault,
 120                                      const RequestPtr &req,
 121                                      ThreadContext *tc, BaseTLB::Mode mode)
 122 {
 123     fault = _fault;
 124
 125     // If there was a fault annotate it with the flag saying the foult occured
 126     // while doing a translation for a stage 1 page table walk.
 127     if (fault != NoFault) {
 128         ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
 129         armFault->annotate(ArmFault::S1PTW, true);
 130         armFault->annotate(ArmFault::OVA, oVAddr);
 131     }
 132
 133     if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
 134         parent.getDMAPort().dmaAction(
 135             MemCmd::ReadReq, req->getPaddr(), numBytes, event, data,
 136             tc->getCpuPtr()->clockPeriod(), req->getFlags());
 137     } else {
 138         // We can't do the DMA access as there's been a problem, so tell the
 139         // event we're done
 140         event->process();
 141     }
 142 }
 143
 144 ArmISA::Stage2MMU *
 145 ArmStage2MMUParams::create()
 146 {
 147     return new ArmISA::Stage2MMU(this);
 148 }