src/arch/arm/stage2_mmu.cc

   1 /*
   2  * Copyright (c) 2012-2013, 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
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   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
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  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #include "arch/arm/stage2_mmu.hh"
  39
  40 #include "arch/arm/faults.hh"
  41 #include "arch/arm/system.hh"
  42 #include "arch/arm/table_walker.hh"
  43 #include "arch/arm/tlb.hh"
  44 #include "cpu/base.hh"
  45 #include "cpu/thread_context.hh"
  46
  47 using namespace ArmISA;
  48
  49 Stage2MMU::Stage2MMU(const Params *p)
  50     : SimObject(p), _stage1Tlb(p->tlb), _stage2Tlb(p->stage2_tlb),
  51       port(_stage1Tlb->getTableWalker(), p->sys),
  52       masterId(p->sys->getMasterId(_stage1Tlb->getTableWalker()))
  53 {
  54     // we use the stage-one table walker as the parent of the port,
  55     // and to get our master id, this is done to keep things
  56     // symmetrical with other ISAs in terms of naming and stats
  57     stage1Tlb()->setMMU(this, masterId);
  58     stage2Tlb()->setMMU(this, masterId);
  59 }
  60
  61 Fault
  62 Stage2MMU::readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
  63     uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional)
  64 {
  65     Fault fault;
  66
  67     // translate to physical address using the second stage MMU
  68     auto req = std::make_shared<Request>();
  69     req->setVirt(descAddr, numBytes, flags | Request::PT_WALK, masterId, 0);
  70     if (isFunctional) {
  71         fault = stage2Tlb()->translateFunctional(req, tc, BaseTLB::Read);
  72     } else {
  73         fault = stage2Tlb()->translateAtomic(req, tc, BaseTLB::Read);
  74     }
  75
  76     // Now do the access.
  77     if (fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
  78         Packet pkt = Packet(req, MemCmd::ReadReq);
  79         pkt.dataStatic(data);
  80         if (isFunctional) {
  81             port.sendFunctional(&pkt);
  82         } else {
  83             port.sendAtomic(&pkt);
  84         }
  85         assert(!pkt.isError());
  86     }
  87
  88     // If there was a fault annotate it with the flag saying the foult occured
  89     // while doing a translation for a stage 1 page table walk.
  90     if (fault != NoFault) {
  91         ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
  92         armFault->annotate(ArmFault::S1PTW, true);
  93         armFault->annotate(ArmFault::OVA, oVAddr);
  94     }
  95     return fault;
  96 }
  97
  98 void
  99 Stage2MMU::readDataTimed(ThreadContext *tc, Addr descAddr,
 100                          Stage2Translation *translation, int numBytes,
 101                          Request::Flags flags)
 102 {
 103     // translate to physical address using the second stage MMU
 104     translation->setVirt(
 105             descAddr, numBytes, flags | Request::PT_WALK, masterId);
 106     translation->translateTiming(tc);
 107 }
 108
 109 Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU &_parent,
 110         uint8_t *_data, Event *_event, Addr _oVAddr)
 111     : data(_data), numBytes(0), event(_event), parent(_parent), oVAddr(_oVAddr),
 112     fault(NoFault)
 113 {
 114     req = std::make_shared<Request>();
 115 }
 116
 117 void
 118 Stage2MMU::Stage2Translation::finish(const Fault &_fault,
 119                                      const RequestPtr &req,
 120                                      ThreadContext *tc, BaseTLB::Mode mode)
 121 {
 122     fault = _fault;
 123
 124     // If there was a fault annotate it with the flag saying the foult occured
 125     // while doing a translation for a stage 1 page table walk.
 126     if (fault != NoFault) {
 127         ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
 128         armFault->annotate(ArmFault::S1PTW, true);
 129         armFault->annotate(ArmFault::OVA, oVAddr);
 130     }
 131
 132     if (_fault == NoFault && !req->getFlags().isSet(Request::NO_ACCESS)) {
 133         parent.getDMAPort().dmaAction(
 134             MemCmd::ReadReq, req->getPaddr(), numBytes, event, data,
 135             tc->getCpuPtr()->clockPeriod(), req->getFlags());
 136     } else {
 137         // We can't do the DMA access as there's been a problem, so tell the
 138         // event we're done
 139         event->process();
 140     }
 141 }
 142
 143 ArmISA::Stage2MMU *
 144 ArmStage2MMUParams::create()
 145 {
 146     return new ArmISA::Stage2MMU(this);
 147 }