2 * Copyright (c) 2012-2013, 2015 ARM Limited
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23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Thomas Grocutt
40 #include "arch/arm/stage2_mmu.hh"
42 #include "arch/arm/faults.hh"
43 #include "arch/arm/system.hh"
44 #include "arch/arm/table_walker.hh"
45 #include "arch/arm/tlb.hh"
46 #include "cpu/base.hh"
47 #include "cpu/thread_context.hh"
49 using namespace ArmISA
;
51 Stage2MMU::Stage2MMU(const Params
*p
)
52 : SimObject(p
), _stage1Tlb(p
->tlb
), _stage2Tlb(p
->stage2_tlb
),
53 port(_stage1Tlb
->getTableWalker(), p
->sys
),
54 masterId(p
->sys
->getMasterId(_stage1Tlb
->getTableWalker()->name()))
56 // we use the stage-one table walker as the parent of the port,
57 // and to get our master id, this is done to keep things
58 // symmetrical with other ISAs in terms of naming and stats
59 stage1Tlb()->setMMU(this, masterId
);
60 stage2Tlb()->setMMU(this, masterId
);
64 Stage2MMU::readDataUntimed(ThreadContext
*tc
, Addr oVAddr
, Addr descAddr
,
65 uint8_t *data
, int numBytes
, Request::Flags flags
, bool isFunctional
)
69 // translate to physical address using the second stage MMU
70 Request req
= Request();
71 req
.setVirt(0, descAddr
, numBytes
, flags
| Request::PT_WALK
, masterId
, 0);
73 fault
= stage2Tlb()->translateFunctional(&req
, tc
, BaseTLB::Read
);
75 fault
= stage2Tlb()->translateAtomic(&req
, tc
, BaseTLB::Read
);
79 if (fault
== NoFault
&& !req
.getFlags().isSet(Request::NO_ACCESS
)) {
80 Packet pkt
= Packet(&req
, MemCmd::ReadReq
);
83 port
.sendFunctional(&pkt
);
85 port
.sendAtomic(&pkt
);
87 assert(!pkt
.isError());
90 // If there was a fault annotate it with the flag saying the foult occured
91 // while doing a translation for a stage 1 page table walk.
92 if (fault
!= NoFault
) {
93 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
94 armFault
->annotate(ArmFault::S1PTW
, true);
95 armFault
->annotate(ArmFault::OVA
, oVAddr
);
101 Stage2MMU::readDataTimed(ThreadContext
*tc
, Addr descAddr
,
102 Stage2Translation
*translation
, int numBytes
,
103 Request::Flags flags
)
106 // translate to physical address using the second stage MMU
107 translation
->setVirt(descAddr
, numBytes
, flags
| Request::PT_WALK
, masterId
);
108 fault
= translation
->translateTiming(tc
);
112 Stage2MMU::Stage2Translation::Stage2Translation(Stage2MMU
&_parent
,
113 uint8_t *_data
, Event
*_event
, Addr _oVAddr
)
114 : data(_data
), numBytes(0), event(_event
), parent(_parent
), oVAddr(_oVAddr
),
120 Stage2MMU::Stage2Translation::finish(const Fault
&_fault
, RequestPtr req
,
121 ThreadContext
*tc
, BaseTLB::Mode mode
)
125 // If there was a fault annotate it with the flag saying the foult occured
126 // while doing a translation for a stage 1 page table walk.
127 if (fault
!= NoFault
) {
128 ArmFault
*armFault
= reinterpret_cast<ArmFault
*>(fault
.get());
129 armFault
->annotate(ArmFault::S1PTW
, true);
130 armFault
->annotate(ArmFault::OVA
, oVAddr
);
133 if (_fault
== NoFault
&& !req
->getFlags().isSet(Request::NO_ACCESS
)) {
134 parent
.getPort().dmaAction(MemCmd::ReadReq
, req
->getPaddr(), numBytes
,
135 event
, data
, tc
->getCpuPtr()->clockPeriod(),
138 // We can't do the DMA access as there's been a problem, so tell the
145 ArmStage2MMUParams::create()
147 return new ArmISA::Stage2MMU(this);