src/arch/arm/stage2_mmu.hh

   1 /*
   2  * Copyright (c) 2012-2013, 2015 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  */
  37
  38 #ifndef __ARCH_ARM_STAGE2_MMU_HH__
  39 #define __ARCH_ARM_STAGE2_MMU_HH__
  40
  41 #include "arch/arm/faults.hh"
  42 #include "arch/arm/tlb.hh"
  43 #include "dev/dma_device.hh"
  44 #include "mem/request.hh"
  45 #include "params/ArmStage2MMU.hh"
  46 #include "sim/eventq.hh"
  47
  48 namespace ArmISA {
  49
  50 class Stage2MMU : public SimObject
  51 {
  52   private:
  53     TLB *_stage1Tlb;
  54     /** The TLB that will cache the stage 2 look ups. */
  55     TLB *_stage2Tlb;
  56
  57   protected:
  58
  59     /** Port to issue translation requests from */
  60     DmaPort port;
  61
  62     /** Request id for requests generated by this MMU */
  63     MasterID masterId;
  64
  65   public:
  66     /** This translation class is used to trigger the data fetch once a timing
  67         translation returns the translated physical address */
  68     class Stage2Translation : public BaseTLB::Translation
  69     {
  70       private:
  71         uint8_t      *data;
  72         int          numBytes;
  73         RequestPtr   req;
  74         Event        *event;
  75         Stage2MMU    &parent;
  76         Addr         oVAddr;
  77
  78       public:
  79         Fault fault;
  80
  81         Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
  82                           Addr _oVAddr);
  83
  84         void
  85         markDelayed() {}
  86
  87         void
  88         finish(const Fault &fault, const RequestPtr &req, ThreadContext *tc,
  89                BaseTLB::Mode mode);
  90
  91         void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
  92         {
  93             numBytes = size;
  94             req->setVirt(vaddr, size, flags, masterId, 0);
  95         }
  96
  97         void translateTiming(ThreadContext *tc)
  98         {
  99             parent.stage2Tlb()->translateTiming(req, tc, this, BaseTLB::Read);
 100         }
 101     };
 102
 103     typedef ArmStage2MMUParams Params;
 104     Stage2MMU(const Params *p);
 105
 106     /**
 107      * Get the port that ultimately belongs to the stage-two MMU, but
 108      * is used by the two table walkers, and is exposed externally and
 109      * connected through the stage-one table walker.
 110      */
 111     DmaPort& getDMAPort() { return port; }
 112
 113     Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
 114         uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
 115     void readDataTimed(ThreadContext *tc, Addr descAddr,
 116                        Stage2Translation *translation, int numBytes,
 117                        Request::Flags flags);
 118
 119     TLB* stage1Tlb() const { return _stage1Tlb; }
 120     TLB* stage2Tlb() const { return _stage2Tlb; }
 121 };
 122
 123
 124
 125 } // namespace ArmISA
 126
 127 #endif //__ARCH_ARM_STAGE2_MMU_HH__
 128