2 * Copyright (c) 2012-2013 ARM Limited
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25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
37 * Authors: Thomas Grocutt
40 #ifndef __ARCH_ARM_STAGE2_MMU_HH__
41 #define __ARCH_ARM_STAGE2_MMU_HH__
43 #include "arch/arm/faults.hh"
44 #include "arch/arm/tlb.hh"
45 #include "mem/request.hh"
46 #include "params/ArmStage2MMU.hh"
47 #include "sim/eventq.hh"
51 class Stage2MMU : public SimObject
55 /** The TLB that will cache the stage 2 look ups. */
59 /** This translation class is used to trigger the data fetch once a timing
60 translation returns the translated physical address */
61 class Stage2Translation : public BaseTLB::Translation
74 Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
81 finish(Fault fault, RequestPtr req, ThreadContext *tc,
84 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
87 req.setVirt(0, vaddr, size, flags, masterId, 0);
90 Fault translateTiming(ThreadContext *tc)
92 return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
96 typedef ArmStage2MMUParams Params;
97 Stage2MMU(const Params *p);
99 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
100 uint8_t *data, int numBytes, Request::Flags flags, int masterId,
102 Fault readDataTimed(ThreadContext *tc, Addr descAddr,
103 Stage2Translation *translation, int numBytes, Request::Flags flags,
106 TLB* stage1Tlb() const { return _stage1Tlb; }
107 TLB* stage2Tlb() const { return _stage2Tlb; }
112 } // namespace ArmISA
114 #endif //__ARCH_ARM_STAGE2_MMU_HH__