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37 * Authors: Thomas Grocutt
40 #ifndef __ARCH_ARM_STAGE2_MMU_HH__
41 #define __ARCH_ARM_STAGE2_MMU_HH__
43 #include "arch/arm/faults.hh"
44 #include "arch/arm/tlb.hh"
45 #include "mem/request.hh"
46 #include "params/ArmStage2MMU.hh"
47 #include "sim/eventq.hh"
51 class Stage2MMU : public SimObject
55 /** The TLB that will cache the stage 2 look ups. */
61 * A snooping DMA port that currently does nothing besides
62 * extending the DMA port to accept snoops without
63 * complaining. Currently we take no action on any snoops.
65 class SnoopingDmaPort : public DmaPort
70 virtual void recvTimingSnoopReq(PacketPtr pkt)
73 virtual Tick recvAtomicSnoop(PacketPtr pkt)
76 virtual void recvFunctionalSnoop(PacketPtr pkt)
79 virtual bool isSnooping() const { return true; }
84 * A snooping DMA port merely calls the construtor of the DMA
87 SnoopingDmaPort(MemObject *dev, System *s) :
92 /** Port to issue translation requests from */
95 /** Request id for requests generated by this MMU */
99 /** This translation class is used to trigger the data fetch once a timing
100 translation returns the translated physical address */
101 class Stage2Translation : public BaseTLB::Translation
114 Stage2Translation(Stage2MMU &_parent, uint8_t *_data, Event *_event,
121 finish(const Fault &fault, RequestPtr req, ThreadContext *tc,
124 void setVirt(Addr vaddr, int size, Request::Flags flags, int masterId)
127 req.setVirt(0, vaddr, size, flags, masterId, 0);
130 Fault translateTiming(ThreadContext *tc)
132 return (parent.stage2Tlb()->translateTiming(&req, tc, this, BaseTLB::Read));
136 typedef ArmStage2MMUParams Params;
137 Stage2MMU(const Params *p);
140 * Get the port that ultimately belongs to the stage-two MMU, but
141 * is used by the two table walkers, and is exposed externally and
142 * connected through the stage-one table walker.
144 DmaPort& getPort() { return port; }
146 unsigned int drain(DrainManager *dm);
148 Fault readDataUntimed(ThreadContext *tc, Addr oVAddr, Addr descAddr,
149 uint8_t *data, int numBytes, Request::Flags flags, bool isFunctional);
150 Fault readDataTimed(ThreadContext *tc, Addr descAddr,
151 Stage2Translation *translation, int numBytes,
152 Request::Flags flags);
154 TLB* stage1Tlb() const { return _stage1Tlb; }
155 TLB* stage2Tlb() const { return _stage2Tlb; }
160 } // namespace ArmISA
162 #endif //__ARCH_ARM_STAGE2_MMU_HH__