src/arch/arm/system.cc

   1 /*
   2  * Copyright (c) 2010, 2012-2013, 2015,2017-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43 #include "arch/arm/system.hh"
  44
  45 #include <iostream>
  46
  47 #include "arch/arm/semihosting.hh"
  48 #include "base/loader/object_file.hh"
  49 #include "base/loader/symtab.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "dev/arm/gic_v2.hh"
  52 #include "mem/fs_translating_port_proxy.hh"
  53 #include "mem/physical.hh"
  54 #include "sim/full_system.hh"
  55
  56 using namespace std;
  57 using namespace Linux;
  58
  59 ArmSystem::ArmSystem(Params *p)
  60     : System(p),
  61       bootLoaders(), bootldr(nullptr),
  62       _haveSecurity(p->have_security),
  63       _haveLPAE(p->have_lpae),
  64       _haveVirtualization(p->have_virtualization),
  65       _haveCrypto(p->have_crypto),
  66       _genericTimer(nullptr),
  67       _gic(nullptr),
  68       _resetAddr(p->auto_reset_addr ?
  69                  (kernelEntry & loadAddrMask) + loadAddrOffset :
  70                  p->reset_addr),
  71       _highestELIs64(p->highest_el_is_64),
  72       _physAddrRange64(p->phys_addr_range_64),
  73       _haveLargeAsid64(p->have_large_asid_64),
  74       _haveSVE(p->have_sve),
  75       _sveVL(p->sve_vl),
  76       _haveLSE(p->have_lse),
  77       _havePAN(p->have_pan),
  78       semihosting(p->semihosting),
  79       multiProc(p->multi_proc)
  80 {
  81     // Check if the physical address range is valid
  82     if (_highestELIs64 && (
  83             _physAddrRange64 < 32 ||
  84             _physAddrRange64 > 48 ||
  85             (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
  86         fatal("Invalid physical address range (%d)\n", _physAddrRange64);
  87     }
  88
  89     bootLoaders.reserve(p->boot_loader.size());
  90     for (const auto &bl : p->boot_loader) {
  91         std::unique_ptr<ObjectFile> obj;
  92         obj.reset(createObjectFile(bl));
  93
  94         fatal_if(!obj, "Could not read bootloader: %s\n", bl);
  95         bootLoaders.emplace_back(std::move(obj));
  96     }
  97
  98     if (kernel) {
  99         bootldr = getBootLoader(kernel);
 100     } else if (!bootLoaders.empty()) {
 101         // No kernel specified, default to the first boot loader
 102         bootldr = bootLoaders[0].get();
 103     }
 104
 105     if (!bootLoaders.empty() && !bootldr)
 106         fatal("Can't find a matching boot loader / kernel combination!");
 107
 108     if (bootldr) {
 109         bootldr->loadGlobalSymbols(debugSymbolTable);
 110
 111         warn_if(bootldr->entryPoint() != _resetAddr,
 112                 "Bootloader entry point %#x overriding reset address %#x",
 113                 bootldr->entryPoint(), _resetAddr);
 114         const_cast<Addr&>(_resetAddr) = bootldr->entryPoint();
 115
 116         if ((bootldr->getArch() == ObjectFile::Arm64) && !_highestELIs64) {
 117             warn("Highest ARM exception-level set to AArch32 but bootloader "
 118                   "is for AArch64. Assuming you wanted these to match.\n");
 119             _highestELIs64 = true;
 120         } else if ((bootldr->getArch() == ObjectFile::Arm) && _highestELIs64) {
 121             warn("Highest ARM exception-level set to AArch64 but bootloader "
 122                   "is for AArch32. Assuming you wanted these to match.\n");
 123             _highestELIs64 = false;
 124         }
 125     }
 126
 127     debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
 128 }
 129
 130 void
 131 ArmSystem::initState()
 132 {
 133     // Moved from the constructor to here since it relies on the
 134     // address map being resolved in the interconnect
 135
 136     // Call the initialisation of the super class
 137     System::initState();
 138
 139     const Params* p = params();
 140
 141     if (bootldr) {
 142         bool is_gic_v2 =
 143             getGIC()->supportsVersion(BaseGic::GicVersion::GIC_V2);
 144         bootldr->buildImage().write(physProxy);
 145
 146         inform("Using bootloader at address %#x\n", bootldr->entryPoint());
 147
 148         // Put the address of the boot loader into r7 so we know
 149         // where to branch to after the reset fault
 150         // All other values needed by the boot loader to know what to do
 151         if (!p->flags_addr)
 152            fatal("flags_addr must be set with bootloader\n");
 153
 154         if (!p->gic_cpu_addr && is_gic_v2)
 155             fatal("gic_cpu_addr must be set with bootloader\n");
 156
 157         for (int i = 0; i < threadContexts.size(); i++) {
 158             if (!_highestELIs64)
 159                 threadContexts[i]->setIntReg(3, (kernelEntry & loadAddrMask) +
 160                         loadAddrOffset);
 161             if (is_gic_v2)
 162                 threadContexts[i]->setIntReg(4, params()->gic_cpu_addr);
 163             threadContexts[i]->setIntReg(5, params()->flags_addr);
 164         }
 165         inform("Using kernel entry physical address at %#x\n",
 166                (kernelEntry & loadAddrMask) + loadAddrOffset);
 167     } else {
 168         // Set the initial PC to be at start of the kernel code
 169         if (!_highestELIs64)
 170             threadContexts[0]->pcState((kernelEntry & loadAddrMask) +
 171                     loadAddrOffset);
 172     }
 173 }
 174
 175 ArmSystem *
 176 ArmSystem::getArmSystem(System *sys)
 177 {
 178     ArmSystem *a_sys = dynamic_cast<ArmSystem *>(sys);
 179     assert(a_sys);
 180     return a_sys;
 181 }
 182
 183 ArmSystem*
 184 ArmSystem::getArmSystem(ThreadContext *tc)
 185 {
 186     ArmSystem *a_sys = dynamic_cast<ArmSystem *>(tc->getSystemPtr());
 187     assert(a_sys);
 188     return a_sys;
 189 }
 190
 191 bool
 192 ArmSystem::haveSecurity(ThreadContext *tc)
 193 {
 194     return FullSystem? getArmSystem(tc)->haveSecurity() : false;
 195 }
 196
 197
 198 ArmSystem::~ArmSystem()
 199 {
 200     if (debugPrintkEvent)
 201         delete debugPrintkEvent;
 202 }
 203
 204 ObjectFile *
 205 ArmSystem::getBootLoader(ObjectFile *const obj)
 206 {
 207     for (auto &bl : bootLoaders) {
 208         if (bl->getArch() == obj->getArch())
 209             return bl.get();
 210     }
 211
 212     return nullptr;
 213 }
 214
 215 bool
 216 ArmSystem::haveLPAE(ThreadContext *tc)
 217 {
 218     return FullSystem? getArmSystem(tc)->haveLPAE() : false;
 219 }
 220
 221 bool
 222 ArmSystem::haveVirtualization(ThreadContext *tc)
 223 {
 224     return FullSystem? getArmSystem(tc)->haveVirtualization() : false;
 225 }
 226
 227 bool
 228 ArmSystem::highestELIs64(ThreadContext *tc)
 229 {
 230     return FullSystem? getArmSystem(tc)->highestELIs64() : true;
 231 }
 232
 233 ExceptionLevel
 234 ArmSystem::highestEL(ThreadContext *tc)
 235 {
 236     return FullSystem? getArmSystem(tc)->highestEL() : EL1;
 237 }
 238
 239 bool
 240 ArmSystem::haveEL(ThreadContext *tc, ExceptionLevel el)
 241 {
 242     switch (el) {
 243       case EL0:
 244       case EL1:
 245         return true;
 246       case EL2:
 247         return haveVirtualization(tc);
 248       case EL3:
 249         return haveSecurity(tc);
 250       default:
 251         warn("Unimplemented Exception Level\n");
 252         return false;
 253     }
 254 }
 255
 256 Addr
 257 ArmSystem::resetAddr(ThreadContext *tc)
 258 {
 259     return getArmSystem(tc)->resetAddr();
 260 }
 261
 262 uint8_t
 263 ArmSystem::physAddrRange(ThreadContext *tc)
 264 {
 265     return getArmSystem(tc)->physAddrRange();
 266 }
 267
 268 Addr
 269 ArmSystem::physAddrMask(ThreadContext *tc)
 270 {
 271     return getArmSystem(tc)->physAddrMask();
 272 }
 273
 274 bool
 275 ArmSystem::haveLargeAsid64(ThreadContext *tc)
 276 {
 277     return getArmSystem(tc)->haveLargeAsid64();
 278 }
 279
 280 bool
 281 ArmSystem::haveSemihosting(ThreadContext *tc)
 282 {
 283     return FullSystem && getArmSystem(tc)->haveSemihosting();
 284 }
 285
 286 uint64_t
 287 ArmSystem::callSemihosting64(ThreadContext *tc,
 288                              uint32_t op, uint64_t param)
 289 {
 290     ArmSystem *sys = getArmSystem(tc);
 291     return sys->semihosting->call64(tc, op, param);
 292 }
 293
 294 uint32_t
 295 ArmSystem::callSemihosting32(ThreadContext *tc,
 296                              uint32_t op, uint32_t param)
 297 {
 298     ArmSystem *sys = getArmSystem(tc);
 299     return sys->semihosting->call32(tc, op, param);
 300 }
 301
 302 ArmSystem *
 303 ArmSystemParams::create()
 304 {
 305     return new ArmSystem(this);
 306 }
 307
 308 void
 309 GenericArmSystem::initState()
 310 {
 311     // Moved from the constructor to here since it relies on the
 312     // address map being resolved in the interconnect
 313
 314     // Call the initialisation of the super class
 315     ArmSystem::initState();
 316 }
 317
 318 GenericArmSystem *
 319 GenericArmSystemParams::create()
 320 {
 321
 322     return new GenericArmSystem(this);
 323 }