src/arch/arm/system.cc

   1 /*
   2  * Copyright (c) 2010, 2012-2013, 2015,2017-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2006 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  *
  40  * Authors: Ali Saidi
  41  */
  42
  43 #include "arch/arm/system.hh"
  44
  45 #include <iostream>
  46
  47 #include "arch/arm/semihosting.hh"
  48 #include "base/loader/object_file.hh"
  49 #include "base/loader/symtab.hh"
  50 #include "cpu/thread_context.hh"
  51 #include "dev/arm/gic_v3.hh"
  52 #include "mem/fs_translating_port_proxy.hh"
  53 #include "mem/physical.hh"
  54 #include "sim/full_system.hh"
  55
  56 using namespace std;
  57 using namespace Linux;
  58
  59 ArmSystem::ArmSystem(Params *p)
  60     : System(p),
  61       bootLoaders(), bootldr(nullptr),
  62       _haveSecurity(p->have_security),
  63       _haveLPAE(p->have_lpae),
  64       _haveVirtualization(p->have_virtualization),
  65       _haveCrypto(p->have_crypto),
  66       _genericTimer(nullptr),
  67       _gic(nullptr),
  68       _resetAddr(p->auto_reset_addr ?
  69                  (kernelEntry & loadAddrMask) + loadAddrOffset :
  70                  p->reset_addr),
  71       _highestELIs64(p->highest_el_is_64),
  72       _physAddrRange64(p->phys_addr_range_64),
  73       _haveLargeAsid64(p->have_large_asid_64),
  74       _haveSVE(p->have_sve),
  75       _sveVL(p->sve_vl),
  76       _haveLSE(p->have_lse),
  77       _havePAN(p->have_pan),
  78       _m5opRange(p->m5ops_base ?
  79                  RangeSize(p->m5ops_base, 0x10000) :
  80                  AddrRange(1, 0)), // Create an empty range if disabled
  81       semihosting(p->semihosting),
  82       multiProc(p->multi_proc)
  83 {
  84     // Check if the physical address range is valid
  85     if (_highestELIs64 && (
  86             _physAddrRange64 < 32 ||
  87             _physAddrRange64 > 48 ||
  88             (_physAddrRange64 % 4 != 0 && _physAddrRange64 != 42))) {
  89         fatal("Invalid physical address range (%d)\n", _physAddrRange64);
  90     }
  91
  92     bootLoaders.reserve(p->boot_loader.size());
  93     for (const auto &bl : p->boot_loader) {
  94         std::unique_ptr<ObjectFile> obj;
  95         obj.reset(createObjectFile(bl));
  96
  97         fatal_if(!obj, "Could not read bootloader: %s\n", bl);
  98         bootLoaders.emplace_back(std::move(obj));
  99     }
 100
 101     if (kernel) {
 102         bootldr = getBootLoader(kernel);
 103     } else if (!bootLoaders.empty()) {
 104         // No kernel specified, default to the first boot loader
 105         bootldr = bootLoaders[0].get();
 106     }
 107
 108     if (!bootLoaders.empty() && !bootldr)
 109         fatal("Can't find a matching boot loader / kernel combination!");
 110
 111     if (bootldr) {
 112         bootldr->loadGlobalSymbols(debugSymbolTable);
 113
 114         warn_if(bootldr->entryPoint() != _resetAddr,
 115                 "Bootloader entry point %#x overriding reset address %#x",
 116                 bootldr->entryPoint(), _resetAddr);
 117         const_cast<Addr&>(_resetAddr) = bootldr->entryPoint();
 118
 119         if ((bootldr->getArch() == ObjectFile::Arm64) && !_highestELIs64) {
 120             warn("Highest ARM exception-level set to AArch32 but bootloader "
 121                   "is for AArch64. Assuming you wanted these to match.\n");
 122             _highestELIs64 = true;
 123         } else if ((bootldr->getArch() == ObjectFile::Arm) && _highestELIs64) {
 124             warn("Highest ARM exception-level set to AArch64 but bootloader "
 125                   "is for AArch32. Assuming you wanted these to match.\n");
 126             _highestELIs64 = false;
 127         }
 128     }
 129
 130     debugPrintkEvent = addKernelFuncEvent<DebugPrintkEvent>("dprintk");
 131 }
 132
 133 void
 134 ArmSystem::initState()
 135 {
 136     // Moved from the constructor to here since it relies on the
 137     // address map being resolved in the interconnect
 138
 139     // Call the initialisation of the super class
 140     System::initState();
 141
 142     const Params* p = params();
 143
 144     if (bootldr) {
 145         bool isGICv3System = dynamic_cast<Gicv3 *>(getGIC()) != nullptr;
 146         bootldr->loadSegments(physProxy);
 147
 148         inform("Using bootloader at address %#x\n", bootldr->entryPoint());
 149
 150         // Put the address of the boot loader into r7 so we know
 151         // where to branch to after the reset fault
 152         // All other values needed by the boot loader to know what to do
 153         if (!p->flags_addr)
 154            fatal("flags_addr must be set with bootloader\n");
 155
 156         if (!p->gic_cpu_addr && !isGICv3System)
 157             fatal("gic_cpu_addr must be set with bootloader\n");
 158
 159         for (int i = 0; i < threadContexts.size(); i++) {
 160             if (!_highestELIs64)
 161                 threadContexts[i]->setIntReg(3, (kernelEntry & loadAddrMask) +
 162                         loadAddrOffset);
 163             if (!isGICv3System)
 164                 threadContexts[i]->setIntReg(4, params()->gic_cpu_addr);
 165             threadContexts[i]->setIntReg(5, params()->flags_addr);
 166         }
 167         inform("Using kernel entry physical address at %#x\n",
 168                (kernelEntry & loadAddrMask) + loadAddrOffset);
 169     } else {
 170         // Set the initial PC to be at start of the kernel code
 171         if (!_highestELIs64)
 172             threadContexts[0]->pcState((kernelEntry & loadAddrMask) +
 173                     loadAddrOffset);
 174     }
 175 }
 176
 177 ArmSystem*
 178 ArmSystem::getArmSystem(ThreadContext *tc)
 179 {
 180     ArmSystem *a_sys = dynamic_cast<ArmSystem *>(tc->getSystemPtr());
 181     assert(a_sys);
 182     return a_sys;
 183 }
 184
 185 bool
 186 ArmSystem::haveSecurity(ThreadContext *tc)
 187 {
 188     return FullSystem? getArmSystem(tc)->haveSecurity() : false;
 189 }
 190
 191
 192 ArmSystem::~ArmSystem()
 193 {
 194     if (debugPrintkEvent)
 195         delete debugPrintkEvent;
 196 }
 197
 198 ObjectFile *
 199 ArmSystem::getBootLoader(ObjectFile *const obj)
 200 {
 201     for (auto &bl : bootLoaders) {
 202         if (bl->getArch() == obj->getArch())
 203             return bl.get();
 204     }
 205
 206     return nullptr;
 207 }
 208
 209 bool
 210 ArmSystem::haveLPAE(ThreadContext *tc)
 211 {
 212     return FullSystem? getArmSystem(tc)->haveLPAE() : false;
 213 }
 214
 215 bool
 216 ArmSystem::haveVirtualization(ThreadContext *tc)
 217 {
 218     return FullSystem? getArmSystem(tc)->haveVirtualization() : false;
 219 }
 220
 221 bool
 222 ArmSystem::highestELIs64(ThreadContext *tc)
 223 {
 224     return FullSystem? getArmSystem(tc)->highestELIs64() : true;
 225 }
 226
 227 ExceptionLevel
 228 ArmSystem::highestEL(ThreadContext *tc)
 229 {
 230     return FullSystem? getArmSystem(tc)->highestEL() : EL1;
 231 }
 232
 233 bool
 234 ArmSystem::haveEL(ThreadContext *tc, ExceptionLevel el)
 235 {
 236     switch (el) {
 237       case EL0:
 238       case EL1:
 239         return true;
 240       case EL2:
 241         return haveVirtualization(tc);
 242       case EL3:
 243         return haveSecurity(tc);
 244       default:
 245         warn("Unimplemented Exception Level\n");
 246         return false;
 247     }
 248 }
 249
 250 Addr
 251 ArmSystem::resetAddr(ThreadContext *tc)
 252 {
 253     return getArmSystem(tc)->resetAddr();
 254 }
 255
 256 uint8_t
 257 ArmSystem::physAddrRange(ThreadContext *tc)
 258 {
 259     return getArmSystem(tc)->physAddrRange();
 260 }
 261
 262 Addr
 263 ArmSystem::physAddrMask(ThreadContext *tc)
 264 {
 265     return getArmSystem(tc)->physAddrMask();
 266 }
 267
 268 bool
 269 ArmSystem::haveLargeAsid64(ThreadContext *tc)
 270 {
 271     return getArmSystem(tc)->haveLargeAsid64();
 272 }
 273
 274 bool
 275 ArmSystem::haveSemihosting(ThreadContext *tc)
 276 {
 277     return FullSystem && getArmSystem(tc)->haveSemihosting();
 278 }
 279
 280 uint64_t
 281 ArmSystem::callSemihosting64(ThreadContext *tc,
 282                              uint32_t op, uint64_t param)
 283 {
 284     ArmSystem *sys = getArmSystem(tc);
 285     return sys->semihosting->call64(tc, op, param);
 286 }
 287
 288 uint32_t
 289 ArmSystem::callSemihosting32(ThreadContext *tc,
 290                              uint32_t op, uint32_t param)
 291 {
 292     ArmSystem *sys = getArmSystem(tc);
 293     return sys->semihosting->call32(tc, op, param);
 294 }
 295
 296 ArmSystem *
 297 ArmSystemParams::create()
 298 {
 299     return new ArmSystem(this);
 300 }
 301
 302 void
 303 GenericArmSystem::initState()
 304 {
 305     // Moved from the constructor to here since it relies on the
 306     // address map being resolved in the interconnect
 307
 308     // Call the initialisation of the super class
 309     ArmSystem::initState();
 310 }
 311
 312 GenericArmSystem *
 313 GenericArmSystemParams::create()
 314 {
 315
 316     return new GenericArmSystem(this);
 317 }