src/arch/arm/system.hh

   1 /*
   2  * Copyright (c) 2010, 2012-2013, 2015-2021 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_SYSTEM_HH__
  42 #define __ARCH_ARM_SYSTEM_HH__
  43
  44 #include <memory>
  45 #include <string>
  46 #include <vector>
  47
  48 #include "kern/linux/events.hh"
  49 #include "params/ArmSystem.hh"
  50 #include "sim/full_system.hh"
  51 #include "sim/sim_object.hh"
  52 #include "sim/system.hh"
  53
  54 class GenericTimer;
  55 class BaseGic;
  56 class FVPBasePwrCtrl;
  57 class ThreadContext;
  58
  59 class ArmSystem : public System
  60 {
  61   protected:
  62     /**
  63      * True if this system implements the Security Extensions
  64      */
  65     const bool _haveSecurity;
  66
  67     /**
  68      * True if this system implements the Large Physical Address Extension
  69      */
  70     const bool _haveLPAE;
  71
  72     /**
  73      * True if this system implements the virtualization Extensions
  74      */
  75     const bool _haveVirtualization;
  76
  77     /**
  78      * True if this system implements the Crypto Extension
  79      */
  80     const bool _haveCrypto;
  81
  82     /**
  83      * Pointer to the Generic Timer wrapper.
  84      */
  85     GenericTimer *_genericTimer;
  86     BaseGic *_gic;
  87
  88     /**
  89      * Pointer to the Power Controller (if any)
  90      */
  91     FVPBasePwrCtrl *_pwrCtrl;
  92
  93     /**
  94      * Reset address (ARMv8)
  95      */
  96     Addr _resetAddr;
  97
  98     /**
  99      * True if the register width of the highest implemented exception level is
 100      * 64 bits (ARMv8)
 101      */
 102     bool _highestELIs64;
 103
 104     /**
 105      * Supported physical address range in bits if the highest implemented
 106      * exception level is 64 bits (ARMv8)
 107      */
 108     const uint8_t _physAddrRange64;
 109
 110     /**
 111      * True if ASID is 16 bits in AArch64 (ARMv8)
 112      */
 113     const bool _haveLargeAsid64;
 114
 115     /**
 116      * True if system implements the transactional memory extension (TME)
 117      */
 118     const bool _haveTME;
 119
 120     /**
 121      * True if SVE is implemented (ARMv8)
 122      */
 123     const bool _haveSVE;
 124
 125     /** SVE vector length at reset, in quadwords */
 126     const unsigned _sveVL;
 127
 128     /**
 129      * True if LSE is implemented (ARMv8.1)
 130      */
 131     const bool _haveLSE;
 132
 133     /** True if FEAT_VHE (Virtualization Host Extensions) is implemented */
 134     const bool _haveVHE;
 135
 136     /** True if Priviledge Access Never is implemented */
 137     const unsigned _havePAN;
 138
 139     /** True if Secure EL2 is implemented */
 140     const unsigned _haveSecEL2;
 141
 142     /**
 143      * True if the Semihosting interface is enabled.
 144      */
 145     ArmSemihosting *const semihosting;
 146
 147   public:
 148     static constexpr Addr PageBytes = ArmISA::PageBytes;
 149     static constexpr Addr PageShift = ArmISA::PageShift;
 150
 151     typedef ArmSystemParams Params;
 152     const Params &
 153     params() const
 154     {
 155         return dynamic_cast<const Params &>(_params);
 156     }
 157
 158     ArmSystem(const Params &p);
 159
 160     /** true if this a multiprocessor system */
 161     bool multiProc;
 162
 163     /** Returns true if this system implements the Security Extensions */
 164     bool haveSecurity() const { return _haveSecurity; }
 165
 166     /** Returns true if this system implements the Large Physical Address
 167      * Extension */
 168     bool haveLPAE() const { return _haveLPAE; }
 169
 170     /** Returns true if this system implements the virtualization
 171       * Extensions
 172       */
 173     bool haveVirtualization() const { return _haveVirtualization; }
 174
 175     /** Returns true if this system implements the Crypto
 176       * Extension
 177       */
 178     bool haveCrypto() const { return _haveCrypto; }
 179
 180     /** Sets the pointer to the Generic Timer. */
 181     void
 182     setGenericTimer(GenericTimer *generic_timer)
 183     {
 184         _genericTimer = generic_timer;
 185     }
 186
 187     /** Sets the pointer to the GIC. */
 188     void setGIC(BaseGic *gic) { _gic = gic; }
 189
 190     /** Sets the pointer to the Power Controller */
 191     void setPowerController(FVPBasePwrCtrl *pwr_ctrl)
 192     {
 193         _pwrCtrl = pwr_ctrl;
 194     }
 195
 196     /** Get a pointer to the system's generic timer model */
 197     GenericTimer *getGenericTimer() const { return _genericTimer; }
 198
 199     /** Get a pointer to the system's GIC */
 200     BaseGic *getGIC() const { return _gic; }
 201
 202     /** Get a pointer to the system's power controller */
 203     FVPBasePwrCtrl *getPowerController() const { return _pwrCtrl; }
 204
 205     /** Returns true if the register width of the highest implemented exception
 206      * level is 64 bits (ARMv8) */
 207     bool highestELIs64() const { return _highestELIs64; }
 208
 209     /** Returns the highest implemented exception level */
 210     ArmISA::ExceptionLevel
 211     highestEL() const
 212     {
 213         if (_haveSecurity)
 214             return ArmISA::EL3;
 215         if (_haveVirtualization)
 216             return ArmISA::EL2;
 217         return ArmISA::EL1;
 218     }
 219
 220     /** Returns the reset address if the highest implemented exception level is
 221      * 64 bits (ARMv8) */
 222     Addr resetAddr() const { return _resetAddr; }
 223     void setResetAddr(Addr addr) { _resetAddr = addr; }
 224
 225     /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
 226     bool haveLargeAsid64() const { return _haveLargeAsid64; }
 227
 228     /** Returns true if this system implements the transactional
 229       * memory extension (ARMv9)
 230       */
 231     bool haveTME() const { return _haveTME; }
 232
 233     /** Returns true if SVE is implemented (ARMv8) */
 234     bool haveSVE() const { return _haveSVE; }
 235
 236     /** Returns the SVE vector length at reset, in quadwords */
 237     unsigned sveVL() const { return _sveVL; }
 238
 239     /** Returns true if LSE is implemented (ARMv8.1) */
 240     bool haveLSE() const { return _haveLSE; }
 241
 242     /** Returns true if Virtualization Host Extensions is implemented */
 243     bool haveVHE() const { return _haveVHE; }
 244
 245     /** Returns true if Priviledge Access Never is implemented */
 246     bool havePAN() const { return _havePAN; }
 247
 248     /** Returns true if Priviledge Access Never is implemented */
 249     bool haveSecEL2() const { return _haveSecEL2; }
 250
 251     /** Returns the supported physical address range in bits if the highest
 252      * implemented exception level is 64 bits (ARMv8) */
 253     uint8_t physAddrRange64() const { return _physAddrRange64; }
 254
 255     /** Returns the supported physical address range in bits */
 256     uint8_t
 257     physAddrRange() const
 258     {
 259         if (_highestELIs64)
 260             return _physAddrRange64;
 261         if (_haveLPAE)
 262             return 40;
 263         return 32;
 264     }
 265
 266     /** Returns the physical address mask */
 267     Addr physAddrMask() const { return mask(physAddrRange()); }
 268
 269     /** Is Arm Semihosting support enabled? */
 270     bool haveSemihosting() const { return semihosting != nullptr; }
 271
 272     /**
 273      * Returns a valid ArmSystem pointer if using ARM ISA, it fails
 274      * otherwise.
 275      */
 276     static ArmSystem*
 277     getArmSystem(ThreadContext *tc)
 278     {
 279         assert(FullSystem);
 280         return static_cast<ArmSystem *>(tc->getSystemPtr());
 281     }
 282
 283     /** Returns true if the system of a specific thread context implements the
 284      * Security Extensions
 285      */
 286     static bool haveSecurity(ThreadContext *tc);
 287
 288     /** Returns true if the system of a specific thread context implements the
 289      * virtualization Extensions
 290      */
 291     static bool haveVirtualization(ThreadContext *tc);
 292
 293     /** Returns true if the system of a specific thread context implements the
 294      * Large Physical Address Extension
 295      */
 296     static bool haveLPAE(ThreadContext *tc);
 297
 298     /** Returns true if the register width of the highest implemented exception
 299      * level for the system of a specific thread context is 64 bits (ARMv8)
 300      */
 301     static bool highestELIs64(ThreadContext *tc);
 302
 303     /** Returns the highest implemented exception level for the system of a
 304      * specific thread context
 305      */
 306     static ArmISA::ExceptionLevel highestEL(ThreadContext *tc);
 307
 308     /** Return true if the system implements a specific exception level */
 309     static bool haveEL(ThreadContext *tc, ArmISA::ExceptionLevel el);
 310
 311     /** Returns true if the system of a specific thread context implements the
 312      * transactional memory extension (TME)
 313      */
 314     static bool haveTME(ThreadContext *tc);
 315
 316     /** Returns the reset address if the highest implemented exception level
 317      * for the system of a specific thread context is 64 bits (ARMv8)
 318      */
 319     static Addr resetAddr(ThreadContext *tc);
 320
 321     /** Returns the supported physical address range in bits for the system of a
 322      * specific thread context
 323      */
 324     static uint8_t physAddrRange(ThreadContext *tc);
 325
 326     /** Returns the physical address mask for the system of a specific thread
 327      * context
 328      */
 329     static Addr physAddrMask(ThreadContext *tc);
 330
 331     /** Returns true if ASID is 16 bits for the system of a specific thread
 332      * context while in AArch64 (ARMv8) */
 333     static bool haveLargeAsid64(ThreadContext *tc);
 334
 335     /** Is Arm Semihosting support enabled? */
 336     static bool haveSemihosting(ThreadContext *tc);
 337
 338     /** Make a Semihosting call from aarch64 */
 339     static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
 340
 341     /** Make a Semihosting call from aarch32 */
 342     static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
 343
 344     /** Make a Semihosting call from either aarch64 or aarch32 */
 345     static bool callSemihosting(ThreadContext *tc, bool gem5_ops=false);
 346
 347     /** Make a call to notify the power controller of STANDBYWFI assertion */
 348     static void callSetStandByWfi(ThreadContext *tc);
 349
 350     /** Make a call to notify the power controller of STANDBYWFI deassertion */
 351     static void callClearStandByWfi(ThreadContext *tc);
 352
 353     /**
 354      * Notify the power controller of WAKEREQUEST assertion. Returns true
 355      * if WAKEREQUEST is enabled as a power-on mechanism, and the core is now
 356      * powered, false otherwise
 357      */
 358     static bool callSetWakeRequest(ThreadContext *tc);
 359
 360     /** Notify the power controller of WAKEREQUEST deassertion */
 361     static void callClearWakeRequest(ThreadContext *tc);
 362 };
 363
 364 #endif