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43 #ifndef __ARCH_ARM_SYSTEM_HH__
44 #define __ARCH_ARM_SYSTEM_HH__
49 #include "dev/arm/generic_timer.hh"
50 #include "kern/linux/events.hh"
51 #include "params/ArmSystem.hh"
52 #include "sim/sim_object.hh"
53 #include "sim/system.hh"
57 class ArmSystem : public System
61 * PC based event to skip the dprink() call and emulate its
64 Linux::DebugPrintkEvent *debugPrintkEvent;
67 * Pointer to the bootloader object
72 * True if this system implements the Security Extensions
74 const bool _haveSecurity;
77 * True if this system implements the Large Physical Address Extension
82 * True if this system implements the virtualization Extensions
84 const bool _haveVirtualization;
87 * True if this system implements the Generic Timer extension
89 const bool _haveGenericTimer;
92 * Pointer to the Generic Timer wrapper.
94 GenericTimer *_genericTimer;
97 * True if the register width of the highest implemented exception level is
103 * Reset address if the highest implemented exception level is 64 bits
106 const Addr _resetAddr64;
109 * Supported physical address range in bits if the highest implemented
110 * exception level is 64 bits (ARMv8)
112 const uint8_t _physAddrRange64;
115 * True if ASID is 16 bits in AArch64 (ARMv8)
117 const bool _haveLargeAsid64;
120 typedef ArmSystemParams Params;
124 return dynamic_cast<const Params *>(_params);
127 ArmSystem(Params *p);
131 * Initialise the system
133 virtual void initState();
135 /** Check if an address should be uncacheable until all caches are enabled.
136 * This exits because coherence on some addresses at boot is maintained via
137 * sw coherence until the caches are enbaled. Since we don't support sw
138 * coherence operations in gem5, this is a method that allows a system
139 * type to designate certain addresses that should remain uncachebale
142 virtual bool adderBootUncacheable(Addr a) { return false; }
144 virtual Addr fixFuncEventAddr(Addr addr)
146 // Remove the low bit that thumb symbols have set
147 // but that aren't actually odd aligned
153 /** true if this a multiprocessor system */
156 /** Returns true if this system implements the Security Extensions */
157 bool haveSecurity() const { return _haveSecurity; }
159 /** Returns true if this system implements the Large Physical Address
161 bool haveLPAE() const { return _haveLPAE; }
163 /** Returns true if this system implements the virtualization
166 bool haveVirtualization() const { return _haveVirtualization; }
168 /** Returns true if this system implements the Generic Timer extension. */
169 bool haveGenericTimer() const { return _haveGenericTimer; }
171 /** Sets the pointer to the Generic Timer. */
172 void setGenericTimer(GenericTimer *generic_timer)
174 _genericTimer = generic_timer;
177 /** Returns a pointer to the system counter. */
178 GenericTimer::SystemCounter *getSystemCounter() const;
180 /** Returns a pointer to the appropriate architected timer. */
181 GenericTimer::ArchTimer *getArchTimer(int cpu_id) const;
183 /** Returns true if the register width of the highest implemented exception
184 * level is 64 bits (ARMv8) */
185 bool highestELIs64() const { return _highestELIs64; }
187 /** Returns the highest implemented exception level */
188 ExceptionLevel highestEL() const
192 // @todo: uncomment this to enable Virtualization
193 // if (_haveVirtualization)
198 /** Returns the reset address if the highest implemented exception level is
200 Addr resetAddr64() const { return _resetAddr64; }
202 /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
203 bool haveLargeAsid64() const { return _haveLargeAsid64; }
205 /** Returns the supported physical address range in bits if the highest
206 * implemented exception level is 64 bits (ARMv8) */
207 uint8_t physAddrRange64() const { return _physAddrRange64; }
209 /** Returns the supported physical address range in bits */
210 uint8_t physAddrRange() const
213 return _physAddrRange64;
219 /** Returns the physical address mask */
220 Addr physAddrMask() const
222 return mask(physAddrRange());
225 /** Returns true if the system of a specific thread context implements the
226 * Security Extensions
228 static bool haveSecurity(ThreadContext *tc);
230 /** Returns true if the system of a specific thread context implements the
231 * virtualization Extensions
233 static bool haveVirtualization(ThreadContext *tc);
235 /** Returns true if the system of a specific thread context implements the
236 * Large Physical Address Extension
238 static bool haveLPAE(ThreadContext *tc);
240 /** Returns true if the register width of the highest implemented exception
241 * level for the system of a specific thread context is 64 bits (ARMv8)
243 static bool highestELIs64(ThreadContext *tc);
245 /** Returns the highest implemented exception level for the system of a
246 * specific thread context
248 static ExceptionLevel highestEL(ThreadContext *tc);
250 /** Returns the reset address if the highest implemented exception level for
251 * the system of a specific thread context is 64 bits (ARMv8)
253 static Addr resetAddr64(ThreadContext *tc);
255 /** Returns the supported physical address range in bits for the system of a
256 * specific thread context
258 static uint8_t physAddrRange(ThreadContext *tc);
260 /** Returns the physical address mask for the system of a specific thread
263 static Addr physAddrMask(ThreadContext *tc);
265 /** Returns true if ASID is 16 bits for the system of a specific thread
266 * context while in AArch64 (ARMv8) */
267 static bool haveLargeAsid64(ThreadContext *tc);