src/arch/arm/system.hh

   1 /*
   2  * Copyright (c) 2010, 2012-2013, 2015-2019 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_SYSTEM_HH__
  42 #define __ARCH_ARM_SYSTEM_HH__
  43
  44 #include <memory>
  45 #include <string>
  46 #include <vector>
  47
  48 #include "kern/linux/events.hh"
  49 #include "params/ArmSystem.hh"
  50 #include "params/GenericArmSystem.hh"
  51 #include "sim/sim_object.hh"
  52 #include "sim/system.hh"
  53
  54 class GenericTimer;
  55 class BaseGic;
  56 class ThreadContext;
  57
  58 class ArmSystem : public System
  59 {
  60   protected:
  61     /**
  62      * PC based event to skip the dprink() call and emulate its
  63      * functionality
  64      */
  65     Linux::DebugPrintkEvent *debugPrintkEvent;
  66
  67     /** Bootloaders */
  68     std::vector<std::unique_ptr<ObjectFile>> bootLoaders;
  69
  70     /**
  71      * Pointer to the bootloader object
  72      */
  73     ObjectFile *bootldr;
  74
  75     /**
  76      * True if this system implements the Security Extensions
  77      */
  78     const bool _haveSecurity;
  79
  80     /**
  81      * True if this system implements the Large Physical Address Extension
  82      */
  83     const bool _haveLPAE;
  84
  85     /**
  86      * True if this system implements the virtualization Extensions
  87      */
  88     const bool _haveVirtualization;
  89
  90     /**
  91      * True if this system implements the Crypto Extension
  92      */
  93     const bool _haveCrypto;
  94
  95     /**
  96      * Pointer to the Generic Timer wrapper.
  97      */
  98     GenericTimer *_genericTimer;
  99     BaseGic *_gic;
 100
 101     /**
 102      * Reset address (ARMv8)
 103      */
 104     const Addr _resetAddr;
 105
 106     /**
 107      * True if the register width of the highest implemented exception level is
 108      * 64 bits (ARMv8)
 109      */
 110     bool _highestELIs64;
 111
 112     /**
 113      * Supported physical address range in bits if the highest implemented
 114      * exception level is 64 bits (ARMv8)
 115      */
 116     const uint8_t _physAddrRange64;
 117
 118     /**
 119      * True if ASID is 16 bits in AArch64 (ARMv8)
 120      */
 121     const bool _haveLargeAsid64;
 122
 123     /**
 124      * True if SVE is implemented (ARMv8)
 125      */
 126     const bool _haveSVE;
 127
 128     /** SVE vector length at reset, in quadwords */
 129     const unsigned _sveVL;
 130
 131     /**
 132      * True if LSE is implemented (ARMv8.1)
 133      */
 134     const bool _haveLSE;
 135
 136     /** True if Priviledge Access Never is implemented */
 137     const unsigned _havePAN;
 138
 139     /**
 140      * True if the Semihosting interface is enabled.
 141      */
 142     ArmSemihosting *const semihosting;
 143
 144   protected:
 145     /**
 146      * Get a boot loader that matches the kernel.
 147      *
 148      * @param obj Kernel binary
 149      * @return Pointer to boot loader ObjectFile or nullptr if there
 150      *         is no matching boot loader.
 151      */
 152     ObjectFile *getBootLoader(ObjectFile *const obj);
 153
 154   public:
 155     typedef ArmSystemParams Params;
 156     const Params *
 157     params() const
 158     {
 159         return dynamic_cast<const Params *>(_params);
 160     }
 161
 162     ArmSystem(Params *p);
 163     ~ArmSystem();
 164
 165     /**
 166      * Initialise the system
 167      */
 168     virtual void initState();
 169
 170     virtual Addr fixFuncEventAddr(Addr addr)
 171     {
 172         // Remove the low bit that thumb symbols have set
 173         // but that aren't actually odd aligned
 174         if (addr & 0x1)
 175             return addr & ~1;
 176         return addr;
 177     }
 178
 179     /** true if this a multiprocessor system */
 180     bool multiProc;
 181
 182     /** Returns true if this system implements the Security Extensions */
 183     bool haveSecurity() const { return _haveSecurity; }
 184
 185     /** Returns true if this system implements the Large Physical Address
 186      * Extension */
 187     bool haveLPAE() const { return _haveLPAE; }
 188
 189     /** Returns true if this system implements the virtualization
 190       * Extensions
 191       */
 192     bool haveVirtualization() const { return _haveVirtualization; }
 193
 194     /** Returns true if this system implements the Crypto
 195       * Extension
 196       */
 197     bool haveCrypto() const { return _haveCrypto; }
 198
 199     /** Sets the pointer to the Generic Timer. */
 200     void setGenericTimer(GenericTimer *generic_timer)
 201     {
 202         _genericTimer = generic_timer;
 203     }
 204
 205     /** Sets the pointer to the GIC. */
 206     void setGIC(BaseGic *gic)
 207     {
 208         _gic = gic;
 209     }
 210
 211     /** Get a pointer to the system's generic timer model */
 212     GenericTimer *getGenericTimer() const { return _genericTimer; }
 213
 214     /** Get a pointer to the system's GIC */
 215     BaseGic *getGIC() const { return _gic; }
 216
 217     /** Returns true if the register width of the highest implemented exception
 218      * level is 64 bits (ARMv8) */
 219     bool highestELIs64() const { return _highestELIs64; }
 220
 221     /** Returns the highest implemented exception level */
 222     ExceptionLevel highestEL() const
 223     {
 224         if (_haveSecurity)
 225             return EL3;
 226         if (_haveVirtualization)
 227             return EL2;
 228         return EL1;
 229     }
 230
 231     /** Returns the reset address if the highest implemented exception level is
 232      * 64 bits (ARMv8) */
 233     Addr resetAddr() const { return _resetAddr; }
 234
 235     /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
 236     bool haveLargeAsid64() const { return _haveLargeAsid64; }
 237
 238     /** Returns true if SVE is implemented (ARMv8) */
 239     bool haveSVE() const { return _haveSVE; }
 240
 241     /** Returns the SVE vector length at reset, in quadwords */
 242     unsigned sveVL() const { return _sveVL; }
 243
 244     /** Returns true if LSE is implemented (ARMv8.1) */
 245     bool haveLSE() const { return _haveLSE; }
 246
 247     /** Returns true if Priviledge Access Never is implemented */
 248     bool havePAN() const { return _havePAN; }
 249
 250     /** Returns the supported physical address range in bits if the highest
 251      * implemented exception level is 64 bits (ARMv8) */
 252     uint8_t physAddrRange64() const { return _physAddrRange64; }
 253
 254     /** Returns the supported physical address range in bits */
 255     uint8_t physAddrRange() const
 256     {
 257         if (_highestELIs64)
 258             return _physAddrRange64;
 259         if (_haveLPAE)
 260             return 40;
 261         return 32;
 262     }
 263
 264     /** Returns the physical address mask */
 265     Addr physAddrMask() const
 266     {
 267         return mask(physAddrRange());
 268     }
 269
 270     /** Is Arm Semihosting support enabled? */
 271     bool haveSemihosting() const { return semihosting != nullptr; }
 272
 273     /**
 274      * Casts the provided System object into a valid ArmSystem, it fails
 275      * otherwise.
 276      * @param sys System object to cast
 277      */
 278     static ArmSystem *getArmSystem(System *sys);
 279
 280     /**
 281      * Returns a valid ArmSystem pointer if using ARM ISA, it fails
 282      * otherwise.
 283      */
 284     static ArmSystem* getArmSystem(ThreadContext *tc);
 285
 286     /** Returns true if the system of a specific thread context implements the
 287      * Security Extensions
 288      */
 289     static bool haveSecurity(ThreadContext *tc);
 290
 291     /** Returns true if the system of a specific thread context implements the
 292      * virtualization Extensions
 293      */
 294     static bool haveVirtualization(ThreadContext *tc);
 295
 296     /** Returns true if the system of a specific thread context implements the
 297      * Large Physical Address Extension
 298      */
 299     static bool haveLPAE(ThreadContext *tc);
 300
 301     /** Returns true if the register width of the highest implemented exception
 302      * level for the system of a specific thread context is 64 bits (ARMv8)
 303      */
 304     static bool highestELIs64(ThreadContext *tc);
 305
 306     /** Returns the highest implemented exception level for the system of a
 307      * specific thread context
 308      */
 309     static ExceptionLevel highestEL(ThreadContext *tc);
 310
 311     /** Return true if the system implements a specific exception level */
 312     static bool haveEL(ThreadContext *tc, ExceptionLevel el);
 313
 314     /** Returns the reset address if the highest implemented exception level
 315      * for the system of a specific thread context is 64 bits (ARMv8)
 316      */
 317     static Addr resetAddr(ThreadContext *tc);
 318
 319     /** Returns the supported physical address range in bits for the system of a
 320      * specific thread context
 321      */
 322     static uint8_t physAddrRange(ThreadContext *tc);
 323
 324     /** Returns the physical address mask for the system of a specific thread
 325      * context
 326      */
 327     static Addr physAddrMask(ThreadContext *tc);
 328
 329     /** Returns true if ASID is 16 bits for the system of a specific thread
 330      * context while in AArch64 (ARMv8) */
 331     static bool haveLargeAsid64(ThreadContext *tc);
 332
 333     /** Is Arm Semihosting support enabled? */
 334     static bool haveSemihosting(ThreadContext *tc);
 335
 336     /** Make a Semihosting call from aarch64 */
 337     static uint64_t callSemihosting64(ThreadContext *tc,
 338                                       uint32_t op, uint64_t param);
 339
 340     /** Make a Semihosting call from aarch32 */
 341     static uint32_t callSemihosting32(ThreadContext *tc,
 342                                       uint32_t op, uint32_t param);
 343 };
 344
 345 class GenericArmSystem : public ArmSystem
 346 {
 347   public:
 348     typedef GenericArmSystemParams Params;
 349     const Params *
 350     params() const
 351     {
 352         return dynamic_cast<const Params *>(_params);
 353     }
 354
 355     GenericArmSystem(Params *p) : ArmSystem(p) {};
 356     virtual ~GenericArmSystem() {};
 357
 358     /**
 359      * Initialise the system
 360      */
 361     virtual void initState();
 362 };
 363
 364 #endif