src/arch/arm/system.hh

   1 /*
   2  * Copyright (c) 2010, 2012-2013, 2015-2020 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Copyright (c) 2002-2005 The Regents of The University of Michigan
  15  * All rights reserved.
  16  *
  17  * Redistribution and use in source and binary forms, with or without
  18  * modification, are permitted provided that the following conditions are
  19  * met: redistributions of source code must retain the above copyright
  20  * notice, this list of conditions and the following disclaimer;
  21  * redistributions in binary form must reproduce the above copyright
  22  * notice, this list of conditions and the following disclaimer in the
  23  * documentation and/or other materials provided with the distribution;
  24  * neither the name of the copyright holders nor the names of its
  25  * contributors may be used to endorse or promote products derived from
  26  * this software without specific prior written permission.
  27  *
  28  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  29  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  30  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  31  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  32  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  33  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  34  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  35  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  36  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  37  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  38  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  39  */
  40
  41 #ifndef __ARCH_ARM_SYSTEM_HH__
  42 #define __ARCH_ARM_SYSTEM_HH__
  43
  44 #include <memory>
  45 #include <string>
  46 #include <vector>
  47
  48 #include "kern/linux/events.hh"
  49 #include "params/ArmSystem.hh"
  50 #include "sim/full_system.hh"
  51 #include "sim/sim_object.hh"
  52 #include "sim/system.hh"
  53
  54 class GenericTimer;
  55 class BaseGic;
  56 class FVPBasePwrCtrl;
  57 class ThreadContext;
  58
  59 class ArmSystem : public System
  60 {
  61   protected:
  62     /**
  63      * True if this system implements the Security Extensions
  64      */
  65     const bool _haveSecurity;
  66
  67     /**
  68      * True if this system implements the Large Physical Address Extension
  69      */
  70     const bool _haveLPAE;
  71
  72     /**
  73      * True if this system implements the virtualization Extensions
  74      */
  75     const bool _haveVirtualization;
  76
  77     /**
  78      * True if this system implements the Crypto Extension
  79      */
  80     const bool _haveCrypto;
  81
  82     /**
  83      * Pointer to the Generic Timer wrapper.
  84      */
  85     GenericTimer *_genericTimer;
  86     BaseGic *_gic;
  87
  88     /**
  89      * Pointer to the Power Controller (if any)
  90      */
  91     FVPBasePwrCtrl *_pwrCtrl;
  92
  93     /**
  94      * Reset address (ARMv8)
  95      */
  96     Addr _resetAddr;
  97
  98     /**
  99      * True if the register width of the highest implemented exception level is
 100      * 64 bits (ARMv8)
 101      */
 102     bool _highestELIs64;
 103
 104     /**
 105      * Supported physical address range in bits if the highest implemented
 106      * exception level is 64 bits (ARMv8)
 107      */
 108     const uint8_t _physAddrRange64;
 109
 110     /**
 111      * True if ASID is 16 bits in AArch64 (ARMv8)
 112      */
 113     const bool _haveLargeAsid64;
 114
 115     /**
 116      * True if SVE is implemented (ARMv8)
 117      */
 118     const bool _haveSVE;
 119
 120     /** SVE vector length at reset, in quadwords */
 121     const unsigned _sveVL;
 122
 123     /**
 124      * True if LSE is implemented (ARMv8.1)
 125      */
 126     const bool _haveLSE;
 127
 128     /** True if Priviledge Access Never is implemented */
 129     const unsigned _havePAN;
 130
 131     /**
 132      * True if the Semihosting interface is enabled.
 133      */
 134     ArmSemihosting *const semihosting;
 135
 136   public:
 137     typedef ArmSystemParams Params;
 138     const Params *
 139     params() const
 140     {
 141         return dynamic_cast<const Params *>(_params);
 142     }
 143
 144     ArmSystem(Params *p);
 145
 146     Addr
 147     fixFuncEventAddr(Addr addr) override
 148     {
 149         // Remove the low bit that thumb symbols have set
 150         // but that aren't actually odd aligned
 151         return addr & ~1;
 152     }
 153
 154     /** true if this a multiprocessor system */
 155     bool multiProc;
 156
 157     /** Returns true if this system implements the Security Extensions */
 158     bool haveSecurity() const { return _haveSecurity; }
 159
 160     /** Returns true if this system implements the Large Physical Address
 161      * Extension */
 162     bool haveLPAE() const { return _haveLPAE; }
 163
 164     /** Returns true if this system implements the virtualization
 165       * Extensions
 166       */
 167     bool haveVirtualization() const { return _haveVirtualization; }
 168
 169     /** Returns true if this system implements the Crypto
 170       * Extension
 171       */
 172     bool haveCrypto() const { return _haveCrypto; }
 173
 174     /** Sets the pointer to the Generic Timer. */
 175     void
 176     setGenericTimer(GenericTimer *generic_timer)
 177     {
 178         _genericTimer = generic_timer;
 179     }
 180
 181     /** Sets the pointer to the GIC. */
 182     void setGIC(BaseGic *gic) { _gic = gic; }
 183
 184     /** Sets the pointer to the Power Controller */
 185     void setPowerController(FVPBasePwrCtrl *pwr_ctrl)
 186     {
 187         _pwrCtrl = pwr_ctrl;
 188     }
 189
 190     /** Get a pointer to the system's generic timer model */
 191     GenericTimer *getGenericTimer() const { return _genericTimer; }
 192
 193     /** Get a pointer to the system's GIC */
 194     BaseGic *getGIC() const { return _gic; }
 195
 196     /** Get a pointer to the system's power controller */
 197     FVPBasePwrCtrl *getPowerController() const { return _pwrCtrl; }
 198
 199     /** Returns true if the register width of the highest implemented exception
 200      * level is 64 bits (ARMv8) */
 201     bool highestELIs64() const { return _highestELIs64; }
 202
 203     /** Returns the highest implemented exception level */
 204     ExceptionLevel
 205     highestEL() const
 206     {
 207         if (_haveSecurity)
 208             return EL3;
 209         if (_haveVirtualization)
 210             return EL2;
 211         return EL1;
 212     }
 213
 214     /** Returns the reset address if the highest implemented exception level is
 215      * 64 bits (ARMv8) */
 216     Addr resetAddr() const { return _resetAddr; }
 217     void setResetAddr(Addr addr) { _resetAddr = addr; }
 218
 219     /** Returns true if ASID is 16 bits in AArch64 (ARMv8) */
 220     bool haveLargeAsid64() const { return _haveLargeAsid64; }
 221
 222     /** Returns true if SVE is implemented (ARMv8) */
 223     bool haveSVE() const { return _haveSVE; }
 224
 225     /** Returns the SVE vector length at reset, in quadwords */
 226     unsigned sveVL() const { return _sveVL; }
 227
 228     /** Returns true if LSE is implemented (ARMv8.1) */
 229     bool haveLSE() const { return _haveLSE; }
 230
 231     /** Returns true if Priviledge Access Never is implemented */
 232     bool havePAN() const { return _havePAN; }
 233
 234     /** Returns the supported physical address range in bits if the highest
 235      * implemented exception level is 64 bits (ARMv8) */
 236     uint8_t physAddrRange64() const { return _physAddrRange64; }
 237
 238     /** Returns the supported physical address range in bits */
 239     uint8_t
 240     physAddrRange() const
 241     {
 242         if (_highestELIs64)
 243             return _physAddrRange64;
 244         if (_haveLPAE)
 245             return 40;
 246         return 32;
 247     }
 248
 249     /** Returns the physical address mask */
 250     Addr physAddrMask() const { return mask(physAddrRange()); }
 251
 252     /** Is Arm Semihosting support enabled? */
 253     bool haveSemihosting() const { return semihosting != nullptr; }
 254
 255     /**
 256      * Returns a valid ArmSystem pointer if using ARM ISA, it fails
 257      * otherwise.
 258      */
 259     static ArmSystem*
 260     getArmSystem(ThreadContext *tc)
 261     {
 262         assert(FullSystem);
 263         return static_cast<ArmSystem *>(tc->getSystemPtr());
 264     }
 265
 266     /** Returns true if the system of a specific thread context implements the
 267      * Security Extensions
 268      */
 269     static bool haveSecurity(ThreadContext *tc);
 270
 271     /** Returns true if the system of a specific thread context implements the
 272      * virtualization Extensions
 273      */
 274     static bool haveVirtualization(ThreadContext *tc);
 275
 276     /** Returns true if the system of a specific thread context implements the
 277      * Large Physical Address Extension
 278      */
 279     static bool haveLPAE(ThreadContext *tc);
 280
 281     /** Returns true if the register width of the highest implemented exception
 282      * level for the system of a specific thread context is 64 bits (ARMv8)
 283      */
 284     static bool highestELIs64(ThreadContext *tc);
 285
 286     /** Returns the highest implemented exception level for the system of a
 287      * specific thread context
 288      */
 289     static ExceptionLevel highestEL(ThreadContext *tc);
 290
 291     /** Return true if the system implements a specific exception level */
 292     static bool haveEL(ThreadContext *tc, ExceptionLevel el);
 293
 294     /** Returns the reset address if the highest implemented exception level
 295      * for the system of a specific thread context is 64 bits (ARMv8)
 296      */
 297     static Addr resetAddr(ThreadContext *tc);
 298
 299     /** Returns the supported physical address range in bits for the system of a
 300      * specific thread context
 301      */
 302     static uint8_t physAddrRange(ThreadContext *tc);
 303
 304     /** Returns the physical address mask for the system of a specific thread
 305      * context
 306      */
 307     static Addr physAddrMask(ThreadContext *tc);
 308
 309     /** Returns true if ASID is 16 bits for the system of a specific thread
 310      * context while in AArch64 (ARMv8) */
 311     static bool haveLargeAsid64(ThreadContext *tc);
 312
 313     /** Is Arm Semihosting support enabled? */
 314     static bool haveSemihosting(ThreadContext *tc);
 315
 316     /** Make a Semihosting call from aarch64 */
 317     static bool callSemihosting64(ThreadContext *tc, bool gem5_ops=false);
 318
 319     /** Make a Semihosting call from aarch32 */
 320     static bool callSemihosting32(ThreadContext *tc, bool gem5_ops=false);
 321
 322     /** Make a call to notify the power controller of STANDBYWFI assertion */
 323     static void callSetStandByWfi(ThreadContext *tc);
 324
 325     /** Make a call to notify the power controller of STANDBYWFI deassertion */
 326     static void callClearStandByWfi(ThreadContext *tc);
 327 };
 328
 329 #endif