2 * Copyright (c) 2010, 2012-2016 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
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17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/arm/table_walker.hh"
44 #include "arch/arm/faults.hh"
45 #include "arch/arm/stage2_mmu.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlb.hh"
48 #include "cpu/base.hh"
49 #include "cpu/thread_context.hh"
50 #include "debug/Checkpoint.hh"
51 #include "debug/Drain.hh"
52 #include "debug/TLB.hh"
53 #include "debug/TLBVerbose.hh"
54 #include "dev/dma_device.hh"
55 #include "sim/system.hh"
57 using namespace ArmISA
;
59 TableWalker::TableWalker(const Params
*p
)
61 stage2Mmu(NULL
), port(NULL
), masterId(Request::invldMasterId
),
62 isStage2(p
->is_stage2
), tlb(NULL
),
63 currState(NULL
), pending(false),
64 numSquashable(p
->num_squash_per_cycle
),
66 pendingChangeTick(curTick()),
67 doL1DescEvent(this), doL2DescEvent(this),
68 doL0LongDescEvent(this), doL1LongDescEvent(this), doL2LongDescEvent(this),
69 doL3LongDescEvent(this),
74 // Cache system-level properties
76 ArmSystem
*armSys
= dynamic_cast<ArmSystem
*>(p
->sys
);
78 haveSecurity
= armSys
->haveSecurity();
79 _haveLPAE
= armSys
->haveLPAE();
80 _haveVirtualization
= armSys
->haveVirtualization();
81 physAddrRange
= armSys
->physAddrRange();
82 _haveLargeAsid64
= armSys
->haveLargeAsid64();
84 haveSecurity
= _haveLPAE
= _haveVirtualization
= false;
85 _haveLargeAsid64
= false;
91 TableWalker::~TableWalker()
97 TableWalker::setMMU(Stage2MMU
*m
, MasterID master_id
)
100 port
= &m
->getPort();
101 masterId
= master_id
;
107 fatal_if(!stage2Mmu
, "Table walker must have a valid stage-2 MMU\n");
108 fatal_if(!port
, "Table walker must have a valid port\n");
109 fatal_if(!tlb
, "Table walker must have a valid TLB\n");
113 TableWalker::getMasterPort(const std::string
&if_name
, PortID idx
)
115 if (if_name
== "port") {
119 fatal("Cannot access table walker port through stage-two walker\n");
122 return MemObject::getMasterPort(if_name
, idx
);
125 TableWalker::WalkerState::WalkerState() :
126 tc(nullptr), aarch64(false), el(EL0
), physAddrRange(0), req(nullptr),
127 asid(0), vmid(0), isHyp(false), transState(nullptr),
128 vaddr(0), vaddr_tainted(0), isWrite(false), isFetch(false), isSecure(false),
129 secureLookup(false), rwTable(false), userTable(false), xnTable(false),
130 pxnTable(false), stage2Req(false), doingStage2(false),
131 stage2Tran(nullptr), timing(false), functional(false),
132 mode(BaseTLB::Read
), tranType(TLB::NormalTran
), l2Desc(l1Desc
),
133 delayed(false), tableWalker(nullptr)
138 TableWalker::completeDrain()
140 if (drainState() == DrainState::Draining
&&
141 stateQueues
[L1
].empty() && stateQueues
[L2
].empty() &&
142 pendingQueue
.empty()) {
144 DPRINTF(Drain
, "TableWalker done draining, processing drain event\n");
152 bool state_queues_not_empty
= false;
154 for (int i
= 0; i
< MAX_LOOKUP_LEVELS
; ++i
) {
155 if (!stateQueues
[i
].empty()) {
156 state_queues_not_empty
= true;
161 if (state_queues_not_empty
|| pendingQueue
.size()) {
162 DPRINTF(Drain
, "TableWalker not drained\n");
163 return DrainState::Draining
;
165 DPRINTF(Drain
, "TableWalker free, no need to drain\n");
166 return DrainState::Drained
;
171 TableWalker::drainResume()
173 if (params()->sys
->isTimingMode() && currState
) {
181 TableWalker::walk(RequestPtr _req
, ThreadContext
*_tc
, uint16_t _asid
,
182 uint8_t _vmid
, bool _isHyp
, TLB::Mode _mode
,
183 TLB::Translation
*_trans
, bool _timing
, bool _functional
,
184 bool secure
, TLB::ArmTranslationType tranType
)
186 assert(!(_functional
&& _timing
));
189 WalkerState
*savedCurrState
= NULL
;
191 if (!currState
&& !_functional
) {
192 // For atomic mode, a new WalkerState instance should be only created
193 // once per TLB. For timing mode, a new instance is generated for every
195 DPRINTF(TLBVerbose
, "creating new instance of WalkerState\n");
197 currState
= new WalkerState();
198 currState
->tableWalker
= this;
199 } else if (_functional
) {
200 // If we are mixing functional mode with timing (or even
201 // atomic), we need to to be careful and clean up after
202 // ourselves to not risk getting into an inconsistent state.
203 DPRINTF(TLBVerbose
, "creating functional instance of WalkerState\n");
204 savedCurrState
= currState
;
205 currState
= new WalkerState();
206 currState
->tableWalker
= this;
207 } else if (_timing
) {
208 // This is a translation that was completed and then faulted again
209 // because some underlying parameters that affect the translation
210 // changed out from under us (e.g. asid). It will either be a
211 // misprediction, in which case nothing will happen or we'll use
212 // this fault to re-execute the faulting instruction which should clean
214 if (currState
->vaddr_tainted
== _req
->getVaddr()) {
215 ++statSquashedBefore
;
216 return std::make_shared
<ReExec
>();
221 currState
->startTime
= curTick();
223 // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672
224 // aarch32/translation/translation/AArch32.TranslateAddress dictates
225 // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
226 currState
->aarch64
= isStage2
|| opModeIs64(currOpMode(_tc
)) ||
227 ((currEL(_tc
) == EL0
) && ELIs64(_tc
, EL1
));
228 currState
->el
= currEL(_tc
);
229 currState
->transState
= _trans
;
230 currState
->req
= _req
;
231 currState
->fault
= NoFault
;
232 currState
->asid
= _asid
;
233 currState
->vmid
= _vmid
;
234 currState
->isHyp
= _isHyp
;
235 currState
->timing
= _timing
;
236 currState
->functional
= _functional
;
237 currState
->mode
= _mode
;
238 currState
->tranType
= tranType
;
239 currState
->isSecure
= secure
;
240 currState
->physAddrRange
= physAddrRange
;
242 /** @todo These should be cached or grabbed from cached copies in
243 the TLB, all these miscreg reads are expensive */
244 currState
->vaddr_tainted
= currState
->req
->getVaddr();
245 if (currState
->aarch64
)
246 currState
->vaddr
= purifyTaggedAddr(currState
->vaddr_tainted
,
247 currState
->tc
, currState
->el
);
249 currState
->vaddr
= currState
->vaddr_tainted
;
251 if (currState
->aarch64
) {
252 switch (currState
->el
) {
255 currState
->sctlr
= currState
->tc
->readMiscReg(MISCREG_SCTLR_EL1
);
256 currState
->tcr
= currState
->tc
->readMiscReg(MISCREG_TCR_EL1
);
259 assert(_haveVirtualization
);
260 currState
->sctlr
= currState
->tc
->readMiscReg(MISCREG_SCTLR_EL2
);
261 currState
->tcr
= currState
->tc
->readMiscReg(MISCREG_TCR_EL2
);
264 assert(haveSecurity
);
265 currState
->sctlr
= currState
->tc
->readMiscReg(MISCREG_SCTLR_EL3
);
266 currState
->tcr
= currState
->tc
->readMiscReg(MISCREG_TCR_EL3
);
269 panic("Invalid exception level");
273 currState
->sctlr
= currState
->tc
->readMiscReg(flattenMiscRegNsBanked(
274 MISCREG_SCTLR
, currState
->tc
, !currState
->isSecure
));
275 currState
->ttbcr
= currState
->tc
->readMiscReg(flattenMiscRegNsBanked(
276 MISCREG_TTBCR
, currState
->tc
, !currState
->isSecure
));
277 currState
->htcr
= currState
->tc
->readMiscReg(MISCREG_HTCR
);
278 currState
->hcr
= currState
->tc
->readMiscReg(MISCREG_HCR
);
279 currState
->vtcr
= currState
->tc
->readMiscReg(MISCREG_VTCR
);
281 sctlr
= currState
->sctlr
;
283 currState
->isFetch
= (currState
->mode
== TLB::Execute
);
284 currState
->isWrite
= (currState
->mode
== TLB::Write
);
286 statRequestOrigin
[REQUESTED
][currState
->isFetch
]++;
288 // We only do a second stage of translation if we're not secure, or in
289 // hyp mode, the second stage MMU is enabled, and this table walker
290 // instance is the first stage.
291 currState
->doingStage2
= false;
292 // @todo: for now disable this in AArch64 (HCR is not set)
293 currState
->stage2Req
= !currState
->aarch64
&& currState
->hcr
.vm
&&
294 !isStage2
&& !currState
->isSecure
&& !currState
->isHyp
;
296 bool long_desc_format
= currState
->aarch64
|| _isHyp
|| isStage2
||
297 longDescFormatInUse(currState
->tc
);
299 if (long_desc_format
) {
300 // Helper variables used for hierarchical permissions
301 currState
->secureLookup
= currState
->isSecure
;
302 currState
->rwTable
= true;
303 currState
->userTable
= true;
304 currState
->xnTable
= false;
305 currState
->pxnTable
= false;
307 ++statWalksLongDescriptor
;
309 ++statWalksShortDescriptor
;
312 if (!currState
->timing
) {
313 Fault fault
= NoFault
;
314 if (currState
->aarch64
)
315 fault
= processWalkAArch64();
316 else if (long_desc_format
)
317 fault
= processWalkLPAE();
319 fault
= processWalk();
321 // If this was a functional non-timing access restore state to
323 if (currState
->functional
) {
325 currState
= savedCurrState
;
330 if (pending
|| pendingQueue
.size()) {
331 pendingQueue
.push_back(currState
);
337 if (currState
->aarch64
)
338 return processWalkAArch64();
339 else if (long_desc_format
)
340 return processWalkLPAE();
342 return processWalk();
349 TableWalker::processWalkWrapper()
352 assert(pendingQueue
.size());
354 currState
= pendingQueue
.front();
356 ExceptionLevel target_el
= EL0
;
357 if (currState
->aarch64
)
358 target_el
= currEL(currState
->tc
);
362 // Check if a previous walk filled this request already
363 // @TODO Should this always be the TLB or should we look in the stage2 TLB?
364 TlbEntry
* te
= tlb
->lookup(currState
->vaddr
, currState
->asid
,
365 currState
->vmid
, currState
->isHyp
, currState
->isSecure
, true, false,
368 // Check if we still need to have a walk for this request. If the requesting
369 // instruction has been squashed, or a previous walk has filled the TLB with
370 // a match, we just want to get rid of the walk. The latter could happen
371 // when there are multiple outstanding misses to a single page and a
372 // previous request has been successfully translated.
373 if (!currState
->transState
->squashed() && !te
) {
374 // We've got a valid request, lets process it
376 pendingQueue
.pop_front();
377 // Keep currState in case one of the processWalk... calls NULLs it
378 WalkerState
*curr_state_copy
= currState
;
380 if (currState
->aarch64
)
381 f
= processWalkAArch64();
382 else if (longDescFormatInUse(currState
->tc
) ||
383 currState
->isHyp
|| isStage2
)
384 f
= processWalkLPAE();
389 curr_state_copy
->transState
->finish(f
, curr_state_copy
->req
,
390 curr_state_copy
->tc
, curr_state_copy
->mode
);
392 delete curr_state_copy
;
398 // If the instruction that we were translating for has been
399 // squashed we shouldn't bother.
400 unsigned num_squashed
= 0;
401 ThreadContext
*tc
= currState
->tc
;
402 while ((num_squashed
< numSquashable
) && currState
&&
403 (currState
->transState
->squashed() || te
)) {
404 pendingQueue
.pop_front();
406 statSquashedBefore
++;
408 DPRINTF(TLB
, "Squashing table walk for address %#x\n",
409 currState
->vaddr_tainted
);
411 if (currState
->transState
->squashed()) {
412 // finish the translation which will delete the translation object
413 currState
->transState
->finish(
414 std::make_shared
<UnimpFault
>("Squashed Inst"),
415 currState
->req
, currState
->tc
, currState
->mode
);
417 // translate the request now that we know it will work
418 statWalkServiceTime
.sample(curTick() - currState
->startTime
);
419 tlb
->translateTiming(currState
->req
, currState
->tc
,
420 currState
->transState
, currState
->mode
);
424 // delete the current request
427 // peak at the next one
428 if (pendingQueue
.size()) {
429 currState
= pendingQueue
.front();
430 te
= tlb
->lookup(currState
->vaddr
, currState
->asid
,
431 currState
->vmid
, currState
->isHyp
, currState
->isSecure
, true,
434 // Terminate the loop, nothing more to do
440 // if we still have pending translations, schedule more work
446 TableWalker::processWalk()
450 // If translation isn't enabled, we shouldn't be here
451 assert(currState
->sctlr
.m
|| isStage2
);
453 DPRINTF(TLB
, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n",
454 currState
->vaddr_tainted
, currState
->ttbcr
, mbits(currState
->vaddr
, 31,
455 32 - currState
->ttbcr
.n
));
457 statWalkWaitTime
.sample(curTick() - currState
->startTime
);
459 if (currState
->ttbcr
.n
== 0 || !mbits(currState
->vaddr
, 31,
460 32 - currState
->ttbcr
.n
)) {
461 DPRINTF(TLB
, " - Selecting TTBR0\n");
462 // Check if table walk is allowed when Security Extensions are enabled
463 if (haveSecurity
&& currState
->ttbcr
.pd0
) {
464 if (currState
->isFetch
)
465 return std::make_shared
<PrefetchAbort
>(
466 currState
->vaddr_tainted
,
467 ArmFault::TranslationLL
+ L1
,
471 return std::make_shared
<DataAbort
>(
472 currState
->vaddr_tainted
,
473 TlbEntry::DomainType::NoAccess
, currState
->isWrite
,
474 ArmFault::TranslationLL
+ L1
, isStage2
,
477 ttbr
= currState
->tc
->readMiscReg(flattenMiscRegNsBanked(
478 MISCREG_TTBR0
, currState
->tc
, !currState
->isSecure
));
480 DPRINTF(TLB
, " - Selecting TTBR1\n");
481 // Check if table walk is allowed when Security Extensions are enabled
482 if (haveSecurity
&& currState
->ttbcr
.pd1
) {
483 if (currState
->isFetch
)
484 return std::make_shared
<PrefetchAbort
>(
485 currState
->vaddr_tainted
,
486 ArmFault::TranslationLL
+ L1
,
490 return std::make_shared
<DataAbort
>(
491 currState
->vaddr_tainted
,
492 TlbEntry::DomainType::NoAccess
, currState
->isWrite
,
493 ArmFault::TranslationLL
+ L1
, isStage2
,
496 ttbr
= currState
->tc
->readMiscReg(flattenMiscRegNsBanked(
497 MISCREG_TTBR1
, currState
->tc
, !currState
->isSecure
));
498 currState
->ttbcr
.n
= 0;
501 Addr l1desc_addr
= mbits(ttbr
, 31, 14 - currState
->ttbcr
.n
) |
502 (bits(currState
->vaddr
, 31 - currState
->ttbcr
.n
, 20) << 2);
503 DPRINTF(TLB
, " - Descriptor at address %#x (%s)\n", l1desc_addr
,
504 currState
->isSecure
? "s" : "ns");
506 // Trickbox address check
508 f
= testWalk(l1desc_addr
, sizeof(uint32_t),
509 TlbEntry::DomainType::NoAccess
, L1
);
511 DPRINTF(TLB
, "Trickbox check caused fault on %#x\n", currState
->vaddr_tainted
);
512 if (currState
->timing
) {
514 nextWalk(currState
->tc
);
517 currState
->tc
= NULL
;
518 currState
->req
= NULL
;
523 Request::Flags flag
= Request::PT_WALK
;
524 if (currState
->sctlr
.c
== 0) {
525 flag
.set(Request::UNCACHEABLE
);
528 if (currState
->isSecure
) {
529 flag
.set(Request::SECURE
);
533 delayed
= fetchDescriptor(l1desc_addr
, (uint8_t*)&currState
->l1Desc
.data
,
534 sizeof(uint32_t), flag
, L1
, &doL1DescEvent
,
535 &TableWalker::doL1Descriptor
);
537 f
= currState
->fault
;
544 TableWalker::processWalkLPAE()
546 Addr ttbr
, ttbr0_max
, ttbr1_min
, desc_addr
;
548 LookupLevel start_lookup_level
= L1
;
550 DPRINTF(TLB
, "Beginning table walk for address %#x, TTBCR: %#x\n",
551 currState
->vaddr_tainted
, currState
->ttbcr
);
553 statWalkWaitTime
.sample(curTick() - currState
->startTime
);
555 Request::Flags flag
= Request::PT_WALK
;
556 if (currState
->isSecure
)
557 flag
.set(Request::SECURE
);
559 // work out which base address register to use, if in hyp mode we always
562 DPRINTF(TLB
, " - Selecting VTTBR (long-desc.)\n");
563 ttbr
= currState
->tc
->readMiscReg(MISCREG_VTTBR
);
564 tsz
= sext
<4>(currState
->vtcr
.t0sz
);
565 start_lookup_level
= currState
->vtcr
.sl0
? L1
: L2
;
566 } else if (currState
->isHyp
) {
567 DPRINTF(TLB
, " - Selecting HTTBR (long-desc.)\n");
568 ttbr
= currState
->tc
->readMiscReg(MISCREG_HTTBR
);
569 tsz
= currState
->htcr
.t0sz
;
571 assert(longDescFormatInUse(currState
->tc
));
573 // Determine boundaries of TTBR0/1 regions
574 if (currState
->ttbcr
.t0sz
)
575 ttbr0_max
= (1ULL << (32 - currState
->ttbcr
.t0sz
)) - 1;
576 else if (currState
->ttbcr
.t1sz
)
577 ttbr0_max
= (1ULL << 32) -
578 (1ULL << (32 - currState
->ttbcr
.t1sz
)) - 1;
580 ttbr0_max
= (1ULL << 32) - 1;
581 if (currState
->ttbcr
.t1sz
)
582 ttbr1_min
= (1ULL << 32) - (1ULL << (32 - currState
->ttbcr
.t1sz
));
584 ttbr1_min
= (1ULL << (32 - currState
->ttbcr
.t0sz
));
586 // The following code snippet selects the appropriate translation table base
587 // address (TTBR0 or TTBR1) and the appropriate starting lookup level
588 // depending on the address range supported by the translation table (ARM
589 // ARM issue C B3.6.4)
590 if (currState
->vaddr
<= ttbr0_max
) {
591 DPRINTF(TLB
, " - Selecting TTBR0 (long-desc.)\n");
592 // Check if table walk is allowed
593 if (currState
->ttbcr
.epd0
) {
594 if (currState
->isFetch
)
595 return std::make_shared
<PrefetchAbort
>(
596 currState
->vaddr_tainted
,
597 ArmFault::TranslationLL
+ L1
,
601 return std::make_shared
<DataAbort
>(
602 currState
->vaddr_tainted
,
603 TlbEntry::DomainType::NoAccess
,
605 ArmFault::TranslationLL
+ L1
,
609 ttbr
= currState
->tc
->readMiscReg(flattenMiscRegNsBanked(
610 MISCREG_TTBR0
, currState
->tc
, !currState
->isSecure
));
611 tsz
= currState
->ttbcr
.t0sz
;
612 if (ttbr0_max
< (1ULL << 30)) // Upper limit < 1 GB
613 start_lookup_level
= L2
;
614 } else if (currState
->vaddr
>= ttbr1_min
) {
615 DPRINTF(TLB
, " - Selecting TTBR1 (long-desc.)\n");
616 // Check if table walk is allowed
617 if (currState
->ttbcr
.epd1
) {
618 if (currState
->isFetch
)
619 return std::make_shared
<PrefetchAbort
>(
620 currState
->vaddr_tainted
,
621 ArmFault::TranslationLL
+ L1
,
625 return std::make_shared
<DataAbort
>(
626 currState
->vaddr_tainted
,
627 TlbEntry::DomainType::NoAccess
,
629 ArmFault::TranslationLL
+ L1
,
633 ttbr
= currState
->tc
->readMiscReg(flattenMiscRegNsBanked(
634 MISCREG_TTBR1
, currState
->tc
, !currState
->isSecure
));
635 tsz
= currState
->ttbcr
.t1sz
;
636 if (ttbr1_min
>= (1ULL << 31) + (1ULL << 30)) // Lower limit >= 3 GB
637 start_lookup_level
= L2
;
639 // Out of boundaries -> translation fault
640 if (currState
->isFetch
)
641 return std::make_shared
<PrefetchAbort
>(
642 currState
->vaddr_tainted
,
643 ArmFault::TranslationLL
+ L1
,
647 return std::make_shared
<DataAbort
>(
648 currState
->vaddr_tainted
,
649 TlbEntry::DomainType::NoAccess
,
650 currState
->isWrite
, ArmFault::TranslationLL
+ L1
,
651 isStage2
, ArmFault::LpaeTran
);
656 // Perform lookup (ARM ARM issue C B3.6.6)
657 if (start_lookup_level
== L1
) {
659 desc_addr
= mbits(ttbr
, 39, n
) |
660 (bits(currState
->vaddr
, n
+ 26, 30) << 3);
661 DPRINTF(TLB
, " - Descriptor at address %#x (%s) (long-desc.)\n",
662 desc_addr
, currState
->isSecure
? "s" : "ns");
664 // Skip first-level lookup
665 n
= (tsz
>= 2 ? 14 - tsz
: 12);
666 desc_addr
= mbits(ttbr
, 39, n
) |
667 (bits(currState
->vaddr
, n
+ 17, 21) << 3);
668 DPRINTF(TLB
, " - Descriptor at address %#x (%s) (long-desc.)\n",
669 desc_addr
, currState
->isSecure
? "s" : "ns");
672 // Trickbox address check
673 Fault f
= testWalk(desc_addr
, sizeof(uint64_t),
674 TlbEntry::DomainType::NoAccess
, start_lookup_level
);
676 DPRINTF(TLB
, "Trickbox check caused fault on %#x\n", currState
->vaddr_tainted
);
677 if (currState
->timing
) {
679 nextWalk(currState
->tc
);
682 currState
->tc
= NULL
;
683 currState
->req
= NULL
;
688 if (currState
->sctlr
.c
== 0) {
689 flag
.set(Request::UNCACHEABLE
);
692 currState
->longDesc
.lookupLevel
= start_lookup_level
;
693 currState
->longDesc
.aarch64
= false;
694 currState
->longDesc
.grainSize
= Grain4KB
;
696 Event
*event
= start_lookup_level
== L1
? (Event
*) &doL1LongDescEvent
697 : (Event
*) &doL2LongDescEvent
;
699 bool delayed
= fetchDescriptor(desc_addr
, (uint8_t*)&currState
->longDesc
.data
,
700 sizeof(uint64_t), flag
, start_lookup_level
,
701 event
, &TableWalker::doLongDescriptor
);
703 f
= currState
->fault
;
710 TableWalker::adjustTableSizeAArch64(unsigned tsz
)
720 TableWalker::checkAddrSizeFaultAArch64(Addr addr
, int currPhysAddrRange
)
722 return (currPhysAddrRange
!= MaxPhysAddrRange
&&
723 bits(addr
, MaxPhysAddrRange
- 1, currPhysAddrRange
));
727 TableWalker::processWalkAArch64()
729 assert(currState
->aarch64
);
731 DPRINTF(TLB
, "Beginning table walk for address %#llx, TCR: %#llx\n",
732 currState
->vaddr_tainted
, currState
->tcr
);
734 static const GrainSize GrainMapDefault
[] =
735 { Grain4KB
, Grain64KB
, Grain16KB
, ReservedGrain
};
736 static const GrainSize GrainMap_EL1_tg1
[] =
737 { ReservedGrain
, Grain16KB
, Grain4KB
, Grain64KB
};
739 statWalkWaitTime
.sample(curTick() - currState
->startTime
);
741 // Determine TTBR, table size, granule size and phys. address range
744 GrainSize tg
= Grain4KB
; // grain size computed from tg* field
746 switch (currState
->el
) {
749 switch (bits(currState
->vaddr
, 63,48)) {
751 DPRINTF(TLB
, " - Selecting TTBR0 (AArch64)\n");
752 ttbr
= currState
->tc
->readMiscReg(MISCREG_TTBR0_EL1
);
753 tsz
= adjustTableSizeAArch64(64 - currState
->tcr
.t0sz
);
754 tg
= GrainMapDefault
[currState
->tcr
.tg0
];
755 if (bits(currState
->vaddr
, 63, tsz
) != 0x0 ||
760 DPRINTF(TLB
, " - Selecting TTBR1 (AArch64)\n");
761 ttbr
= currState
->tc
->readMiscReg(MISCREG_TTBR1_EL1
);
762 tsz
= adjustTableSizeAArch64(64 - currState
->tcr
.t1sz
);
763 tg
= GrainMap_EL1_tg1
[currState
->tcr
.tg1
];
764 if (bits(currState
->vaddr
, 63, tsz
) != mask(64-tsz
) ||
769 // top two bytes must be all 0s or all 1s, else invalid addr
772 ps
= currState
->tcr
.ips
;
776 switch(bits(currState
->vaddr
, 63,48)) {
778 DPRINTF(TLB
, " - Selecting TTBR0 (AArch64)\n");
779 if (currState
->el
== EL2
)
780 ttbr
= currState
->tc
->readMiscReg(MISCREG_TTBR0_EL2
);
782 ttbr
= currState
->tc
->readMiscReg(MISCREG_TTBR0_EL3
);
783 tsz
= adjustTableSizeAArch64(64 - currState
->tcr
.t0sz
);
784 tg
= GrainMapDefault
[currState
->tcr
.tg0
];
787 // invalid addr if top two bytes are not all 0s
790 ps
= currState
->tcr
.ips
;
796 if (currState
->isFetch
)
797 f
= std::make_shared
<PrefetchAbort
>(
798 currState
->vaddr_tainted
,
799 ArmFault::TranslationLL
+ L0
, isStage2
,
802 f
= std::make_shared
<DataAbort
>(
803 currState
->vaddr_tainted
,
804 TlbEntry::DomainType::NoAccess
,
806 ArmFault::TranslationLL
+ L0
,
807 isStage2
, ArmFault::LpaeTran
);
809 if (currState
->timing
) {
811 nextWalk(currState
->tc
);
814 currState
->tc
= NULL
;
815 currState
->req
= NULL
;
821 if (tg
== ReservedGrain
) {
822 warn_once("Reserved granule size requested; gem5's IMPLEMENTATION "
823 "DEFINED behavior takes this to mean 4KB granules\n");
828 LookupLevel start_lookup_level
= MAX_LOOKUP_LEVELS
;
830 // Determine starting lookup level
831 // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library
832 // in ARM DDI 0487A. These table values correspond to the cascading tests
833 // to compute the lookup level and are of the form
834 // (grain_size + N*stride), for N = {1, 2, 3}.
835 // A value of 64 will never succeed and a value of 0 will always succeed.
838 GrainSize grain_size
;
839 unsigned lookup_level_cutoff
[MAX_LOOKUP_LEVELS
];
841 static const GrainMap GM
[] = {
842 { Grain4KB
, { 39, 30, 0, 0 } },
843 { Grain16KB
, { 47, 36, 25, 0 } },
844 { Grain64KB
, { 64, 42, 29, 0 } }
847 const unsigned *lookup
= NULL
; // points to a lookup_level_cutoff
849 for (unsigned i
= 0; i
< 3; ++i
) { // choose entry of GM[]
850 if (tg
== GM
[i
].grain_size
) {
851 lookup
= GM
[i
].lookup_level_cutoff
;
857 for (int L
= L0
; L
!= MAX_LOOKUP_LEVELS
; ++L
) {
858 if (tsz
> lookup
[L
]) {
859 start_lookup_level
= (LookupLevel
) L
;
863 panic_if(start_lookup_level
== MAX_LOOKUP_LEVELS
,
864 "Table walker couldn't find lookup level\n");
867 // Determine table base address
868 int base_addr_lo
= 3 + tsz
- stride
* (3 - start_lookup_level
) - tg
;
869 Addr base_addr
= mbits(ttbr
, 47, base_addr_lo
);
871 // Determine physical address size and raise an Address Size Fault if
873 int pa_range
= decodePhysAddrRange64(ps
);
874 // Clamp to lower limit
875 if (pa_range
> physAddrRange
)
876 currState
->physAddrRange
= physAddrRange
;
878 currState
->physAddrRange
= pa_range
;
879 if (checkAddrSizeFaultAArch64(base_addr
, currState
->physAddrRange
)) {
880 DPRINTF(TLB
, "Address size fault before any lookup\n");
882 if (currState
->isFetch
)
883 f
= std::make_shared
<PrefetchAbort
>(
884 currState
->vaddr_tainted
,
885 ArmFault::AddressSizeLL
+ start_lookup_level
,
889 f
= std::make_shared
<DataAbort
>(
890 currState
->vaddr_tainted
,
891 TlbEntry::DomainType::NoAccess
,
893 ArmFault::AddressSizeLL
+ start_lookup_level
,
898 if (currState
->timing
) {
900 nextWalk(currState
->tc
);
903 currState
->tc
= NULL
;
904 currState
->req
= NULL
;
910 // Determine descriptor address
911 Addr desc_addr
= base_addr
|
912 (bits(currState
->vaddr
, tsz
- 1,
913 stride
* (3 - start_lookup_level
) + tg
) << 3);
915 // Trickbox address check
916 Fault f
= testWalk(desc_addr
, sizeof(uint64_t),
917 TlbEntry::DomainType::NoAccess
, start_lookup_level
);
919 DPRINTF(TLB
, "Trickbox check caused fault on %#x\n", currState
->vaddr_tainted
);
920 if (currState
->timing
) {
922 nextWalk(currState
->tc
);
925 currState
->tc
= NULL
;
926 currState
->req
= NULL
;
931 Request::Flags flag
= Request::PT_WALK
;
932 if (currState
->sctlr
.c
== 0) {
933 flag
.set(Request::UNCACHEABLE
);
936 if (currState
->isSecure
) {
937 flag
.set(Request::SECURE
);
940 currState
->longDesc
.lookupLevel
= start_lookup_level
;
941 currState
->longDesc
.aarch64
= true;
942 currState
->longDesc
.grainSize
= tg
;
944 if (currState
->timing
) {
946 switch (start_lookup_level
) {
948 event
= (Event
*) &doL0LongDescEvent
;
951 event
= (Event
*) &doL1LongDescEvent
;
954 event
= (Event
*) &doL2LongDescEvent
;
957 event
= (Event
*) &doL3LongDescEvent
;
960 panic("Invalid table lookup level");
963 port
->dmaAction(MemCmd::ReadReq
, desc_addr
, sizeof(uint64_t),
964 event
, (uint8_t*) &currState
->longDesc
.data
,
965 currState
->tc
->getCpuPtr()->clockPeriod(), flag
);
967 "Adding to walker fifo: queue size before adding: %d\n",
968 stateQueues
[start_lookup_level
].size());
969 stateQueues
[start_lookup_level
].push_back(currState
);
971 } else if (!currState
->functional
) {
972 port
->dmaAction(MemCmd::ReadReq
, desc_addr
, sizeof(uint64_t),
973 NULL
, (uint8_t*) &currState
->longDesc
.data
,
974 currState
->tc
->getCpuPtr()->clockPeriod(), flag
);
976 f
= currState
->fault
;
978 RequestPtr req
= new Request(desc_addr
, sizeof(uint64_t), flag
,
980 PacketPtr pkt
= new Packet(req
, MemCmd::ReadReq
);
981 pkt
->dataStatic((uint8_t*) &currState
->longDesc
.data
);
982 port
->sendFunctional(pkt
);
986 f
= currState
->fault
;
993 TableWalker::memAttrs(ThreadContext
*tc
, TlbEntry
&te
, SCTLR sctlr
,
994 uint8_t texcb
, bool s
)
996 // Note: tc and sctlr local variables are hiding tc and sctrl class
998 DPRINTF(TLBVerbose
, "memAttrs texcb:%d s:%d\n", texcb
, s
);
999 te
.shareable
= false; // default value
1000 te
.nonCacheable
= false;
1001 te
.outerShareable
= false;
1002 if (sctlr
.tre
== 0 || ((sctlr
.tre
== 1) && (sctlr
.m
== 0))) {
1004 case 0: // Stongly-ordered
1005 te
.nonCacheable
= true;
1006 te
.mtype
= TlbEntry::MemoryType::StronglyOrdered
;
1007 te
.shareable
= true;
1011 case 1: // Shareable Device
1012 te
.nonCacheable
= true;
1013 te
.mtype
= TlbEntry::MemoryType::Device
;
1014 te
.shareable
= true;
1018 case 2: // Outer and Inner Write-Through, no Write-Allocate
1019 te
.mtype
= TlbEntry::MemoryType::Normal
;
1022 te
.outerAttrs
= bits(texcb
, 1, 0);
1024 case 3: // Outer and Inner Write-Back, no Write-Allocate
1025 te
.mtype
= TlbEntry::MemoryType::Normal
;
1028 te
.outerAttrs
= bits(texcb
, 1, 0);
1030 case 4: // Outer and Inner Non-cacheable
1031 te
.nonCacheable
= true;
1032 te
.mtype
= TlbEntry::MemoryType::Normal
;
1035 te
.outerAttrs
= bits(texcb
, 1, 0);
1038 panic("Reserved texcb value!\n");
1040 case 6: // Implementation Defined
1041 panic("Implementation-defined texcb value!\n");
1043 case 7: // Outer and Inner Write-Back, Write-Allocate
1044 te
.mtype
= TlbEntry::MemoryType::Normal
;
1049 case 8: // Non-shareable Device
1050 te
.nonCacheable
= true;
1051 te
.mtype
= TlbEntry::MemoryType::Device
;
1052 te
.shareable
= false;
1056 case 9 ... 15: // Reserved
1057 panic("Reserved texcb value!\n");
1059 case 16 ... 31: // Cacheable Memory
1060 te
.mtype
= TlbEntry::MemoryType::Normal
;
1062 if (bits(texcb
, 1,0) == 0 || bits(texcb
, 3,2) == 0)
1063 te
.nonCacheable
= true;
1064 te
.innerAttrs
= bits(texcb
, 1, 0);
1065 te
.outerAttrs
= bits(texcb
, 3, 2);
1068 panic("More than 32 states for 5 bits?\n");
1072 PRRR prrr
= tc
->readMiscReg(flattenMiscRegNsBanked(MISCREG_PRRR
,
1073 currState
->tc
, !currState
->isSecure
));
1074 NMRR nmrr
= tc
->readMiscReg(flattenMiscRegNsBanked(MISCREG_NMRR
,
1075 currState
->tc
, !currState
->isSecure
));
1076 DPRINTF(TLBVerbose
, "memAttrs PRRR:%08x NMRR:%08x\n", prrr
, nmrr
);
1077 uint8_t curr_tr
= 0, curr_ir
= 0, curr_or
= 0;
1078 switch(bits(texcb
, 2,0)) {
1083 te
.outerShareable
= (prrr
.nos0
== 0);
1089 te
.outerShareable
= (prrr
.nos1
== 0);
1095 te
.outerShareable
= (prrr
.nos2
== 0);
1101 te
.outerShareable
= (prrr
.nos3
== 0);
1107 te
.outerShareable
= (prrr
.nos4
== 0);
1113 te
.outerShareable
= (prrr
.nos5
== 0);
1116 panic("Imp defined type\n");
1121 te
.outerShareable
= (prrr
.nos7
== 0);
1127 DPRINTF(TLBVerbose
, "StronglyOrdered\n");
1128 te
.mtype
= TlbEntry::MemoryType::StronglyOrdered
;
1129 te
.nonCacheable
= true;
1132 te
.shareable
= true;
1135 DPRINTF(TLBVerbose
, "Device ds1:%d ds0:%d s:%d\n",
1136 prrr
.ds1
, prrr
.ds0
, s
);
1137 te
.mtype
= TlbEntry::MemoryType::Device
;
1138 te
.nonCacheable
= true;
1142 te
.shareable
= true;
1144 te
.shareable
= true;
1147 DPRINTF(TLBVerbose
, "Normal ns1:%d ns0:%d s:%d\n",
1148 prrr
.ns1
, prrr
.ns0
, s
);
1149 te
.mtype
= TlbEntry::MemoryType::Normal
;
1151 te
.shareable
= true;
1153 te
.shareable
= true;
1156 panic("Reserved type");
1159 if (te
.mtype
== TlbEntry::MemoryType::Normal
){
1162 te
.nonCacheable
= true;
1178 te
.nonCacheable
= true;
1193 DPRINTF(TLBVerbose
, "memAttrs: shareable: %d, innerAttrs: %d, "
1195 te
.shareable
, te
.innerAttrs
, te
.outerAttrs
);
1196 te
.setAttributes(false);
1200 TableWalker::memAttrsLPAE(ThreadContext
*tc
, TlbEntry
&te
,
1201 LongDescriptor
&lDescriptor
)
1206 uint8_t sh
= lDescriptor
.sh();
1207 // Different format and source of attributes if this is a stage 2
1210 attr
= lDescriptor
.memAttr();
1211 uint8_t attr_3_2
= (attr
>> 2) & 0x3;
1212 uint8_t attr_1_0
= attr
& 0x3;
1214 DPRINTF(TLBVerbose
, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr
, sh
);
1216 if (attr_3_2
== 0) {
1217 te
.mtype
= attr_1_0
== 0 ? TlbEntry::MemoryType::StronglyOrdered
1218 : TlbEntry::MemoryType::Device
;
1220 te
.innerAttrs
= attr_1_0
== 0 ? 1 : 3;
1221 te
.nonCacheable
= true;
1223 te
.mtype
= TlbEntry::MemoryType::Normal
;
1224 te
.outerAttrs
= attr_3_2
== 1 ? 0 :
1225 attr_3_2
== 2 ? 2 : 1;
1226 te
.innerAttrs
= attr_1_0
== 1 ? 0 :
1227 attr_1_0
== 2 ? 6 : 5;
1228 te
.nonCacheable
= (attr_3_2
== 1) || (attr_1_0
== 1);
1231 uint8_t attrIndx
= lDescriptor
.attrIndx();
1233 // LPAE always uses remapping of memory attributes, irrespective of the
1234 // value of SCTLR.TRE
1235 MiscRegIndex reg
= attrIndx
& 0x4 ? MISCREG_MAIR1
: MISCREG_MAIR0
;
1236 int reg_as_int
= flattenMiscRegNsBanked(reg
, currState
->tc
,
1237 !currState
->isSecure
);
1238 uint32_t mair
= currState
->tc
->readMiscReg(reg_as_int
);
1239 attr
= (mair
>> (8 * (attrIndx
% 4))) & 0xff;
1240 uint8_t attr_7_4
= bits(attr
, 7, 4);
1241 uint8_t attr_3_0
= bits(attr
, 3, 0);
1242 DPRINTF(TLBVerbose
, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx
, sh
, attr
);
1244 // Note: the memory subsystem only cares about the 'cacheable' memory
1245 // attribute. The other attributes are only used to fill the PAR register
1246 // accordingly to provide the illusion of full support
1247 te
.nonCacheable
= false;
1251 // Strongly-ordered or Device memory
1252 if (attr_3_0
== 0x0)
1253 te
.mtype
= TlbEntry::MemoryType::StronglyOrdered
;
1254 else if (attr_3_0
== 0x4)
1255 te
.mtype
= TlbEntry::MemoryType::Device
;
1257 panic("Unpredictable behavior\n");
1258 te
.nonCacheable
= true;
1262 // Normal memory, Outer Non-cacheable
1263 te
.mtype
= TlbEntry::MemoryType::Normal
;
1265 if (attr_3_0
== 0x4)
1266 // Inner Non-cacheable
1267 te
.nonCacheable
= true;
1268 else if (attr_3_0
< 0x8)
1269 panic("Unpredictable behavior\n");
1279 if (attr_7_4
& 0x4) {
1280 te
.outerAttrs
= (attr_7_4
& 1) ? 1 : 3;
1282 te
.outerAttrs
= 0x2;
1284 // Normal memory, Outer Cacheable
1285 te
.mtype
= TlbEntry::MemoryType::Normal
;
1286 if (attr_3_0
!= 0x4 && attr_3_0
< 0x8)
1287 panic("Unpredictable behavior\n");
1290 panic("Unpredictable behavior\n");
1296 te
.innerAttrs
= 0x1;
1299 te
.innerAttrs
= attr_7_4
== 0 ? 0x3 : 0;
1311 te
.innerAttrs
= attr_3_0
& 1 ? 0x5 : 0x7;
1314 panic("Unpredictable behavior\n");
1319 te
.outerShareable
= sh
== 2;
1320 te
.shareable
= (sh
& 0x2) ? true : false;
1321 te
.setAttributes(true);
1322 te
.attributes
|= (uint64_t) attr
<< 56;
1326 TableWalker::memAttrsAArch64(ThreadContext
*tc
, TlbEntry
&te
, uint8_t attrIndx
,
1329 DPRINTF(TLBVerbose
, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx
, sh
);
1333 switch (currState
->el
) {
1336 mair
= tc
->readMiscReg(MISCREG_MAIR_EL1
);
1339 mair
= tc
->readMiscReg(MISCREG_MAIR_EL2
);
1342 mair
= tc
->readMiscReg(MISCREG_MAIR_EL3
);
1345 panic("Invalid exception level");
1349 // Select attributes
1350 uint8_t attr
= bits(mair
, 8 * attrIndx
+ 7, 8 * attrIndx
);
1351 uint8_t attr_lo
= bits(attr
, 3, 0);
1352 uint8_t attr_hi
= bits(attr
, 7, 4);
1355 te
.mtype
= attr_hi
== 0 ? TlbEntry::MemoryType::Device
: TlbEntry::MemoryType::Normal
;
1358 te
.nonCacheable
= false;
1359 if (te
.mtype
== TlbEntry::MemoryType::Device
|| // Device memory
1360 attr_hi
== 0x8 || // Normal memory, Outer Non-cacheable
1361 attr_lo
== 0x8) { // Normal memory, Inner Non-cacheable
1362 te
.nonCacheable
= true;
1365 te
.shareable
= sh
== 2;
1366 te
.outerShareable
= (sh
& 0x2) ? true : false;
1367 // Attributes formatted according to the 64-bit PAR
1368 te
.attributes
= ((uint64_t) attr
<< 56) |
1369 (1 << 11) | // LPAE bit
1370 (te
.ns
<< 9) | // NS bit
1375 TableWalker::doL1Descriptor()
1377 if (currState
->fault
!= NoFault
) {
1381 DPRINTF(TLB
, "L1 descriptor for %#x is %#x\n",
1382 currState
->vaddr_tainted
, currState
->l1Desc
.data
);
1385 switch (currState
->l1Desc
.type()) {
1386 case L1Descriptor::Ignore
:
1387 case L1Descriptor::Reserved
:
1388 if (!currState
->timing
) {
1389 currState
->tc
= NULL
;
1390 currState
->req
= NULL
;
1392 DPRINTF(TLB
, "L1 Descriptor Reserved/Ignore, causing fault\n");
1393 if (currState
->isFetch
)
1395 std::make_shared
<PrefetchAbort
>(
1396 currState
->vaddr_tainted
,
1397 ArmFault::TranslationLL
+ L1
,
1399 ArmFault::VmsaTran
);
1402 std::make_shared
<DataAbort
>(
1403 currState
->vaddr_tainted
,
1404 TlbEntry::DomainType::NoAccess
,
1406 ArmFault::TranslationLL
+ L1
, isStage2
,
1407 ArmFault::VmsaTran
);
1409 case L1Descriptor::Section
:
1410 if (currState
->sctlr
.afe
&& bits(currState
->l1Desc
.ap(), 0) == 0) {
1411 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is
1412 * enabled if set, do l1.Desc.setAp0() instead of generating
1416 currState
->fault
= std::make_shared
<DataAbort
>(
1417 currState
->vaddr_tainted
,
1418 currState
->l1Desc
.domain(),
1420 ArmFault::AccessFlagLL
+ L1
,
1422 ArmFault::VmsaTran
);
1424 if (currState
->l1Desc
.supersection()) {
1425 panic("Haven't implemented supersections\n");
1427 insertTableEntry(currState
->l1Desc
, false);
1429 case L1Descriptor::PageTable
:
1432 l2desc_addr
= currState
->l1Desc
.l2Addr() |
1433 (bits(currState
->vaddr
, 19, 12) << 2);
1434 DPRINTF(TLB
, "L1 descriptor points to page table at: %#x (%s)\n",
1435 l2desc_addr
, currState
->isSecure
? "s" : "ns");
1437 // Trickbox address check
1438 currState
->fault
= testWalk(l2desc_addr
, sizeof(uint32_t),
1439 currState
->l1Desc
.domain(), L2
);
1441 if (currState
->fault
) {
1442 if (!currState
->timing
) {
1443 currState
->tc
= NULL
;
1444 currState
->req
= NULL
;
1449 Request::Flags flag
= Request::PT_WALK
;
1450 if (currState
->isSecure
)
1451 flag
.set(Request::SECURE
);
1454 delayed
= fetchDescriptor(l2desc_addr
,
1455 (uint8_t*)&currState
->l2Desc
.data
,
1456 sizeof(uint32_t), flag
, -1, &doL2DescEvent
,
1457 &TableWalker::doL2Descriptor
);
1459 currState
->delayed
= true;
1465 panic("A new type in a 2 bit field?\n");
1470 TableWalker::doLongDescriptor()
1472 if (currState
->fault
!= NoFault
) {
1476 DPRINTF(TLB
, "L%d descriptor for %#llx is %#llx (%s)\n",
1477 currState
->longDesc
.lookupLevel
, currState
->vaddr_tainted
,
1478 currState
->longDesc
.data
,
1479 currState
->aarch64
? "AArch64" : "long-desc.");
1481 if ((currState
->longDesc
.type() == LongDescriptor::Block
) ||
1482 (currState
->longDesc
.type() == LongDescriptor::Page
)) {
1483 DPRINTF(TLBVerbose
, "Analyzing L%d descriptor: %#llx, pxn: %d, "
1484 "xn: %d, ap: %d, af: %d, type: %d\n",
1485 currState
->longDesc
.lookupLevel
,
1486 currState
->longDesc
.data
,
1487 currState
->longDesc
.pxn(),
1488 currState
->longDesc
.xn(),
1489 currState
->longDesc
.ap(),
1490 currState
->longDesc
.af(),
1491 currState
->longDesc
.type());
1493 DPRINTF(TLBVerbose
, "Analyzing L%d descriptor: %#llx, type: %d\n",
1494 currState
->longDesc
.lookupLevel
,
1495 currState
->longDesc
.data
,
1496 currState
->longDesc
.type());
1501 switch (currState
->longDesc
.type()) {
1502 case LongDescriptor::Invalid
:
1503 if (!currState
->timing
) {
1504 currState
->tc
= NULL
;
1505 currState
->req
= NULL
;
1508 DPRINTF(TLB
, "L%d descriptor Invalid, causing fault type %d\n",
1509 currState
->longDesc
.lookupLevel
,
1510 ArmFault::TranslationLL
+ currState
->longDesc
.lookupLevel
);
1511 if (currState
->isFetch
)
1512 currState
->fault
= std::make_shared
<PrefetchAbort
>(
1513 currState
->vaddr_tainted
,
1514 ArmFault::TranslationLL
+ currState
->longDesc
.lookupLevel
,
1516 ArmFault::LpaeTran
);
1518 currState
->fault
= std::make_shared
<DataAbort
>(
1519 currState
->vaddr_tainted
,
1520 TlbEntry::DomainType::NoAccess
,
1522 ArmFault::TranslationLL
+ currState
->longDesc
.lookupLevel
,
1524 ArmFault::LpaeTran
);
1526 case LongDescriptor::Block
:
1527 case LongDescriptor::Page
:
1531 // Check for address size fault
1532 if (checkAddrSizeFaultAArch64(
1533 mbits(currState
->longDesc
.data
, MaxPhysAddrRange
- 1,
1534 currState
->longDesc
.offsetBits()),
1535 currState
->physAddrRange
)) {
1537 DPRINTF(TLB
, "L%d descriptor causing Address Size Fault\n",
1538 currState
->longDesc
.lookupLevel
);
1539 // Check for access fault
1540 } else if (currState
->longDesc
.af() == 0) {
1542 DPRINTF(TLB
, "L%d descriptor causing Access Fault\n",
1543 currState
->longDesc
.lookupLevel
);
1547 if (currState
->isFetch
)
1548 currState
->fault
= std::make_shared
<PrefetchAbort
>(
1549 currState
->vaddr_tainted
,
1550 (aff
? ArmFault::AccessFlagLL
: ArmFault::AddressSizeLL
) +
1551 currState
->longDesc
.lookupLevel
,
1553 ArmFault::LpaeTran
);
1555 currState
->fault
= std::make_shared
<DataAbort
>(
1556 currState
->vaddr_tainted
,
1557 TlbEntry::DomainType::NoAccess
, currState
->isWrite
,
1558 (aff
? ArmFault::AccessFlagLL
: ArmFault::AddressSizeLL
) +
1559 currState
->longDesc
.lookupLevel
,
1561 ArmFault::LpaeTran
);
1563 insertTableEntry(currState
->longDesc
, true);
1567 case LongDescriptor::Table
:
1569 // Set hierarchical permission flags
1570 currState
->secureLookup
= currState
->secureLookup
&&
1571 currState
->longDesc
.secureTable();
1572 currState
->rwTable
= currState
->rwTable
&&
1573 currState
->longDesc
.rwTable();
1574 currState
->userTable
= currState
->userTable
&&
1575 currState
->longDesc
.userTable();
1576 currState
->xnTable
= currState
->xnTable
||
1577 currState
->longDesc
.xnTable();
1578 currState
->pxnTable
= currState
->pxnTable
||
1579 currState
->longDesc
.pxnTable();
1581 // Set up next level lookup
1582 Addr next_desc_addr
= currState
->longDesc
.nextDescAddr(
1585 DPRINTF(TLB
, "L%d descriptor points to L%d descriptor at: %#x (%s)\n",
1586 currState
->longDesc
.lookupLevel
,
1587 currState
->longDesc
.lookupLevel
+ 1,
1589 currState
->secureLookup
? "s" : "ns");
1591 // Check for address size fault
1592 if (currState
->aarch64
&& checkAddrSizeFaultAArch64(
1593 next_desc_addr
, currState
->physAddrRange
)) {
1594 DPRINTF(TLB
, "L%d descriptor causing Address Size Fault\n",
1595 currState
->longDesc
.lookupLevel
);
1596 if (currState
->isFetch
)
1597 currState
->fault
= std::make_shared
<PrefetchAbort
>(
1598 currState
->vaddr_tainted
,
1599 ArmFault::AddressSizeLL
1600 + currState
->longDesc
.lookupLevel
,
1602 ArmFault::LpaeTran
);
1604 currState
->fault
= std::make_shared
<DataAbort
>(
1605 currState
->vaddr_tainted
,
1606 TlbEntry::DomainType::NoAccess
, currState
->isWrite
,
1607 ArmFault::AddressSizeLL
1608 + currState
->longDesc
.lookupLevel
,
1610 ArmFault::LpaeTran
);
1614 // Trickbox address check
1615 currState
->fault
= testWalk(
1616 next_desc_addr
, sizeof(uint64_t), TlbEntry::DomainType::Client
,
1617 toLookupLevel(currState
->longDesc
.lookupLevel
+1));
1619 if (currState
->fault
) {
1620 if (!currState
->timing
) {
1621 currState
->tc
= NULL
;
1622 currState
->req
= NULL
;
1627 Request::Flags flag
= Request::PT_WALK
;
1628 if (currState
->secureLookup
)
1629 flag
.set(Request::SECURE
);
1631 currState
->longDesc
.lookupLevel
=
1632 (LookupLevel
) (currState
->longDesc
.lookupLevel
+ 1);
1633 Event
*event
= NULL
;
1634 switch (currState
->longDesc
.lookupLevel
) {
1636 assert(currState
->aarch64
);
1637 event
= &doL1LongDescEvent
;
1640 event
= &doL2LongDescEvent
;
1643 event
= &doL3LongDescEvent
;
1646 panic("Wrong lookup level in table walk\n");
1651 delayed
= fetchDescriptor(next_desc_addr
, (uint8_t*)&currState
->longDesc
.data
,
1652 sizeof(uint64_t), flag
, -1, event
,
1653 &TableWalker::doLongDescriptor
);
1655 currState
->delayed
= true;
1660 panic("A new type in a 2 bit field?\n");
1665 TableWalker::doL2Descriptor()
1667 if (currState
->fault
!= NoFault
) {
1671 DPRINTF(TLB
, "L2 descriptor for %#x is %#x\n",
1672 currState
->vaddr_tainted
, currState
->l2Desc
.data
);
1675 if (currState
->l2Desc
.invalid()) {
1676 DPRINTF(TLB
, "L2 descriptor invalid, causing fault\n");
1677 if (!currState
->timing
) {
1678 currState
->tc
= NULL
;
1679 currState
->req
= NULL
;
1681 if (currState
->isFetch
)
1682 currState
->fault
= std::make_shared
<PrefetchAbort
>(
1683 currState
->vaddr_tainted
,
1684 ArmFault::TranslationLL
+ L2
,
1686 ArmFault::VmsaTran
);
1688 currState
->fault
= std::make_shared
<DataAbort
>(
1689 currState
->vaddr_tainted
, currState
->l1Desc
.domain(),
1690 currState
->isWrite
, ArmFault::TranslationLL
+ L2
,
1692 ArmFault::VmsaTran
);
1696 if (currState
->sctlr
.afe
&& bits(currState
->l2Desc
.ap(), 0) == 0) {
1697 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled
1698 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0
1700 DPRINTF(TLB
, "Generating access fault at L2, afe: %d, ap: %d\n",
1701 currState
->sctlr
.afe
, currState
->l2Desc
.ap());
1703 currState
->fault
= std::make_shared
<DataAbort
>(
1704 currState
->vaddr_tainted
,
1705 TlbEntry::DomainType::NoAccess
, currState
->isWrite
,
1706 ArmFault::AccessFlagLL
+ L2
, isStage2
,
1707 ArmFault::VmsaTran
);
1710 insertTableEntry(currState
->l2Desc
, false);
1714 TableWalker::doL1DescriptorWrapper()
1716 currState
= stateQueues
[L1
].front();
1717 currState
->delayed
= false;
1718 // if there's a stage2 translation object we don't need it any more
1719 if (currState
->stage2Tran
) {
1720 delete currState
->stage2Tran
;
1721 currState
->stage2Tran
= NULL
;
1725 DPRINTF(TLBVerbose
, "L1 Desc object host addr: %p\n",&currState
->l1Desc
.data
);
1726 DPRINTF(TLBVerbose
, "L1 Desc object data: %08x\n",currState
->l1Desc
.data
);
1728 DPRINTF(TLBVerbose
, "calling doL1Descriptor for vaddr:%#x\n", currState
->vaddr_tainted
);
1731 stateQueues
[L1
].pop_front();
1732 // Check if fault was generated
1733 if (currState
->fault
!= NoFault
) {
1734 currState
->transState
->finish(currState
->fault
, currState
->req
,
1735 currState
->tc
, currState
->mode
);
1736 statWalksShortTerminatedAtLevel
[0]++;
1739 nextWalk(currState
->tc
);
1741 currState
->req
= NULL
;
1742 currState
->tc
= NULL
;
1743 currState
->delayed
= false;
1746 else if (!currState
->delayed
) {
1747 // delay is not set so there is no L2 to do
1748 // Don't finish the translation if a stage 2 look up is underway
1749 if (!currState
->doingStage2
) {
1750 statWalkServiceTime
.sample(curTick() - currState
->startTime
);
1751 DPRINTF(TLBVerbose
, "calling translateTiming again\n");
1752 currState
->fault
= tlb
->translateTiming(currState
->req
, currState
->tc
,
1753 currState
->transState
, currState
->mode
);
1754 statWalksShortTerminatedAtLevel
[0]++;
1758 nextWalk(currState
->tc
);
1760 currState
->req
= NULL
;
1761 currState
->tc
= NULL
;
1762 currState
->delayed
= false;
1765 // need to do L2 descriptor
1766 stateQueues
[L2
].push_back(currState
);
1772 TableWalker::doL2DescriptorWrapper()
1774 currState
= stateQueues
[L2
].front();
1775 assert(currState
->delayed
);
1776 // if there's a stage2 translation object we don't need it any more
1777 if (currState
->stage2Tran
) {
1778 delete currState
->stage2Tran
;
1779 currState
->stage2Tran
= NULL
;
1782 DPRINTF(TLBVerbose
, "calling doL2Descriptor for vaddr:%#x\n",
1783 currState
->vaddr_tainted
);
1786 // Check if fault was generated
1787 if (currState
->fault
!= NoFault
) {
1788 currState
->transState
->finish(currState
->fault
, currState
->req
,
1789 currState
->tc
, currState
->mode
);
1790 statWalksShortTerminatedAtLevel
[1]++;
1793 // Don't finish the translation if a stage 2 look up is underway
1794 if (!currState
->doingStage2
) {
1795 statWalkServiceTime
.sample(curTick() - currState
->startTime
);
1796 DPRINTF(TLBVerbose
, "calling translateTiming again\n");
1797 currState
->fault
= tlb
->translateTiming(currState
->req
,
1798 currState
->tc
, currState
->transState
, currState
->mode
);
1799 statWalksShortTerminatedAtLevel
[1]++;
1804 stateQueues
[L2
].pop_front();
1806 nextWalk(currState
->tc
);
1808 currState
->req
= NULL
;
1809 currState
->tc
= NULL
;
1810 currState
->delayed
= false;
1817 TableWalker::doL0LongDescriptorWrapper()
1819 doLongDescriptorWrapper(L0
);
1823 TableWalker::doL1LongDescriptorWrapper()
1825 doLongDescriptorWrapper(L1
);
1829 TableWalker::doL2LongDescriptorWrapper()
1831 doLongDescriptorWrapper(L2
);
1835 TableWalker::doL3LongDescriptorWrapper()
1837 doLongDescriptorWrapper(L3
);
1841 TableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level
)
1843 currState
= stateQueues
[curr_lookup_level
].front();
1844 assert(curr_lookup_level
== currState
->longDesc
.lookupLevel
);
1845 currState
->delayed
= false;
1847 // if there's a stage2 translation object we don't need it any more
1848 if (currState
->stage2Tran
) {
1849 delete currState
->stage2Tran
;
1850 currState
->stage2Tran
= NULL
;
1853 DPRINTF(TLBVerbose
, "calling doLongDescriptor for vaddr:%#x\n",
1854 currState
->vaddr_tainted
);
1857 stateQueues
[curr_lookup_level
].pop_front();
1859 if (currState
->fault
!= NoFault
) {
1860 // A fault was generated
1861 currState
->transState
->finish(currState
->fault
, currState
->req
,
1862 currState
->tc
, currState
->mode
);
1865 nextWalk(currState
->tc
);
1867 currState
->req
= NULL
;
1868 currState
->tc
= NULL
;
1869 currState
->delayed
= false;
1871 } else if (!currState
->delayed
) {
1872 // No additional lookups required
1873 // Don't finish the translation if a stage 2 look up is underway
1874 if (!currState
->doingStage2
) {
1875 DPRINTF(TLBVerbose
, "calling translateTiming again\n");
1876 statWalkServiceTime
.sample(curTick() - currState
->startTime
);
1877 currState
->fault
= tlb
->translateTiming(currState
->req
, currState
->tc
,
1878 currState
->transState
,
1880 statWalksLongTerminatedAtLevel
[(unsigned) curr_lookup_level
]++;
1884 nextWalk(currState
->tc
);
1886 currState
->req
= NULL
;
1887 currState
->tc
= NULL
;
1888 currState
->delayed
= false;
1891 if (curr_lookup_level
>= MAX_LOOKUP_LEVELS
- 1)
1892 panic("Max. number of lookups already reached in table walk\n");
1893 // Need to perform additional lookups
1894 stateQueues
[currState
->longDesc
.lookupLevel
].push_back(currState
);
1901 TableWalker::nextWalk(ThreadContext
*tc
)
1903 if (pendingQueue
.size())
1904 schedule(doProcessEvent
, clockEdge(Cycles(1)));
1910 TableWalker::fetchDescriptor(Addr descAddr
, uint8_t *data
, int numBytes
,
1911 Request::Flags flags
, int queueIndex
, Event
*event
,
1912 void (TableWalker::*doDescriptor
)())
1914 bool isTiming
= currState
->timing
;
1916 // do the requests for the page table descriptors have to go through the
1918 if (currState
->stage2Req
) {
1920 flags
= flags
| TLB::MustBeOne
;
1923 Stage2MMU::Stage2Translation
*tran
= new
1924 Stage2MMU::Stage2Translation(*stage2Mmu
, data
, event
,
1926 currState
->stage2Tran
= tran
;
1927 stage2Mmu
->readDataTimed(currState
->tc
, descAddr
, tran
, numBytes
,
1929 fault
= tran
->fault
;
1931 fault
= stage2Mmu
->readDataUntimed(currState
->tc
,
1932 currState
->vaddr
, descAddr
, data
, numBytes
, flags
,
1933 currState
->functional
);
1936 if (fault
!= NoFault
) {
1937 currState
->fault
= fault
;
1940 if (queueIndex
>= 0) {
1941 DPRINTF(TLBVerbose
, "Adding to walker fifo: queue size before adding: %d\n",
1942 stateQueues
[queueIndex
].size());
1943 stateQueues
[queueIndex
].push_back(currState
);
1947 (this->*doDescriptor
)();
1951 port
->dmaAction(MemCmd::ReadReq
, descAddr
, numBytes
, event
, data
,
1952 currState
->tc
->getCpuPtr()->clockPeriod(),flags
);
1953 if (queueIndex
>= 0) {
1954 DPRINTF(TLBVerbose
, "Adding to walker fifo: queue size before adding: %d\n",
1955 stateQueues
[queueIndex
].size());
1956 stateQueues
[queueIndex
].push_back(currState
);
1959 } else if (!currState
->functional
) {
1960 port
->dmaAction(MemCmd::ReadReq
, descAddr
, numBytes
, NULL
, data
,
1961 currState
->tc
->getCpuPtr()->clockPeriod(), flags
);
1962 (this->*doDescriptor
)();
1964 RequestPtr req
= new Request(descAddr
, numBytes
, flags
, masterId
);
1965 req
->taskId(ContextSwitchTaskId::DMA
);
1966 PacketPtr pkt
= new Packet(req
, MemCmd::ReadReq
);
1967 pkt
->dataStatic(data
);
1968 port
->sendFunctional(pkt
);
1969 (this->*doDescriptor
)();
1978 TableWalker::insertTableEntry(DescriptorBase
&descriptor
, bool longDescriptor
)
1982 // Create and fill a new page table entry
1984 te
.longDescFormat
= longDescriptor
;
1985 te
.isHyp
= currState
->isHyp
;
1986 te
.asid
= currState
->asid
;
1987 te
.vmid
= currState
->vmid
;
1988 te
.N
= descriptor
.offsetBits();
1989 te
.vpn
= currState
->vaddr
>> te
.N
;
1990 te
.size
= (1<<te
.N
) - 1;
1991 te
.pfn
= descriptor
.pfn();
1992 te
.domain
= descriptor
.domain();
1993 te
.lookupLevel
= descriptor
.lookupLevel
;
1994 te
.ns
= !descriptor
.secure(haveSecurity
, currState
) || isStage2
;
1995 te
.nstid
= !currState
->isSecure
;
1996 te
.xn
= descriptor
.xn();
1997 if (currState
->aarch64
)
1998 te
.el
= currState
->el
;
2002 statPageSizes
[pageSizeNtoStatBin(te
.N
)]++;
2003 statRequestOrigin
[COMPLETED
][currState
->isFetch
]++;
2005 // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries
2007 te
.global
= descriptor
.global(currState
) || isStage2
;
2008 if (longDescriptor
) {
2009 LongDescriptor lDescriptor
=
2010 dynamic_cast<LongDescriptor
&>(descriptor
);
2012 te
.xn
|= currState
->xnTable
;
2013 te
.pxn
= currState
->pxnTable
|| lDescriptor
.pxn();
2015 // this is actually the HAP field, but its stored in the same bit
2016 // possitions as the AP field in a stage 1 translation.
2017 te
.hap
= lDescriptor
.ap();
2019 te
.ap
= ((!currState
->rwTable
|| descriptor
.ap() >> 1) << 1) |
2020 (currState
->userTable
&& (descriptor
.ap() & 0x1));
2022 if (currState
->aarch64
)
2023 memAttrsAArch64(currState
->tc
, te
, currState
->longDesc
.attrIndx(),
2024 currState
->longDesc
.sh());
2026 memAttrsLPAE(currState
->tc
, te
, lDescriptor
);
2028 te
.ap
= descriptor
.ap();
2029 memAttrs(currState
->tc
, te
, currState
->sctlr
, descriptor
.texcb(),
2030 descriptor
.shareable());
2034 DPRINTF(TLB
, descriptor
.dbgHeader().c_str());
2035 DPRINTF(TLB
, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n",
2036 te
.N
, te
.pfn
, te
.size
, te
.global
, te
.valid
);
2037 DPRINTF(TLB
, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d "
2038 "vmid:%d hyp:%d nc:%d ns:%d\n", te
.vpn
, te
.xn
, te
.pxn
,
2039 te
.ap
, static_cast<uint8_t>(te
.domain
), te
.asid
, te
.vmid
, te
.isHyp
,
2040 te
.nonCacheable
, te
.ns
);
2041 DPRINTF(TLB
, " - domain from L%d desc:%d data:%#x\n",
2042 descriptor
.lookupLevel
, static_cast<uint8_t>(descriptor
.domain()),
2043 descriptor
.getRawData());
2045 // Insert the entry into the TLB
2046 tlb
->insert(currState
->vaddr
, te
);
2047 if (!currState
->timing
) {
2048 currState
->tc
= NULL
;
2049 currState
->req
= NULL
;
2053 ArmISA::TableWalker
*
2054 ArmTableWalkerParams::create()
2056 return new ArmISA::TableWalker(this);
2060 TableWalker::toLookupLevel(uint8_t lookup_level_as_int
)
2062 switch (lookup_level_as_int
) {
2070 panic("Invalid lookup level conversion");
2074 /* this method keeps track of the table walker queue's residency, so
2075 * needs to be called whenever requests start and complete. */
2077 TableWalker::pendingChange()
2079 unsigned n
= pendingQueue
.size();
2080 if ((currState
!= NULL
) && (currState
!= pendingQueue
.front())) {
2084 if (n
!= pendingReqs
) {
2085 Tick now
= curTick();
2086 statPendingWalks
.sample(pendingReqs
, now
- pendingChangeTick
);
2088 pendingChangeTick
= now
;
2093 TableWalker::testWalk(Addr pa
, Addr size
, TlbEntry::DomainType domain
,
2094 LookupLevel lookup_level
)
2096 return tlb
->testWalk(pa
, size
, currState
->vaddr
, currState
->isSecure
,
2097 currState
->mode
, domain
, lookup_level
);
2102 TableWalker::pageSizeNtoStatBin(uint8_t N
)
2104 /* for statPageSizes */
2106 case 12: return 0; // 4K
2107 case 14: return 1; // 16K (using 16K granule in v8-64)
2108 case 16: return 2; // 64K
2109 case 20: return 3; // 1M
2110 case 21: return 4; // 2M-LPAE
2111 case 24: return 5; // 16M
2112 case 25: return 6; // 32M (using 16K granule in v8-64)
2113 case 29: return 7; // 512M (using 64K granule in v8-64)
2114 case 30: return 8; // 1G-LPAE
2116 panic("unknown page size");
2122 TableWalker::regStats()
2124 ClockedObject::regStats();
2127 .name(name() + ".walks")
2128 .desc("Table walker walks requested")
2131 statWalksShortDescriptor
2132 .name(name() + ".walksShort")
2133 .desc("Table walker walks initiated with short descriptors")
2134 .flags(Stats::nozero
)
2137 statWalksLongDescriptor
2138 .name(name() + ".walksLong")
2139 .desc("Table walker walks initiated with long descriptors")
2140 .flags(Stats::nozero
)
2143 statWalksShortTerminatedAtLevel
2145 .name(name() + ".walksShortTerminationLevel")
2146 .desc("Level at which table walker walks "
2147 "with short descriptors terminate")
2148 .flags(Stats::nozero
)
2150 statWalksShortTerminatedAtLevel
.subname(0, "Level1");
2151 statWalksShortTerminatedAtLevel
.subname(1, "Level2");
2153 statWalksLongTerminatedAtLevel
2155 .name(name() + ".walksLongTerminationLevel")
2156 .desc("Level at which table walker walks "
2157 "with long descriptors terminate")
2158 .flags(Stats::nozero
)
2160 statWalksLongTerminatedAtLevel
.subname(0, "Level0");
2161 statWalksLongTerminatedAtLevel
.subname(1, "Level1");
2162 statWalksLongTerminatedAtLevel
.subname(2, "Level2");
2163 statWalksLongTerminatedAtLevel
.subname(3, "Level3");
2166 .name(name() + ".walksSquashedBefore")
2167 .desc("Table walks squashed before starting")
2168 .flags(Stats::nozero
)
2172 .name(name() + ".walksSquashedAfter")
2173 .desc("Table walks squashed after completion")
2174 .flags(Stats::nozero
)
2179 .name(name() + ".walkWaitTime")
2180 .desc("Table walker wait (enqueue to first request) latency")
2181 .flags(Stats::pdf
| Stats::nozero
| Stats::nonan
)
2186 .name(name() + ".walkCompletionTime")
2187 .desc("Table walker service (enqueue to completion) latency")
2188 .flags(Stats::pdf
| Stats::nozero
| Stats::nonan
)
2193 .name(name() + ".walksPending")
2194 .desc("Table walker pending requests distribution")
2195 .flags(Stats::pdf
| Stats::dist
| Stats::nozero
| Stats::nonan
)
2198 statPageSizes
// see DDI 0487A D4-1661
2200 .name(name() + ".walkPageSizes")
2201 .desc("Table walker page sizes translated")
2202 .flags(Stats::total
| Stats::pdf
| Stats::dist
| Stats::nozero
)
2204 statPageSizes
.subname(0, "4K");
2205 statPageSizes
.subname(1, "16K");
2206 statPageSizes
.subname(2, "64K");
2207 statPageSizes
.subname(3, "1M");
2208 statPageSizes
.subname(4, "2M");
2209 statPageSizes
.subname(5, "16M");
2210 statPageSizes
.subname(6, "32M");
2211 statPageSizes
.subname(7, "512M");
2212 statPageSizes
.subname(8, "1G");
2215 .init(2,2) // Instruction/Data, requests/completed
2216 .name(name() + ".walkRequestOrigin")
2217 .desc("Table walker requests started/completed, data/inst")
2218 .flags(Stats::total
)
2220 statRequestOrigin
.subname(0,"Requested");
2221 statRequestOrigin
.subname(1,"Completed");
2222 statRequestOrigin
.ysubname(0,"Data");
2223 statRequestOrigin
.ysubname(1,"Inst");