2 * Copyright (c) 2010, 2012-2019 ARM Limited
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
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17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
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21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 #include "arch/arm/table_walker.hh"
44 #include "arch/arm/faults.hh"
45 #include "arch/arm/stage2_mmu.hh"
46 #include "arch/arm/system.hh"
47 #include "arch/arm/tlb.hh"
48 #include "cpu/base.hh"
49 #include "cpu/thread_context.hh"
50 #include "debug/Checkpoint.hh"
51 #include "debug/Drain.hh"
52 #include "debug/TLB.hh"
53 #include "debug/TLBVerbose.hh"
54 #include "dev/dma_device.hh"
55 #include "sim/system.hh"
57 using namespace ArmISA
;
59 TableWalker::TableWalker(const Params
*p
)
61 stage2Mmu(NULL
), port(NULL
), masterId(Request::invldMasterId
),
62 isStage2(p
->is_stage2
), tlb(NULL
),
63 currState(NULL
), pending(false),
64 numSquashable(p
->num_squash_per_cycle
),
66 pendingChangeTick(curTick()),
67 doL1DescEvent([this]{ doL1DescriptorWrapper(); }, name()),
68 doL2DescEvent([this]{ doL2DescriptorWrapper(); }, name()),
69 doL0LongDescEvent([this]{ doL0LongDescriptorWrapper(); }, name()),
70 doL1LongDescEvent([this]{ doL1LongDescriptorWrapper(); }, name()),
71 doL2LongDescEvent([this]{ doL2LongDescriptorWrapper(); }, name()),
72 doL3LongDescEvent([this]{ doL3LongDescriptorWrapper(); }, name()),
73 LongDescEventByLevel
{ &doL0LongDescEvent
, &doL1LongDescEvent
,
74 &doL2LongDescEvent
, &doL3LongDescEvent
},
75 doProcessEvent([this]{ processWalkWrapper(); }, name())
79 // Cache system-level properties
81 ArmSystem
*armSys
= dynamic_cast<ArmSystem
*>(p
->sys
);
83 haveSecurity
= armSys
->haveSecurity();
84 _haveLPAE
= armSys
->haveLPAE();
85 _haveVirtualization
= armSys
->haveVirtualization();
86 physAddrRange
= armSys
->physAddrRange();
87 _haveLargeAsid64
= armSys
->haveLargeAsid64();
89 haveSecurity
= _haveLPAE
= _haveVirtualization
= false;
90 _haveLargeAsid64
= false;
96 TableWalker::~TableWalker()
102 TableWalker::setMMU(Stage2MMU
*m
, MasterID master_id
)
105 port
= &m
->getDMAPort();
106 masterId
= master_id
;
112 fatal_if(!stage2Mmu
, "Table walker must have a valid stage-2 MMU\n");
113 fatal_if(!port
, "Table walker must have a valid port\n");
114 fatal_if(!tlb
, "Table walker must have a valid TLB\n");
118 TableWalker::getPort(const std::string
&if_name
, PortID idx
)
120 if (if_name
== "port") {
124 fatal("Cannot access table walker port through stage-two walker\n");
127 return ClockedObject::getPort(if_name
, idx
);
130 TableWalker::WalkerState::WalkerState() :
131 tc(nullptr), aarch64(false), el(EL0
), physAddrRange(0), req(nullptr),
132 asid(0), vmid(0), isHyp(false), transState(nullptr),
133 vaddr(0), vaddr_tainted(0),
134 sctlr(0), scr(0), cpsr(0), tcr(0),
135 htcr(0), hcr(0), vtcr(0),
136 isWrite(false), isFetch(false), isSecure(false),
137 isUncacheable(false),
138 secureLookup(false), rwTable(false), userTable(false), xnTable(false),
139 pxnTable(false), hpd(false), stage2Req(false),
140 stage2Tran(nullptr), timing(false), functional(false),
141 mode(BaseTLB::Read
), tranType(TLB::NormalTran
), l2Desc(l1Desc
),
142 delayed(false), tableWalker(nullptr)
147 TableWalker::completeDrain()
149 if (drainState() == DrainState::Draining
&&
150 stateQueues
[L0
].empty() && stateQueues
[L1
].empty() &&
151 stateQueues
[L2
].empty() && stateQueues
[L3
].empty() &&
152 pendingQueue
.empty()) {
154 DPRINTF(Drain
, "TableWalker done draining, processing drain event\n");
162 bool state_queues_not_empty
= false;
164 for (int i
= 0; i
< MAX_LOOKUP_LEVELS
; ++i
) {
165 if (!stateQueues
[i
].empty()) {
166 state_queues_not_empty
= true;
171 if (state_queues_not_empty
|| pendingQueue
.size()) {
172 DPRINTF(Drain
, "TableWalker not drained\n");
173 return DrainState::Draining
;
175 DPRINTF(Drain
, "TableWalker free, no need to drain\n");
176 return DrainState::Drained
;
181 TableWalker::drainResume()
183 if (params()->sys
->isTimingMode() && currState
) {
191 TableWalker::walk(const RequestPtr
&_req
, ThreadContext
*_tc
, uint16_t _asid
,
192 uint8_t _vmid
, bool _isHyp
, TLB::Mode _mode
,
193 TLB::Translation
*_trans
, bool _timing
, bool _functional
,
194 bool secure
, TLB::ArmTranslationType tranType
,
197 assert(!(_functional
&& _timing
));
200 WalkerState
*savedCurrState
= NULL
;
202 if (!currState
&& !_functional
) {
203 // For atomic mode, a new WalkerState instance should be only created
204 // once per TLB. For timing mode, a new instance is generated for every
206 DPRINTF(TLBVerbose
, "creating new instance of WalkerState\n");
208 currState
= new WalkerState();
209 currState
->tableWalker
= this;
210 } else if (_functional
) {
211 // If we are mixing functional mode with timing (or even
212 // atomic), we need to to be careful and clean up after
213 // ourselves to not risk getting into an inconsistent state.
214 DPRINTF(TLBVerbose
, "creating functional instance of WalkerState\n");
215 savedCurrState
= currState
;
216 currState
= new WalkerState();
217 currState
->tableWalker
= this;
218 } else if (_timing
) {
219 // This is a translation that was completed and then faulted again
220 // because some underlying parameters that affect the translation
221 // changed out from under us (e.g. asid). It will either be a
222 // misprediction, in which case nothing will happen or we'll use
223 // this fault to re-execute the faulting instruction which should clean
225 if (currState
->vaddr_tainted
== _req
->getVaddr()) {
226 ++statSquashedBefore
;
227 return std::make_shared
<ReExec
>();
232 currState
->startTime
= curTick();
234 // ARM DDI 0487A.f (ARMv8 ARM) pg J8-5672
235 // aarch32/translation/translation/AArch32.TranslateAddress dictates
236 // even AArch32 EL0 will use AArch64 translation if EL1 is in AArch64.
239 currState
->aarch64
= ELIs64(_tc
, EL2
);
242 TLB::tranTypeEL(_tc
->readMiscReg(MISCREG_CPSR
), tranType
);
244 ELIs64(_tc
, currState
->el
== EL0
? EL1
: currState
->el
);
246 currState
->transState
= _trans
;
247 currState
->req
= _req
;
248 currState
->fault
= NoFault
;
249 currState
->asid
= _asid
;
250 currState
->vmid
= _vmid
;
251 currState
->isHyp
= _isHyp
;
252 currState
->timing
= _timing
;
253 currState
->functional
= _functional
;
254 currState
->mode
= _mode
;
255 currState
->tranType
= tranType
;
256 currState
->isSecure
= secure
;
257 currState
->physAddrRange
= physAddrRange
;
259 /** @todo These should be cached or grabbed from cached copies in
260 the TLB, all these miscreg reads are expensive */
261 currState
->vaddr_tainted
= currState
->req
->getVaddr();
262 if (currState
->aarch64
)
263 currState
->vaddr
= purifyTaggedAddr(currState
->vaddr_tainted
,
264 currState
->tc
, currState
->el
);
266 currState
->vaddr
= currState
->vaddr_tainted
;
268 if (currState
->aarch64
) {
270 currState
->sctlr
= currState
->tc
->readMiscReg(MISCREG_SCTLR_EL1
);
271 currState
->vtcr
= currState
->tc
->readMiscReg(MISCREG_VTCR_EL2
);
272 } else switch (currState
->el
) {
275 currState
->sctlr
= currState
->tc
->readMiscReg(MISCREG_SCTLR_EL1
);
276 currState
->tcr
= currState
->tc
->readMiscReg(MISCREG_TCR_EL1
);
279 assert(_haveVirtualization
);
280 currState
->sctlr
= currState
->tc
->readMiscReg(MISCREG_SCTLR_EL2
);
281 currState
->tcr
= currState
->tc
->readMiscReg(MISCREG_TCR_EL2
);
284 assert(haveSecurity
);
285 currState
->sctlr
= currState
->tc
->readMiscReg(MISCREG_SCTLR_EL3
);
286 currState
->tcr
= currState
->tc
->readMiscReg(MISCREG_TCR_EL3
);
289 panic("Invalid exception level");
292 currState
->hcr
= currState
->tc
->readMiscReg(MISCREG_HCR_EL2
);
294 currState
->sctlr
= currState
->tc
->readMiscReg(snsBankedIndex(
295 MISCREG_SCTLR
, currState
->tc
, !currState
->isSecure
));
296 currState
->ttbcr
= currState
->tc
->readMiscReg(snsBankedIndex(
297 MISCREG_TTBCR
, currState
->tc
, !currState
->isSecure
));
298 currState
->htcr
= currState
->tc
->readMiscReg(MISCREG_HTCR
);
299 currState
->hcr
= currState
->tc
->readMiscReg(MISCREG_HCR
);
300 currState
->vtcr
= currState
->tc
->readMiscReg(MISCREG_VTCR
);
302 sctlr
= currState
->sctlr
;
304 currState
->isFetch
= (currState
->mode
== TLB::Execute
);
305 currState
->isWrite
= (currState
->mode
== TLB::Write
);
307 statRequestOrigin
[REQUESTED
][currState
->isFetch
]++;
309 currState
->stage2Req
= _stage2Req
&& !isStage2
;
311 bool long_desc_format
= currState
->aarch64
|| _isHyp
|| isStage2
||
312 longDescFormatInUse(currState
->tc
);
314 if (long_desc_format
) {
315 // Helper variables used for hierarchical permissions
316 currState
->secureLookup
= currState
->isSecure
;
317 currState
->rwTable
= true;
318 currState
->userTable
= true;
319 currState
->xnTable
= false;
320 currState
->pxnTable
= false;
322 ++statWalksLongDescriptor
;
324 ++statWalksShortDescriptor
;
327 if (!currState
->timing
) {
328 Fault fault
= NoFault
;
329 if (currState
->aarch64
)
330 fault
= processWalkAArch64();
331 else if (long_desc_format
)
332 fault
= processWalkLPAE();
334 fault
= processWalk();
336 // If this was a functional non-timing access restore state to
338 if (currState
->functional
) {
340 currState
= savedCurrState
;
345 if (pending
|| pendingQueue
.size()) {
346 pendingQueue
.push_back(currState
);
352 if (currState
->aarch64
)
353 return processWalkAArch64();
354 else if (long_desc_format
)
355 return processWalkLPAE();
357 return processWalk();
364 TableWalker::processWalkWrapper()
367 assert(pendingQueue
.size());
369 currState
= pendingQueue
.front();
371 // Check if a previous walk filled this request already
372 // @TODO Should this always be the TLB or should we look in the stage2 TLB?
373 TlbEntry
* te
= tlb
->lookup(currState
->vaddr
, currState
->asid
,
374 currState
->vmid
, currState
->isHyp
, currState
->isSecure
, true, false,
377 // Check if we still need to have a walk for this request. If the requesting
378 // instruction has been squashed, or a previous walk has filled the TLB with
379 // a match, we just want to get rid of the walk. The latter could happen
380 // when there are multiple outstanding misses to a single page and a
381 // previous request has been successfully translated.
382 if (!currState
->transState
->squashed() && !te
) {
383 // We've got a valid request, lets process it
385 pendingQueue
.pop_front();
386 // Keep currState in case one of the processWalk... calls NULLs it
387 WalkerState
*curr_state_copy
= currState
;
389 if (currState
->aarch64
)
390 f
= processWalkAArch64();
391 else if (longDescFormatInUse(currState
->tc
) ||
392 currState
->isHyp
|| isStage2
)
393 f
= processWalkLPAE();
398 curr_state_copy
->transState
->finish(f
, curr_state_copy
->req
,
399 curr_state_copy
->tc
, curr_state_copy
->mode
);
401 delete curr_state_copy
;
407 // If the instruction that we were translating for has been
408 // squashed we shouldn't bother.
409 unsigned num_squashed
= 0;
410 ThreadContext
*tc
= currState
->tc
;
411 while ((num_squashed
< numSquashable
) && currState
&&
412 (currState
->transState
->squashed() || te
)) {
413 pendingQueue
.pop_front();
415 statSquashedBefore
++;
417 DPRINTF(TLB
, "Squashing table walk for address %#x\n",
418 currState
->vaddr_tainted
);
420 if (currState
->transState
->squashed()) {
421 // finish the translation which will delete the translation object
422 currState
->transState
->finish(
423 std::make_shared
<UnimpFault
>("Squashed Inst"),
424 currState
->req
, currState
->tc
, currState
->mode
);
426 // translate the request now that we know it will work
427 statWalkServiceTime
.sample(curTick() - currState
->startTime
);
428 tlb
->translateTiming(currState
->req
, currState
->tc
,
429 currState
->transState
, currState
->mode
);
433 // delete the current request
436 // peak at the next one
437 if (pendingQueue
.size()) {
438 currState
= pendingQueue
.front();
439 te
= tlb
->lookup(currState
->vaddr
, currState
->asid
,
440 currState
->vmid
, currState
->isHyp
, currState
->isSecure
, true,
441 false, currState
->el
);
443 // Terminate the loop, nothing more to do
449 // if we still have pending translations, schedule more work
455 TableWalker::processWalk()
459 // For short descriptors, translation configs are held in
461 RegVal ttbr1
= currState
->tc
->readMiscReg(snsBankedIndex(
462 MISCREG_TTBR1
, currState
->tc
, !currState
->isSecure
));
464 const auto irgn0_mask
= 0x1;
465 const auto irgn1_mask
= 0x40;
466 currState
->isUncacheable
= (ttbr1
& (irgn0_mask
| irgn1_mask
)) == 0;
468 // If translation isn't enabled, we shouldn't be here
469 assert(currState
->sctlr
.m
|| isStage2
);
470 const bool is_atomic
= currState
->req
->isAtomic();
472 DPRINTF(TLB
, "Beginning table walk for address %#x, TTBCR: %#x, bits:%#x\n",
473 currState
->vaddr_tainted
, currState
->ttbcr
, mbits(currState
->vaddr
, 31,
474 32 - currState
->ttbcr
.n
));
476 statWalkWaitTime
.sample(curTick() - currState
->startTime
);
478 if (currState
->ttbcr
.n
== 0 || !mbits(currState
->vaddr
, 31,
479 32 - currState
->ttbcr
.n
)) {
480 DPRINTF(TLB
, " - Selecting TTBR0\n");
481 // Check if table walk is allowed when Security Extensions are enabled
482 if (haveSecurity
&& currState
->ttbcr
.pd0
) {
483 if (currState
->isFetch
)
484 return std::make_shared
<PrefetchAbort
>(
485 currState
->vaddr_tainted
,
486 ArmFault::TranslationLL
+ L1
,
490 return std::make_shared
<DataAbort
>(
491 currState
->vaddr_tainted
,
492 TlbEntry::DomainType::NoAccess
,
493 is_atomic
? false : currState
->isWrite
,
494 ArmFault::TranslationLL
+ L1
, isStage2
,
497 ttbr
= currState
->tc
->readMiscReg(snsBankedIndex(
498 MISCREG_TTBR0
, currState
->tc
, !currState
->isSecure
));
500 DPRINTF(TLB
, " - Selecting TTBR1\n");
501 // Check if table walk is allowed when Security Extensions are enabled
502 if (haveSecurity
&& currState
->ttbcr
.pd1
) {
503 if (currState
->isFetch
)
504 return std::make_shared
<PrefetchAbort
>(
505 currState
->vaddr_tainted
,
506 ArmFault::TranslationLL
+ L1
,
510 return std::make_shared
<DataAbort
>(
511 currState
->vaddr_tainted
,
512 TlbEntry::DomainType::NoAccess
,
513 is_atomic
? false : currState
->isWrite
,
514 ArmFault::TranslationLL
+ L1
, isStage2
,
518 currState
->ttbcr
.n
= 0;
521 Addr l1desc_addr
= mbits(ttbr
, 31, 14 - currState
->ttbcr
.n
) |
522 (bits(currState
->vaddr
, 31 - currState
->ttbcr
.n
, 20) << 2);
523 DPRINTF(TLB
, " - Descriptor at address %#x (%s)\n", l1desc_addr
,
524 currState
->isSecure
? "s" : "ns");
526 // Trickbox address check
528 f
= testWalk(l1desc_addr
, sizeof(uint32_t),
529 TlbEntry::DomainType::NoAccess
, L1
);
531 DPRINTF(TLB
, "Trickbox check caused fault on %#x\n", currState
->vaddr_tainted
);
532 if (currState
->timing
) {
534 nextWalk(currState
->tc
);
537 currState
->tc
= NULL
;
538 currState
->req
= NULL
;
543 Request::Flags flag
= Request::PT_WALK
;
544 if (currState
->sctlr
.c
== 0 || currState
->isUncacheable
) {
545 flag
.set(Request::UNCACHEABLE
);
548 if (currState
->isSecure
) {
549 flag
.set(Request::SECURE
);
553 delayed
= fetchDescriptor(l1desc_addr
, (uint8_t*)&currState
->l1Desc
.data
,
554 sizeof(uint32_t), flag
, L1
, &doL1DescEvent
,
555 &TableWalker::doL1Descriptor
);
557 f
= currState
->fault
;
564 TableWalker::processWalkLPAE()
566 Addr ttbr
, ttbr0_max
, ttbr1_min
, desc_addr
;
568 LookupLevel start_lookup_level
= L1
;
570 DPRINTF(TLB
, "Beginning table walk for address %#x, TTBCR: %#x\n",
571 currState
->vaddr_tainted
, currState
->ttbcr
);
573 statWalkWaitTime
.sample(curTick() - currState
->startTime
);
575 Request::Flags flag
= Request::PT_WALK
;
576 if (currState
->isSecure
)
577 flag
.set(Request::SECURE
);
579 // work out which base address register to use, if in hyp mode we always
582 DPRINTF(TLB
, " - Selecting VTTBR (long-desc.)\n");
583 ttbr
= currState
->tc
->readMiscReg(MISCREG_VTTBR
);
584 tsz
= sext
<4>(currState
->vtcr
.t0sz
);
585 start_lookup_level
= currState
->vtcr
.sl0
? L1
: L2
;
586 currState
->isUncacheable
= currState
->vtcr
.irgn0
== 0;
587 } else if (currState
->isHyp
) {
588 DPRINTF(TLB
, " - Selecting HTTBR (long-desc.)\n");
589 ttbr
= currState
->tc
->readMiscReg(MISCREG_HTTBR
);
590 tsz
= currState
->htcr
.t0sz
;
591 currState
->isUncacheable
= currState
->htcr
.irgn0
== 0;
593 assert(longDescFormatInUse(currState
->tc
));
595 // Determine boundaries of TTBR0/1 regions
596 if (currState
->ttbcr
.t0sz
)
597 ttbr0_max
= (1ULL << (32 - currState
->ttbcr
.t0sz
)) - 1;
598 else if (currState
->ttbcr
.t1sz
)
599 ttbr0_max
= (1ULL << 32) -
600 (1ULL << (32 - currState
->ttbcr
.t1sz
)) - 1;
602 ttbr0_max
= (1ULL << 32) - 1;
603 if (currState
->ttbcr
.t1sz
)
604 ttbr1_min
= (1ULL << 32) - (1ULL << (32 - currState
->ttbcr
.t1sz
));
606 ttbr1_min
= (1ULL << (32 - currState
->ttbcr
.t0sz
));
608 const bool is_atomic
= currState
->req
->isAtomic();
610 // The following code snippet selects the appropriate translation table base
611 // address (TTBR0 or TTBR1) and the appropriate starting lookup level
612 // depending on the address range supported by the translation table (ARM
613 // ARM issue C B3.6.4)
614 if (currState
->vaddr
<= ttbr0_max
) {
615 DPRINTF(TLB
, " - Selecting TTBR0 (long-desc.)\n");
616 // Check if table walk is allowed
617 if (currState
->ttbcr
.epd0
) {
618 if (currState
->isFetch
)
619 return std::make_shared
<PrefetchAbort
>(
620 currState
->vaddr_tainted
,
621 ArmFault::TranslationLL
+ L1
,
625 return std::make_shared
<DataAbort
>(
626 currState
->vaddr_tainted
,
627 TlbEntry::DomainType::NoAccess
,
628 is_atomic
? false : currState
->isWrite
,
629 ArmFault::TranslationLL
+ L1
,
633 ttbr
= currState
->tc
->readMiscReg(snsBankedIndex(
634 MISCREG_TTBR0
, currState
->tc
, !currState
->isSecure
));
635 tsz
= currState
->ttbcr
.t0sz
;
636 currState
->isUncacheable
= currState
->ttbcr
.irgn0
== 0;
637 if (ttbr0_max
< (1ULL << 30)) // Upper limit < 1 GB
638 start_lookup_level
= L2
;
639 } else if (currState
->vaddr
>= ttbr1_min
) {
640 DPRINTF(TLB
, " - Selecting TTBR1 (long-desc.)\n");
641 // Check if table walk is allowed
642 if (currState
->ttbcr
.epd1
) {
643 if (currState
->isFetch
)
644 return std::make_shared
<PrefetchAbort
>(
645 currState
->vaddr_tainted
,
646 ArmFault::TranslationLL
+ L1
,
650 return std::make_shared
<DataAbort
>(
651 currState
->vaddr_tainted
,
652 TlbEntry::DomainType::NoAccess
,
653 is_atomic
? false : currState
->isWrite
,
654 ArmFault::TranslationLL
+ L1
,
658 ttbr
= currState
->tc
->readMiscReg(snsBankedIndex(
659 MISCREG_TTBR1
, currState
->tc
, !currState
->isSecure
));
660 tsz
= currState
->ttbcr
.t1sz
;
661 currState
->isUncacheable
= currState
->ttbcr
.irgn1
== 0;
662 // Lower limit >= 3 GB
663 if (ttbr1_min
>= (1ULL << 31) + (1ULL << 30))
664 start_lookup_level
= L2
;
666 // Out of boundaries -> translation fault
667 if (currState
->isFetch
)
668 return std::make_shared
<PrefetchAbort
>(
669 currState
->vaddr_tainted
,
670 ArmFault::TranslationLL
+ L1
,
674 return std::make_shared
<DataAbort
>(
675 currState
->vaddr_tainted
,
676 TlbEntry::DomainType::NoAccess
,
677 is_atomic
? false : currState
->isWrite
,
678 ArmFault::TranslationLL
+ L1
,
679 isStage2
, ArmFault::LpaeTran
);
684 // Perform lookup (ARM ARM issue C B3.6.6)
685 if (start_lookup_level
== L1
) {
687 desc_addr
= mbits(ttbr
, 39, n
) |
688 (bits(currState
->vaddr
, n
+ 26, 30) << 3);
689 DPRINTF(TLB
, " - Descriptor at address %#x (%s) (long-desc.)\n",
690 desc_addr
, currState
->isSecure
? "s" : "ns");
692 // Skip first-level lookup
693 n
= (tsz
>= 2 ? 14 - tsz
: 12);
694 desc_addr
= mbits(ttbr
, 39, n
) |
695 (bits(currState
->vaddr
, n
+ 17, 21) << 3);
696 DPRINTF(TLB
, " - Descriptor at address %#x (%s) (long-desc.)\n",
697 desc_addr
, currState
->isSecure
? "s" : "ns");
700 // Trickbox address check
701 Fault f
= testWalk(desc_addr
, sizeof(uint64_t),
702 TlbEntry::DomainType::NoAccess
, start_lookup_level
);
704 DPRINTF(TLB
, "Trickbox check caused fault on %#x\n", currState
->vaddr_tainted
);
705 if (currState
->timing
) {
707 nextWalk(currState
->tc
);
710 currState
->tc
= NULL
;
711 currState
->req
= NULL
;
716 if (currState
->sctlr
.c
== 0 || currState
->isUncacheable
) {
717 flag
.set(Request::UNCACHEABLE
);
720 currState
->longDesc
.lookupLevel
= start_lookup_level
;
721 currState
->longDesc
.aarch64
= false;
722 currState
->longDesc
.grainSize
= Grain4KB
;
724 bool delayed
= fetchDescriptor(desc_addr
, (uint8_t*)&currState
->longDesc
.data
,
725 sizeof(uint64_t), flag
, start_lookup_level
,
726 LongDescEventByLevel
[start_lookup_level
],
727 &TableWalker::doLongDescriptor
);
729 f
= currState
->fault
;
736 TableWalker::adjustTableSizeAArch64(unsigned tsz
)
746 TableWalker::checkAddrSizeFaultAArch64(Addr addr
, int currPhysAddrRange
)
748 return (currPhysAddrRange
!= MaxPhysAddrRange
&&
749 bits(addr
, MaxPhysAddrRange
- 1, currPhysAddrRange
));
753 TableWalker::processWalkAArch64()
755 assert(currState
->aarch64
);
757 DPRINTF(TLB
, "Beginning table walk for address %#llx, TCR: %#llx\n",
758 currState
->vaddr_tainted
, currState
->tcr
);
760 static const GrainSize GrainMap_tg0
[] =
761 { Grain4KB
, Grain64KB
, Grain16KB
, ReservedGrain
};
762 static const GrainSize GrainMap_tg1
[] =
763 { ReservedGrain
, Grain16KB
, Grain4KB
, Grain64KB
};
765 statWalkWaitTime
.sample(curTick() - currState
->startTime
);
767 // Determine TTBR, table size, granule size and phys. address range
770 GrainSize tg
= Grain4KB
; // grain size computed from tg* field
773 LookupLevel start_lookup_level
= MAX_LOOKUP_LEVELS
;
775 switch (currState
->el
) {
779 DPRINTF(TLB
, " - Selecting VTTBR0 (AArch64 stage 2)\n");
780 ttbr
= currState
->tc
->readMiscReg(MISCREG_VTTBR_EL2
);
781 tsz
= 64 - currState
->vtcr
.t0sz64
;
782 tg
= GrainMap_tg0
[currState
->vtcr
.tg0
];
783 // ARM DDI 0487A.f D7-2148
784 // The starting level of stage 2 translation depends on
785 // VTCR_EL2.SL0 and VTCR_EL2.TG0
786 LookupLevel __
= MAX_LOOKUP_LEVELS
; // invalid level
787 uint8_t sl_tg
= (currState
->vtcr
.sl0
<< 2) | currState
->vtcr
.tg0
;
788 static const LookupLevel SLL
[] = {
789 L2
, L3
, L3
, __
, // sl0 == 0
790 L1
, L2
, L2
, __
, // sl0 == 1, etc.
794 start_lookup_level
= SLL
[sl_tg
];
795 panic_if(start_lookup_level
== MAX_LOOKUP_LEVELS
,
796 "Cannot discern lookup level from vtcr.{sl0,tg0}");
797 ps
= currState
->vtcr
.ps
;
798 currState
->isUncacheable
= currState
->vtcr
.irgn0
== 0;
800 switch (bits(currState
->vaddr
, 63,48)) {
802 DPRINTF(TLB
, " - Selecting TTBR0 (AArch64)\n");
803 ttbr
= currState
->tc
->readMiscReg(MISCREG_TTBR0_EL1
);
804 tsz
= adjustTableSizeAArch64(64 - currState
->tcr
.t0sz
);
805 tg
= GrainMap_tg0
[currState
->tcr
.tg0
];
806 currState
->hpd
= currState
->tcr
.hpd0
;
807 currState
->isUncacheable
= currState
->tcr
.irgn0
== 0;
808 if (bits(currState
->vaddr
, 63, tsz
) != 0x0 ||
813 DPRINTF(TLB
, " - Selecting TTBR1 (AArch64)\n");
814 ttbr
= currState
->tc
->readMiscReg(MISCREG_TTBR1_EL1
);
815 tsz
= adjustTableSizeAArch64(64 - currState
->tcr
.t1sz
);
816 tg
= GrainMap_tg1
[currState
->tcr
.tg1
];
817 currState
->hpd
= currState
->tcr
.hpd1
;
818 currState
->isUncacheable
= currState
->tcr
.irgn1
== 0;
819 if (bits(currState
->vaddr
, 63, tsz
) != mask(64-tsz
) ||
824 // top two bytes must be all 0s or all 1s, else invalid addr
827 ps
= currState
->tcr
.ips
;
831 switch(bits(currState
->vaddr
, 63,48)) {
833 DPRINTF(TLB
, " - Selecting TTBR0 (AArch64)\n");
834 ttbr
= currState
->tc
->readMiscReg(MISCREG_TTBR0_EL2
);
835 tsz
= adjustTableSizeAArch64(64 - currState
->tcr
.t0sz
);
836 tg
= GrainMap_tg0
[currState
->tcr
.tg0
];
837 currState
->hpd
= currState
->hcr
.e2h
?
838 currState
->tcr
.hpd0
: currState
->tcr
.hpd
;
839 currState
->isUncacheable
= currState
->tcr
.irgn0
== 0;
843 DPRINTF(TLB
, " - Selecting TTBR1 (AArch64)\n");
844 ttbr
= currState
->tc
->readMiscReg(MISCREG_TTBR1_EL2
);
845 tsz
= adjustTableSizeAArch64(64 - currState
->tcr
.t1sz
);
846 tg
= GrainMap_tg1
[currState
->tcr
.tg1
];
847 currState
->hpd
= currState
->tcr
.hpd1
;
848 currState
->isUncacheable
= currState
->tcr
.irgn1
== 0;
849 if (bits(currState
->vaddr
, 63, tsz
) != mask(64-tsz
) ||
850 currState
->tcr
.epd1
|| !currState
->hcr
.e2h
)
855 // invalid addr if top two bytes are not all 0s
858 ps
= currState
->tcr
.ps
;
861 switch(bits(currState
->vaddr
, 63,48)) {
863 DPRINTF(TLB
, " - Selecting TTBR0 (AArch64)\n");
864 ttbr
= currState
->tc
->readMiscReg(MISCREG_TTBR0_EL3
);
865 tsz
= adjustTableSizeAArch64(64 - currState
->tcr
.t0sz
);
866 tg
= GrainMap_tg0
[currState
->tcr
.tg0
];
867 currState
->hpd
= currState
->tcr
.hpd
;
868 currState
->isUncacheable
= currState
->tcr
.irgn0
== 0;
871 // invalid addr if top two bytes are not all 0s
874 ps
= currState
->tcr
.ps
;
878 const bool is_atomic
= currState
->req
->isAtomic();
882 if (currState
->isFetch
)
883 f
= std::make_shared
<PrefetchAbort
>(
884 currState
->vaddr_tainted
,
885 ArmFault::TranslationLL
+ L0
, isStage2
,
888 f
= std::make_shared
<DataAbort
>(
889 currState
->vaddr_tainted
,
890 TlbEntry::DomainType::NoAccess
,
891 is_atomic
? false : currState
->isWrite
,
892 ArmFault::TranslationLL
+ L0
,
893 isStage2
, ArmFault::LpaeTran
);
895 if (currState
->timing
) {
897 nextWalk(currState
->tc
);
900 currState
->tc
= NULL
;
901 currState
->req
= NULL
;
907 if (tg
== ReservedGrain
) {
908 warn_once("Reserved granule size requested; gem5's IMPLEMENTATION "
909 "DEFINED behavior takes this to mean 4KB granules\n");
913 // Determine starting lookup level
914 // See aarch64/translation/walk in Appendix G: ARMv8 Pseudocode Library
915 // in ARM DDI 0487A. These table values correspond to the cascading tests
916 // to compute the lookup level and are of the form
917 // (grain_size + N*stride), for N = {1, 2, 3}.
918 // A value of 64 will never succeed and a value of 0 will always succeed.
919 if (start_lookup_level
== MAX_LOOKUP_LEVELS
) {
921 GrainSize grain_size
;
922 unsigned lookup_level_cutoff
[MAX_LOOKUP_LEVELS
];
924 static const GrainMap GM
[] = {
925 { Grain4KB
, { 39, 30, 0, 0 } },
926 { Grain16KB
, { 47, 36, 25, 0 } },
927 { Grain64KB
, { 64, 42, 29, 0 } }
930 const unsigned *lookup
= NULL
; // points to a lookup_level_cutoff
932 for (unsigned i
= 0; i
< 3; ++i
) { // choose entry of GM[]
933 if (tg
== GM
[i
].grain_size
) {
934 lookup
= GM
[i
].lookup_level_cutoff
;
940 for (int L
= L0
; L
!= MAX_LOOKUP_LEVELS
; ++L
) {
941 if (tsz
> lookup
[L
]) {
942 start_lookup_level
= (LookupLevel
) L
;
946 panic_if(start_lookup_level
== MAX_LOOKUP_LEVELS
,
947 "Table walker couldn't find lookup level\n");
952 // Determine table base address
953 int base_addr_lo
= 3 + tsz
- stride
* (3 - start_lookup_level
) - tg
;
954 Addr base_addr
= mbits(ttbr
, 47, base_addr_lo
);
956 // Determine physical address size and raise an Address Size Fault if
958 int pa_range
= decodePhysAddrRange64(ps
);
959 // Clamp to lower limit
960 if (pa_range
> physAddrRange
)
961 currState
->physAddrRange
= physAddrRange
;
963 currState
->physAddrRange
= pa_range
;
964 if (checkAddrSizeFaultAArch64(base_addr
, currState
->physAddrRange
)) {
965 DPRINTF(TLB
, "Address size fault before any lookup\n");
967 if (currState
->isFetch
)
968 f
= std::make_shared
<PrefetchAbort
>(
969 currState
->vaddr_tainted
,
970 ArmFault::AddressSizeLL
+ start_lookup_level
,
974 f
= std::make_shared
<DataAbort
>(
975 currState
->vaddr_tainted
,
976 TlbEntry::DomainType::NoAccess
,
977 is_atomic
? false : currState
->isWrite
,
978 ArmFault::AddressSizeLL
+ start_lookup_level
,
983 if (currState
->timing
) {
985 nextWalk(currState
->tc
);
988 currState
->tc
= NULL
;
989 currState
->req
= NULL
;
995 // Determine descriptor address
996 Addr desc_addr
= base_addr
|
997 (bits(currState
->vaddr
, tsz
- 1,
998 stride
* (3 - start_lookup_level
) + tg
) << 3);
1000 // Trickbox address check
1001 Fault f
= testWalk(desc_addr
, sizeof(uint64_t),
1002 TlbEntry::DomainType::NoAccess
, start_lookup_level
);
1004 DPRINTF(TLB
, "Trickbox check caused fault on %#x\n", currState
->vaddr_tainted
);
1005 if (currState
->timing
) {
1007 nextWalk(currState
->tc
);
1010 currState
->tc
= NULL
;
1011 currState
->req
= NULL
;
1016 Request::Flags flag
= Request::PT_WALK
;
1017 if (currState
->sctlr
.c
== 0 || currState
->isUncacheable
) {
1018 flag
.set(Request::UNCACHEABLE
);
1021 if (currState
->isSecure
) {
1022 flag
.set(Request::SECURE
);
1025 currState
->longDesc
.lookupLevel
= start_lookup_level
;
1026 currState
->longDesc
.aarch64
= true;
1027 currState
->longDesc
.grainSize
= tg
;
1029 if (currState
->timing
) {
1030 fetchDescriptor(desc_addr
, (uint8_t*) &currState
->longDesc
.data
,
1031 sizeof(uint64_t), flag
, start_lookup_level
,
1032 LongDescEventByLevel
[start_lookup_level
], NULL
);
1034 fetchDescriptor(desc_addr
, (uint8_t*)&currState
->longDesc
.data
,
1035 sizeof(uint64_t), flag
, -1, NULL
,
1036 &TableWalker::doLongDescriptor
);
1037 f
= currState
->fault
;
1044 TableWalker::memAttrs(ThreadContext
*tc
, TlbEntry
&te
, SCTLR sctlr
,
1045 uint8_t texcb
, bool s
)
1047 // Note: tc and sctlr local variables are hiding tc and sctrl class
1049 DPRINTF(TLBVerbose
, "memAttrs texcb:%d s:%d\n", texcb
, s
);
1050 te
.shareable
= false; // default value
1051 te
.nonCacheable
= false;
1052 te
.outerShareable
= false;
1053 if (sctlr
.tre
== 0 || ((sctlr
.tre
== 1) && (sctlr
.m
== 0))) {
1055 case 0: // Stongly-ordered
1056 te
.nonCacheable
= true;
1057 te
.mtype
= TlbEntry::MemoryType::StronglyOrdered
;
1058 te
.shareable
= true;
1062 case 1: // Shareable Device
1063 te
.nonCacheable
= true;
1064 te
.mtype
= TlbEntry::MemoryType::Device
;
1065 te
.shareable
= true;
1069 case 2: // Outer and Inner Write-Through, no Write-Allocate
1070 te
.mtype
= TlbEntry::MemoryType::Normal
;
1073 te
.outerAttrs
= bits(texcb
, 1, 0);
1075 case 3: // Outer and Inner Write-Back, no Write-Allocate
1076 te
.mtype
= TlbEntry::MemoryType::Normal
;
1079 te
.outerAttrs
= bits(texcb
, 1, 0);
1081 case 4: // Outer and Inner Non-cacheable
1082 te
.nonCacheable
= true;
1083 te
.mtype
= TlbEntry::MemoryType::Normal
;
1086 te
.outerAttrs
= bits(texcb
, 1, 0);
1089 panic("Reserved texcb value!\n");
1091 case 6: // Implementation Defined
1092 panic("Implementation-defined texcb value!\n");
1094 case 7: // Outer and Inner Write-Back, Write-Allocate
1095 te
.mtype
= TlbEntry::MemoryType::Normal
;
1100 case 8: // Non-shareable Device
1101 te
.nonCacheable
= true;
1102 te
.mtype
= TlbEntry::MemoryType::Device
;
1103 te
.shareable
= false;
1107 case 9 ... 15: // Reserved
1108 panic("Reserved texcb value!\n");
1110 case 16 ... 31: // Cacheable Memory
1111 te
.mtype
= TlbEntry::MemoryType::Normal
;
1113 if (bits(texcb
, 1,0) == 0 || bits(texcb
, 3,2) == 0)
1114 te
.nonCacheable
= true;
1115 te
.innerAttrs
= bits(texcb
, 1, 0);
1116 te
.outerAttrs
= bits(texcb
, 3, 2);
1119 panic("More than 32 states for 5 bits?\n");
1123 PRRR prrr
= tc
->readMiscReg(snsBankedIndex(MISCREG_PRRR
,
1124 currState
->tc
, !currState
->isSecure
));
1125 NMRR nmrr
= tc
->readMiscReg(snsBankedIndex(MISCREG_NMRR
,
1126 currState
->tc
, !currState
->isSecure
));
1127 DPRINTF(TLBVerbose
, "memAttrs PRRR:%08x NMRR:%08x\n", prrr
, nmrr
);
1128 uint8_t curr_tr
= 0, curr_ir
= 0, curr_or
= 0;
1129 switch(bits(texcb
, 2,0)) {
1134 te
.outerShareable
= (prrr
.nos0
== 0);
1140 te
.outerShareable
= (prrr
.nos1
== 0);
1146 te
.outerShareable
= (prrr
.nos2
== 0);
1152 te
.outerShareable
= (prrr
.nos3
== 0);
1158 te
.outerShareable
= (prrr
.nos4
== 0);
1164 te
.outerShareable
= (prrr
.nos5
== 0);
1167 panic("Imp defined type\n");
1172 te
.outerShareable
= (prrr
.nos7
== 0);
1178 DPRINTF(TLBVerbose
, "StronglyOrdered\n");
1179 te
.mtype
= TlbEntry::MemoryType::StronglyOrdered
;
1180 te
.nonCacheable
= true;
1183 te
.shareable
= true;
1186 DPRINTF(TLBVerbose
, "Device ds1:%d ds0:%d s:%d\n",
1187 prrr
.ds1
, prrr
.ds0
, s
);
1188 te
.mtype
= TlbEntry::MemoryType::Device
;
1189 te
.nonCacheable
= true;
1193 te
.shareable
= true;
1195 te
.shareable
= true;
1198 DPRINTF(TLBVerbose
, "Normal ns1:%d ns0:%d s:%d\n",
1199 prrr
.ns1
, prrr
.ns0
, s
);
1200 te
.mtype
= TlbEntry::MemoryType::Normal
;
1202 te
.shareable
= true;
1204 te
.shareable
= true;
1207 panic("Reserved type");
1210 if (te
.mtype
== TlbEntry::MemoryType::Normal
){
1213 te
.nonCacheable
= true;
1229 te
.nonCacheable
= true;
1244 DPRINTF(TLBVerbose
, "memAttrs: shareable: %d, innerAttrs: %d, "
1246 te
.shareable
, te
.innerAttrs
, te
.outerAttrs
);
1247 te
.setAttributes(false);
1251 TableWalker::memAttrsLPAE(ThreadContext
*tc
, TlbEntry
&te
,
1252 LongDescriptor
&lDescriptor
)
1257 uint8_t sh
= lDescriptor
.sh();
1258 // Different format and source of attributes if this is a stage 2
1261 attr
= lDescriptor
.memAttr();
1262 uint8_t attr_3_2
= (attr
>> 2) & 0x3;
1263 uint8_t attr_1_0
= attr
& 0x3;
1265 DPRINTF(TLBVerbose
, "memAttrsLPAE MemAttr:%#x sh:%#x\n", attr
, sh
);
1267 if (attr_3_2
== 0) {
1268 te
.mtype
= attr_1_0
== 0 ? TlbEntry::MemoryType::StronglyOrdered
1269 : TlbEntry::MemoryType::Device
;
1271 te
.innerAttrs
= attr_1_0
== 0 ? 1 : 3;
1272 te
.nonCacheable
= true;
1274 te
.mtype
= TlbEntry::MemoryType::Normal
;
1275 te
.outerAttrs
= attr_3_2
== 1 ? 0 :
1276 attr_3_2
== 2 ? 2 : 1;
1277 te
.innerAttrs
= attr_1_0
== 1 ? 0 :
1278 attr_1_0
== 2 ? 6 : 5;
1279 te
.nonCacheable
= (attr_3_2
== 1) || (attr_1_0
== 1);
1282 uint8_t attrIndx
= lDescriptor
.attrIndx();
1284 // LPAE always uses remapping of memory attributes, irrespective of the
1285 // value of SCTLR.TRE
1286 MiscRegIndex reg
= attrIndx
& 0x4 ? MISCREG_MAIR1
: MISCREG_MAIR0
;
1287 int reg_as_int
= snsBankedIndex(reg
, currState
->tc
,
1288 !currState
->isSecure
);
1289 uint32_t mair
= currState
->tc
->readMiscReg(reg_as_int
);
1290 attr
= (mair
>> (8 * (attrIndx
% 4))) & 0xff;
1291 uint8_t attr_7_4
= bits(attr
, 7, 4);
1292 uint8_t attr_3_0
= bits(attr
, 3, 0);
1293 DPRINTF(TLBVerbose
, "memAttrsLPAE AttrIndx:%#x sh:%#x, attr %#x\n", attrIndx
, sh
, attr
);
1295 // Note: the memory subsystem only cares about the 'cacheable' memory
1296 // attribute. The other attributes are only used to fill the PAR register
1297 // accordingly to provide the illusion of full support
1298 te
.nonCacheable
= false;
1302 // Strongly-ordered or Device memory
1303 if (attr_3_0
== 0x0)
1304 te
.mtype
= TlbEntry::MemoryType::StronglyOrdered
;
1305 else if (attr_3_0
== 0x4)
1306 te
.mtype
= TlbEntry::MemoryType::Device
;
1308 panic("Unpredictable behavior\n");
1309 te
.nonCacheable
= true;
1313 // Normal memory, Outer Non-cacheable
1314 te
.mtype
= TlbEntry::MemoryType::Normal
;
1316 if (attr_3_0
== 0x4)
1317 // Inner Non-cacheable
1318 te
.nonCacheable
= true;
1319 else if (attr_3_0
< 0x8)
1320 panic("Unpredictable behavior\n");
1330 if (attr_7_4
& 0x4) {
1331 te
.outerAttrs
= (attr_7_4
& 1) ? 1 : 3;
1333 te
.outerAttrs
= 0x2;
1335 // Normal memory, Outer Cacheable
1336 te
.mtype
= TlbEntry::MemoryType::Normal
;
1337 if (attr_3_0
!= 0x4 && attr_3_0
< 0x8)
1338 panic("Unpredictable behavior\n");
1341 panic("Unpredictable behavior\n");
1347 te
.innerAttrs
= 0x1;
1350 te
.innerAttrs
= attr_7_4
== 0 ? 0x3 : 0;
1362 te
.innerAttrs
= attr_3_0
& 1 ? 0x5 : 0x7;
1365 panic("Unpredictable behavior\n");
1370 te
.outerShareable
= sh
== 2;
1371 te
.shareable
= (sh
& 0x2) ? true : false;
1372 te
.setAttributes(true);
1373 te
.attributes
|= (uint64_t) attr
<< 56;
1377 TableWalker::memAttrsAArch64(ThreadContext
*tc
, TlbEntry
&te
,
1378 LongDescriptor
&lDescriptor
)
1383 uint8_t sh
= lDescriptor
.sh();
1386 attr
= lDescriptor
.memAttr();
1387 uint8_t attr_hi
= (attr
>> 2) & 0x3;
1388 uint8_t attr_lo
= attr
& 0x3;
1390 DPRINTF(TLBVerbose
, "memAttrsAArch64 MemAttr:%#x sh:%#x\n", attr
, sh
);
1393 te
.mtype
= attr_lo
== 0 ? TlbEntry::MemoryType::StronglyOrdered
1394 : TlbEntry::MemoryType::Device
;
1396 te
.innerAttrs
= attr_lo
== 0 ? 1 : 3;
1397 te
.nonCacheable
= true;
1399 te
.mtype
= TlbEntry::MemoryType::Normal
;
1400 te
.outerAttrs
= attr_hi
== 1 ? 0 :
1401 attr_hi
== 2 ? 2 : 1;
1402 te
.innerAttrs
= attr_lo
== 1 ? 0 :
1403 attr_lo
== 2 ? 6 : 5;
1404 // Treat write-through memory as uncacheable, this is safe
1405 // but for performance reasons not optimal.
1406 te
.nonCacheable
= (attr_hi
== 1) || (attr_hi
== 2) ||
1407 (attr_lo
== 1) || (attr_lo
== 2);
1410 uint8_t attrIndx
= lDescriptor
.attrIndx();
1412 DPRINTF(TLBVerbose
, "memAttrsAArch64 AttrIndx:%#x sh:%#x\n", attrIndx
, sh
);
1416 switch (currState
->el
) {
1419 mair
= tc
->readMiscReg(MISCREG_MAIR_EL1
);
1422 mair
= tc
->readMiscReg(MISCREG_MAIR_EL2
);
1425 mair
= tc
->readMiscReg(MISCREG_MAIR_EL3
);
1428 panic("Invalid exception level");
1432 // Select attributes
1433 attr
= bits(mair
, 8 * attrIndx
+ 7, 8 * attrIndx
);
1434 attr_lo
= bits(attr
, 3, 0);
1435 attr_hi
= bits(attr
, 7, 4);
1438 te
.mtype
= attr_hi
== 0 ? TlbEntry::MemoryType::Device
: TlbEntry::MemoryType::Normal
;
1441 te
.nonCacheable
= false;
1442 if (te
.mtype
== TlbEntry::MemoryType::Device
) { // Device memory
1443 te
.nonCacheable
= true;
1445 // Treat write-through memory as uncacheable, this is safe
1446 // but for performance reasons not optimal.
1448 case 0x1 ... 0x3: // Normal Memory, Outer Write-through transient
1449 case 0x4: // Normal memory, Outer Non-cacheable
1450 case 0x8 ... 0xb: // Normal Memory, Outer Write-through non-transient
1451 te
.nonCacheable
= true;
1454 case 0x1 ... 0x3: // Normal Memory, Inner Write-through transient
1455 case 0x9 ... 0xb: // Normal Memory, Inner Write-through non-transient
1456 warn_if(!attr_hi
, "Unpredictable behavior");
1458 case 0x4: // Device-nGnRE memory or
1459 // Normal memory, Inner Non-cacheable
1460 case 0x8: // Device-nGRE memory or
1461 // Normal memory, Inner Write-through non-transient
1462 te
.nonCacheable
= true;
1465 te
.shareable
= sh
== 2;
1466 te
.outerShareable
= (sh
& 0x2) ? true : false;
1467 // Attributes formatted according to the 64-bit PAR
1468 te
.attributes
= ((uint64_t) attr
<< 56) |
1469 (1 << 11) | // LPAE bit
1470 (te
.ns
<< 9) | // NS bit
1476 TableWalker::doL1Descriptor()
1478 if (currState
->fault
!= NoFault
) {
1482 currState
->l1Desc
.data
= htog(currState
->l1Desc
.data
,
1483 byteOrder(currState
->tc
));
1485 DPRINTF(TLB
, "L1 descriptor for %#x is %#x\n",
1486 currState
->vaddr_tainted
, currState
->l1Desc
.data
);
1489 const bool is_atomic
= currState
->req
->isAtomic();
1491 switch (currState
->l1Desc
.type()) {
1492 case L1Descriptor::Ignore
:
1493 case L1Descriptor::Reserved
:
1494 if (!currState
->timing
) {
1495 currState
->tc
= NULL
;
1496 currState
->req
= NULL
;
1498 DPRINTF(TLB
, "L1 Descriptor Reserved/Ignore, causing fault\n");
1499 if (currState
->isFetch
)
1501 std::make_shared
<PrefetchAbort
>(
1502 currState
->vaddr_tainted
,
1503 ArmFault::TranslationLL
+ L1
,
1505 ArmFault::VmsaTran
);
1508 std::make_shared
<DataAbort
>(
1509 currState
->vaddr_tainted
,
1510 TlbEntry::DomainType::NoAccess
,
1511 is_atomic
? false : currState
->isWrite
,
1512 ArmFault::TranslationLL
+ L1
, isStage2
,
1513 ArmFault::VmsaTran
);
1515 case L1Descriptor::Section
:
1516 if (currState
->sctlr
.afe
&& bits(currState
->l1Desc
.ap(), 0) == 0) {
1517 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is
1518 * enabled if set, do l1.Desc.setAp0() instead of generating
1522 currState
->fault
= std::make_shared
<DataAbort
>(
1523 currState
->vaddr_tainted
,
1524 currState
->l1Desc
.domain(),
1525 is_atomic
? false : currState
->isWrite
,
1526 ArmFault::AccessFlagLL
+ L1
,
1528 ArmFault::VmsaTran
);
1530 if (currState
->l1Desc
.supersection()) {
1531 panic("Haven't implemented supersections\n");
1533 insertTableEntry(currState
->l1Desc
, false);
1535 case L1Descriptor::PageTable
:
1538 l2desc_addr
= currState
->l1Desc
.l2Addr() |
1539 (bits(currState
->vaddr
, 19, 12) << 2);
1540 DPRINTF(TLB
, "L1 descriptor points to page table at: %#x (%s)\n",
1541 l2desc_addr
, currState
->isSecure
? "s" : "ns");
1543 // Trickbox address check
1544 currState
->fault
= testWalk(l2desc_addr
, sizeof(uint32_t),
1545 currState
->l1Desc
.domain(), L2
);
1547 if (currState
->fault
) {
1548 if (!currState
->timing
) {
1549 currState
->tc
= NULL
;
1550 currState
->req
= NULL
;
1555 Request::Flags flag
= Request::PT_WALK
;
1557 if (currState
->sctlr
.c
== 0 || currState
->isUncacheable
) {
1558 flag
.set(Request::UNCACHEABLE
);
1561 if (currState
->isSecure
)
1562 flag
.set(Request::SECURE
);
1565 delayed
= fetchDescriptor(l2desc_addr
,
1566 (uint8_t*)&currState
->l2Desc
.data
,
1567 sizeof(uint32_t), flag
, -1, &doL2DescEvent
,
1568 &TableWalker::doL2Descriptor
);
1570 currState
->delayed
= true;
1576 panic("A new type in a 2 bit field?\n");
1581 TableWalker::generateLongDescFault(ArmFault::FaultSource src
)
1583 if (currState
->isFetch
) {
1584 return std::make_shared
<PrefetchAbort
>(
1585 currState
->vaddr_tainted
,
1586 src
+ currState
->longDesc
.lookupLevel
,
1588 ArmFault::LpaeTran
);
1590 return std::make_shared
<DataAbort
>(
1591 currState
->vaddr_tainted
,
1592 TlbEntry::DomainType::NoAccess
,
1593 currState
->req
->isAtomic() ? false : currState
->isWrite
,
1594 src
+ currState
->longDesc
.lookupLevel
,
1596 ArmFault::LpaeTran
);
1601 TableWalker::doLongDescriptor()
1603 if (currState
->fault
!= NoFault
) {
1607 currState
->longDesc
.data
= htog(currState
->longDesc
.data
,
1608 byteOrder(currState
->tc
));
1610 DPRINTF(TLB
, "L%d descriptor for %#llx is %#llx (%s)\n",
1611 currState
->longDesc
.lookupLevel
, currState
->vaddr_tainted
,
1612 currState
->longDesc
.data
,
1613 currState
->aarch64
? "AArch64" : "long-desc.");
1615 if ((currState
->longDesc
.type() == LongDescriptor::Block
) ||
1616 (currState
->longDesc
.type() == LongDescriptor::Page
)) {
1617 DPRINTF(TLBVerbose
, "Analyzing L%d descriptor: %#llx, pxn: %d, "
1618 "xn: %d, ap: %d, af: %d, type: %d\n",
1619 currState
->longDesc
.lookupLevel
,
1620 currState
->longDesc
.data
,
1621 currState
->longDesc
.pxn(),
1622 currState
->longDesc
.xn(),
1623 currState
->longDesc
.ap(),
1624 currState
->longDesc
.af(),
1625 currState
->longDesc
.type());
1627 DPRINTF(TLBVerbose
, "Analyzing L%d descriptor: %#llx, type: %d\n",
1628 currState
->longDesc
.lookupLevel
,
1629 currState
->longDesc
.data
,
1630 currState
->longDesc
.type());
1635 switch (currState
->longDesc
.type()) {
1636 case LongDescriptor::Invalid
:
1637 DPRINTF(TLB
, "L%d descriptor Invalid, causing fault type %d\n",
1638 currState
->longDesc
.lookupLevel
,
1639 ArmFault::TranslationLL
+ currState
->longDesc
.lookupLevel
);
1641 currState
->fault
= generateLongDescFault(ArmFault::TranslationLL
);
1642 if (!currState
->timing
) {
1643 currState
->tc
= NULL
;
1644 currState
->req
= NULL
;
1648 case LongDescriptor::Block
:
1649 case LongDescriptor::Page
:
1651 auto fault_source
= ArmFault::FaultSourceInvalid
;
1652 // Check for address size fault
1653 if (checkAddrSizeFaultAArch64(
1654 mbits(currState
->longDesc
.data
, MaxPhysAddrRange
- 1,
1655 currState
->longDesc
.offsetBits()),
1656 currState
->physAddrRange
)) {
1658 DPRINTF(TLB
, "L%d descriptor causing Address Size Fault\n",
1659 currState
->longDesc
.lookupLevel
);
1660 fault_source
= ArmFault::AddressSizeLL
;
1662 // Check for access fault
1663 } else if (currState
->longDesc
.af() == 0) {
1665 DPRINTF(TLB
, "L%d descriptor causing Access Fault\n",
1666 currState
->longDesc
.lookupLevel
);
1667 fault_source
= ArmFault::AccessFlagLL
;
1670 if (fault_source
!= ArmFault::FaultSourceInvalid
) {
1671 currState
->fault
= generateLongDescFault(fault_source
);
1673 insertTableEntry(currState
->longDesc
, true);
1677 case LongDescriptor::Table
:
1679 // Set hierarchical permission flags
1680 currState
->secureLookup
= currState
->secureLookup
&&
1681 currState
->longDesc
.secureTable();
1682 currState
->rwTable
= currState
->rwTable
&&
1683 (currState
->longDesc
.rwTable() || currState
->hpd
);
1684 currState
->userTable
= currState
->userTable
&&
1685 (currState
->longDesc
.userTable() || currState
->hpd
);
1686 currState
->xnTable
= currState
->xnTable
||
1687 (currState
->longDesc
.xnTable() && !currState
->hpd
);
1688 currState
->pxnTable
= currState
->pxnTable
||
1689 (currState
->longDesc
.pxnTable() && !currState
->hpd
);
1691 // Set up next level lookup
1692 Addr next_desc_addr
= currState
->longDesc
.nextDescAddr(
1695 DPRINTF(TLB
, "L%d descriptor points to L%d descriptor at: %#x (%s)\n",
1696 currState
->longDesc
.lookupLevel
,
1697 currState
->longDesc
.lookupLevel
+ 1,
1699 currState
->secureLookup
? "s" : "ns");
1701 // Check for address size fault
1702 if (currState
->aarch64
&& checkAddrSizeFaultAArch64(
1703 next_desc_addr
, currState
->physAddrRange
)) {
1704 DPRINTF(TLB
, "L%d descriptor causing Address Size Fault\n",
1705 currState
->longDesc
.lookupLevel
);
1707 currState
->fault
= generateLongDescFault(
1708 ArmFault::AddressSizeLL
);
1712 // Trickbox address check
1713 currState
->fault
= testWalk(
1714 next_desc_addr
, sizeof(uint64_t), TlbEntry::DomainType::Client
,
1715 toLookupLevel(currState
->longDesc
.lookupLevel
+1));
1717 if (currState
->fault
) {
1718 if (!currState
->timing
) {
1719 currState
->tc
= NULL
;
1720 currState
->req
= NULL
;
1725 Request::Flags flag
= Request::PT_WALK
;
1726 if (currState
->secureLookup
)
1727 flag
.set(Request::SECURE
);
1729 if (currState
->sctlr
.c
== 0 || currState
->isUncacheable
) {
1730 flag
.set(Request::UNCACHEABLE
);
1733 LookupLevel L
= currState
->longDesc
.lookupLevel
=
1734 (LookupLevel
) (currState
->longDesc
.lookupLevel
+ 1);
1735 Event
*event
= NULL
;
1738 assert(currState
->aarch64
);
1741 event
= LongDescEventByLevel
[L
];
1744 panic("Wrong lookup level in table walk\n");
1749 delayed
= fetchDescriptor(next_desc_addr
, (uint8_t*)&currState
->longDesc
.data
,
1750 sizeof(uint64_t), flag
, -1, event
,
1751 &TableWalker::doLongDescriptor
);
1753 currState
->delayed
= true;
1758 panic("A new type in a 2 bit field?\n");
1763 TableWalker::doL2Descriptor()
1765 if (currState
->fault
!= NoFault
) {
1769 currState
->l2Desc
.data
= htog(currState
->l2Desc
.data
,
1770 byteOrder(currState
->tc
));
1772 DPRINTF(TLB
, "L2 descriptor for %#x is %#x\n",
1773 currState
->vaddr_tainted
, currState
->l2Desc
.data
);
1776 const bool is_atomic
= currState
->req
->isAtomic();
1778 if (currState
->l2Desc
.invalid()) {
1779 DPRINTF(TLB
, "L2 descriptor invalid, causing fault\n");
1780 if (!currState
->timing
) {
1781 currState
->tc
= NULL
;
1782 currState
->req
= NULL
;
1784 if (currState
->isFetch
)
1785 currState
->fault
= std::make_shared
<PrefetchAbort
>(
1786 currState
->vaddr_tainted
,
1787 ArmFault::TranslationLL
+ L2
,
1789 ArmFault::VmsaTran
);
1791 currState
->fault
= std::make_shared
<DataAbort
>(
1792 currState
->vaddr_tainted
, currState
->l1Desc
.domain(),
1793 is_atomic
? false : currState
->isWrite
,
1794 ArmFault::TranslationLL
+ L2
,
1796 ArmFault::VmsaTran
);
1800 if (currState
->sctlr
.afe
&& bits(currState
->l2Desc
.ap(), 0) == 0) {
1801 /** @todo: check sctlr.ha (bit[17]) if Hardware Access Flag is enabled
1802 * if set, do l2.Desc.setAp0() instead of generating AccessFlag0
1804 DPRINTF(TLB
, "Generating access fault at L2, afe: %d, ap: %d\n",
1805 currState
->sctlr
.afe
, currState
->l2Desc
.ap());
1807 currState
->fault
= std::make_shared
<DataAbort
>(
1808 currState
->vaddr_tainted
,
1809 TlbEntry::DomainType::NoAccess
,
1810 is_atomic
? false : currState
->isWrite
,
1811 ArmFault::AccessFlagLL
+ L2
, isStage2
,
1812 ArmFault::VmsaTran
);
1815 insertTableEntry(currState
->l2Desc
, false);
1819 TableWalker::doL1DescriptorWrapper()
1821 currState
= stateQueues
[L1
].front();
1822 currState
->delayed
= false;
1823 // if there's a stage2 translation object we don't need it any more
1824 if (currState
->stage2Tran
) {
1825 delete currState
->stage2Tran
;
1826 currState
->stage2Tran
= NULL
;
1830 DPRINTF(TLBVerbose
, "L1 Desc object host addr: %p\n",&currState
->l1Desc
.data
);
1831 DPRINTF(TLBVerbose
, "L1 Desc object data: %08x\n",currState
->l1Desc
.data
);
1833 DPRINTF(TLBVerbose
, "calling doL1Descriptor for vaddr:%#x\n", currState
->vaddr_tainted
);
1836 stateQueues
[L1
].pop_front();
1837 // Check if fault was generated
1838 if (currState
->fault
!= NoFault
) {
1839 currState
->transState
->finish(currState
->fault
, currState
->req
,
1840 currState
->tc
, currState
->mode
);
1841 statWalksShortTerminatedAtLevel
[0]++;
1844 nextWalk(currState
->tc
);
1846 currState
->req
= NULL
;
1847 currState
->tc
= NULL
;
1848 currState
->delayed
= false;
1851 else if (!currState
->delayed
) {
1852 // delay is not set so there is no L2 to do
1853 // Don't finish the translation if a stage 2 look up is underway
1854 statWalkServiceTime
.sample(curTick() - currState
->startTime
);
1855 DPRINTF(TLBVerbose
, "calling translateTiming again\n");
1856 tlb
->translateTiming(currState
->req
, currState
->tc
,
1857 currState
->transState
, currState
->mode
);
1858 statWalksShortTerminatedAtLevel
[0]++;
1861 nextWalk(currState
->tc
);
1863 currState
->req
= NULL
;
1864 currState
->tc
= NULL
;
1865 currState
->delayed
= false;
1868 // need to do L2 descriptor
1869 stateQueues
[L2
].push_back(currState
);
1875 TableWalker::doL2DescriptorWrapper()
1877 currState
= stateQueues
[L2
].front();
1878 assert(currState
->delayed
);
1879 // if there's a stage2 translation object we don't need it any more
1880 if (currState
->stage2Tran
) {
1881 delete currState
->stage2Tran
;
1882 currState
->stage2Tran
= NULL
;
1885 DPRINTF(TLBVerbose
, "calling doL2Descriptor for vaddr:%#x\n",
1886 currState
->vaddr_tainted
);
1889 // Check if fault was generated
1890 if (currState
->fault
!= NoFault
) {
1891 currState
->transState
->finish(currState
->fault
, currState
->req
,
1892 currState
->tc
, currState
->mode
);
1893 statWalksShortTerminatedAtLevel
[1]++;
1895 statWalkServiceTime
.sample(curTick() - currState
->startTime
);
1896 DPRINTF(TLBVerbose
, "calling translateTiming again\n");
1897 tlb
->translateTiming(currState
->req
, currState
->tc
,
1898 currState
->transState
, currState
->mode
);
1899 statWalksShortTerminatedAtLevel
[1]++;
1903 stateQueues
[L2
].pop_front();
1905 nextWalk(currState
->tc
);
1907 currState
->req
= NULL
;
1908 currState
->tc
= NULL
;
1909 currState
->delayed
= false;
1916 TableWalker::doL0LongDescriptorWrapper()
1918 doLongDescriptorWrapper(L0
);
1922 TableWalker::doL1LongDescriptorWrapper()
1924 doLongDescriptorWrapper(L1
);
1928 TableWalker::doL2LongDescriptorWrapper()
1930 doLongDescriptorWrapper(L2
);
1934 TableWalker::doL3LongDescriptorWrapper()
1936 doLongDescriptorWrapper(L3
);
1940 TableWalker::doLongDescriptorWrapper(LookupLevel curr_lookup_level
)
1942 currState
= stateQueues
[curr_lookup_level
].front();
1943 assert(curr_lookup_level
== currState
->longDesc
.lookupLevel
);
1944 currState
->delayed
= false;
1946 // if there's a stage2 translation object we don't need it any more
1947 if (currState
->stage2Tran
) {
1948 delete currState
->stage2Tran
;
1949 currState
->stage2Tran
= NULL
;
1952 DPRINTF(TLBVerbose
, "calling doLongDescriptor for vaddr:%#x\n",
1953 currState
->vaddr_tainted
);
1956 stateQueues
[curr_lookup_level
].pop_front();
1958 if (currState
->fault
!= NoFault
) {
1959 // A fault was generated
1960 currState
->transState
->finish(currState
->fault
, currState
->req
,
1961 currState
->tc
, currState
->mode
);
1964 nextWalk(currState
->tc
);
1966 currState
->req
= NULL
;
1967 currState
->tc
= NULL
;
1968 currState
->delayed
= false;
1970 } else if (!currState
->delayed
) {
1971 // No additional lookups required
1972 DPRINTF(TLBVerbose
, "calling translateTiming again\n");
1973 statWalkServiceTime
.sample(curTick() - currState
->startTime
);
1974 tlb
->translateTiming(currState
->req
, currState
->tc
,
1975 currState
->transState
, currState
->mode
);
1976 statWalksLongTerminatedAtLevel
[(unsigned) curr_lookup_level
]++;
1979 nextWalk(currState
->tc
);
1981 currState
->req
= NULL
;
1982 currState
->tc
= NULL
;
1983 currState
->delayed
= false;
1986 if (curr_lookup_level
>= MAX_LOOKUP_LEVELS
- 1)
1987 panic("Max. number of lookups already reached in table walk\n");
1988 // Need to perform additional lookups
1989 stateQueues
[currState
->longDesc
.lookupLevel
].push_back(currState
);
1996 TableWalker::nextWalk(ThreadContext
*tc
)
1998 if (pendingQueue
.size())
1999 schedule(doProcessEvent
, clockEdge(Cycles(1)));
2005 TableWalker::fetchDescriptor(Addr descAddr
, uint8_t *data
, int numBytes
,
2006 Request::Flags flags
, int queueIndex
, Event
*event
,
2007 void (TableWalker::*doDescriptor
)())
2009 bool isTiming
= currState
->timing
;
2011 DPRINTF(TLBVerbose
, "Fetching descriptor at address: 0x%x stage2Req: %d\n",
2012 descAddr
, currState
->stage2Req
);
2014 // If this translation has a stage 2 then we know descAddr is an IPA and
2015 // needs to be translated before we can access the page table. Do that
2017 if (currState
->stage2Req
) {
2019 flags
= flags
| TLB::MustBeOne
;
2022 Stage2MMU::Stage2Translation
*tran
= new
2023 Stage2MMU::Stage2Translation(*stage2Mmu
, data
, event
,
2025 currState
->stage2Tran
= tran
;
2026 stage2Mmu
->readDataTimed(currState
->tc
, descAddr
, tran
, numBytes
,
2028 fault
= tran
->fault
;
2030 fault
= stage2Mmu
->readDataUntimed(currState
->tc
,
2031 currState
->vaddr
, descAddr
, data
, numBytes
, flags
,
2032 currState
->functional
);
2035 if (fault
!= NoFault
) {
2036 currState
->fault
= fault
;
2039 if (queueIndex
>= 0) {
2040 DPRINTF(TLBVerbose
, "Adding to walker fifo: queue size before adding: %d\n",
2041 stateQueues
[queueIndex
].size());
2042 stateQueues
[queueIndex
].push_back(currState
);
2046 (this->*doDescriptor
)();
2050 port
->dmaAction(MemCmd::ReadReq
, descAddr
, numBytes
, event
, data
,
2051 currState
->tc
->getCpuPtr()->clockPeriod(),flags
);
2052 if (queueIndex
>= 0) {
2053 DPRINTF(TLBVerbose
, "Adding to walker fifo: queue size before adding: %d\n",
2054 stateQueues
[queueIndex
].size());
2055 stateQueues
[queueIndex
].push_back(currState
);
2058 } else if (!currState
->functional
) {
2059 port
->dmaAction(MemCmd::ReadReq
, descAddr
, numBytes
, NULL
, data
,
2060 currState
->tc
->getCpuPtr()->clockPeriod(), flags
);
2061 (this->*doDescriptor
)();
2063 RequestPtr req
= std::make_shared
<Request
>(
2064 descAddr
, numBytes
, flags
, masterId
);
2066 req
->taskId(ContextSwitchTaskId::DMA
);
2067 PacketPtr pkt
= new Packet(req
, MemCmd::ReadReq
);
2068 pkt
->dataStatic(data
);
2069 port
->sendFunctional(pkt
);
2070 (this->*doDescriptor
)();
2078 TableWalker::insertTableEntry(DescriptorBase
&descriptor
, bool longDescriptor
)
2082 // Create and fill a new page table entry
2084 te
.longDescFormat
= longDescriptor
;
2085 te
.isHyp
= currState
->isHyp
;
2086 te
.asid
= currState
->asid
;
2087 te
.vmid
= currState
->vmid
;
2088 te
.N
= descriptor
.offsetBits();
2089 te
.vpn
= currState
->vaddr
>> te
.N
;
2090 te
.size
= (1<<te
.N
) - 1;
2091 te
.pfn
= descriptor
.pfn();
2092 te
.domain
= descriptor
.domain();
2093 te
.lookupLevel
= descriptor
.lookupLevel
;
2094 te
.ns
= !descriptor
.secure(haveSecurity
, currState
) || isStage2
;
2095 te
.nstid
= !currState
->isSecure
;
2096 te
.xn
= descriptor
.xn();
2097 if (currState
->aarch64
)
2098 te
.el
= currState
->el
;
2102 statPageSizes
[pageSizeNtoStatBin(te
.N
)]++;
2103 statRequestOrigin
[COMPLETED
][currState
->isFetch
]++;
2105 // ASID has no meaning for stage 2 TLB entries, so mark all stage 2 entries
2107 te
.global
= descriptor
.global(currState
) || isStage2
;
2108 if (longDescriptor
) {
2109 LongDescriptor lDescriptor
=
2110 dynamic_cast<LongDescriptor
&>(descriptor
);
2112 te
.xn
|= currState
->xnTable
;
2113 te
.pxn
= currState
->pxnTable
|| lDescriptor
.pxn();
2115 // this is actually the HAP field, but its stored in the same bit
2116 // possitions as the AP field in a stage 1 translation.
2117 te
.hap
= lDescriptor
.ap();
2119 te
.ap
= ((!currState
->rwTable
|| descriptor
.ap() >> 1) << 1) |
2120 (currState
->userTable
&& (descriptor
.ap() & 0x1));
2122 if (currState
->aarch64
)
2123 memAttrsAArch64(currState
->tc
, te
, lDescriptor
);
2125 memAttrsLPAE(currState
->tc
, te
, lDescriptor
);
2127 te
.ap
= descriptor
.ap();
2128 memAttrs(currState
->tc
, te
, currState
->sctlr
, descriptor
.texcb(),
2129 descriptor
.shareable());
2133 DPRINTF(TLB
, descriptor
.dbgHeader().c_str());
2134 DPRINTF(TLB
, " - N:%d pfn:%#x size:%#x global:%d valid:%d\n",
2135 te
.N
, te
.pfn
, te
.size
, te
.global
, te
.valid
);
2136 DPRINTF(TLB
, " - vpn:%#x xn:%d pxn:%d ap:%d domain:%d asid:%d "
2137 "vmid:%d hyp:%d nc:%d ns:%d\n", te
.vpn
, te
.xn
, te
.pxn
,
2138 te
.ap
, static_cast<uint8_t>(te
.domain
), te
.asid
, te
.vmid
, te
.isHyp
,
2139 te
.nonCacheable
, te
.ns
);
2140 DPRINTF(TLB
, " - domain from L%d desc:%d data:%#x\n",
2141 descriptor
.lookupLevel
, static_cast<uint8_t>(descriptor
.domain()),
2142 descriptor
.getRawData());
2144 // Insert the entry into the TLB
2145 tlb
->insert(currState
->vaddr
, te
);
2146 if (!currState
->timing
) {
2147 currState
->tc
= NULL
;
2148 currState
->req
= NULL
;
2152 ArmISA::TableWalker
*
2153 ArmTableWalkerParams::create()
2155 return new ArmISA::TableWalker(this);
2159 TableWalker::toLookupLevel(uint8_t lookup_level_as_int
)
2161 switch (lookup_level_as_int
) {
2169 panic("Invalid lookup level conversion");
2173 /* this method keeps track of the table walker queue's residency, so
2174 * needs to be called whenever requests start and complete. */
2176 TableWalker::pendingChange()
2178 unsigned n
= pendingQueue
.size();
2179 if ((currState
!= NULL
) && (currState
!= pendingQueue
.front())) {
2183 if (n
!= pendingReqs
) {
2184 Tick now
= curTick();
2185 statPendingWalks
.sample(pendingReqs
, now
- pendingChangeTick
);
2187 pendingChangeTick
= now
;
2192 TableWalker::testWalk(Addr pa
, Addr size
, TlbEntry::DomainType domain
,
2193 LookupLevel lookup_level
)
2195 return tlb
->testWalk(pa
, size
, currState
->vaddr
, currState
->isSecure
,
2196 currState
->mode
, domain
, lookup_level
);
2201 TableWalker::pageSizeNtoStatBin(uint8_t N
)
2203 /* for statPageSizes */
2205 case 12: return 0; // 4K
2206 case 14: return 1; // 16K (using 16K granule in v8-64)
2207 case 16: return 2; // 64K
2208 case 20: return 3; // 1M
2209 case 21: return 4; // 2M-LPAE
2210 case 24: return 5; // 16M
2211 case 25: return 6; // 32M (using 16K granule in v8-64)
2212 case 29: return 7; // 512M (using 64K granule in v8-64)
2213 case 30: return 8; // 1G-LPAE
2215 panic("unknown page size");
2221 TableWalker::regStats()
2223 ClockedObject::regStats();
2226 .name(name() + ".walks")
2227 .desc("Table walker walks requested")
2230 statWalksShortDescriptor
2231 .name(name() + ".walksShort")
2232 .desc("Table walker walks initiated with short descriptors")
2233 .flags(Stats::nozero
)
2236 statWalksLongDescriptor
2237 .name(name() + ".walksLong")
2238 .desc("Table walker walks initiated with long descriptors")
2239 .flags(Stats::nozero
)
2242 statWalksShortTerminatedAtLevel
2244 .name(name() + ".walksShortTerminationLevel")
2245 .desc("Level at which table walker walks "
2246 "with short descriptors terminate")
2247 .flags(Stats::nozero
)
2249 statWalksShortTerminatedAtLevel
.subname(0, "Level1");
2250 statWalksShortTerminatedAtLevel
.subname(1, "Level2");
2252 statWalksLongTerminatedAtLevel
2254 .name(name() + ".walksLongTerminationLevel")
2255 .desc("Level at which table walker walks "
2256 "with long descriptors terminate")
2257 .flags(Stats::nozero
)
2259 statWalksLongTerminatedAtLevel
.subname(0, "Level0");
2260 statWalksLongTerminatedAtLevel
.subname(1, "Level1");
2261 statWalksLongTerminatedAtLevel
.subname(2, "Level2");
2262 statWalksLongTerminatedAtLevel
.subname(3, "Level3");
2265 .name(name() + ".walksSquashedBefore")
2266 .desc("Table walks squashed before starting")
2267 .flags(Stats::nozero
)
2271 .name(name() + ".walksSquashedAfter")
2272 .desc("Table walks squashed after completion")
2273 .flags(Stats::nozero
)
2278 .name(name() + ".walkWaitTime")
2279 .desc("Table walker wait (enqueue to first request) latency")
2280 .flags(Stats::pdf
| Stats::nozero
| Stats::nonan
)
2285 .name(name() + ".walkCompletionTime")
2286 .desc("Table walker service (enqueue to completion) latency")
2287 .flags(Stats::pdf
| Stats::nozero
| Stats::nonan
)
2292 .name(name() + ".walksPending")
2293 .desc("Table walker pending requests distribution")
2294 .flags(Stats::pdf
| Stats::dist
| Stats::nozero
| Stats::nonan
)
2297 statPageSizes
// see DDI 0487A D4-1661
2299 .name(name() + ".walkPageSizes")
2300 .desc("Table walker page sizes translated")
2301 .flags(Stats::total
| Stats::pdf
| Stats::dist
| Stats::nozero
)
2303 statPageSizes
.subname(0, "4K");
2304 statPageSizes
.subname(1, "16K");
2305 statPageSizes
.subname(2, "64K");
2306 statPageSizes
.subname(3, "1M");
2307 statPageSizes
.subname(4, "2M");
2308 statPageSizes
.subname(5, "16M");
2309 statPageSizes
.subname(6, "32M");
2310 statPageSizes
.subname(7, "512M");
2311 statPageSizes
.subname(8, "1G");
2314 .init(2,2) // Instruction/Data, requests/completed
2315 .name(name() + ".walkRequestOrigin")
2316 .desc("Table walker requests started/completed, data/inst")
2317 .flags(Stats::total
)
2319 statRequestOrigin
.subname(0,"Requested");
2320 statRequestOrigin
.subname(1,"Completed");
2321 statRequestOrigin
.ysubname(0,"Data");
2322 statRequestOrigin
.ysubname(1,"Inst");