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40 #ifndef __ARCH_ARM_TABLE_WALKER_HH__
41 #define __ARCH_ARM_TABLE_WALKER_HH__
45 #include "arch/arm/miscregs.hh"
46 #include "arch/arm/tlb.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/request.hh"
49 #include "mem/request.hh"
50 #include "params/ArmTableWalker.hh"
51 #include "sim/faults.hh"
52 #include "sim/eventq.hh"
61 class TableWalker : public MemObject
65 /** Type of page table entry ARM DDI 0406B: B3-8*/
73 /** The raw bits of the entry */
76 /** This entry has been modified (access flag set) and needs to be
77 * written back to memory */
80 EntryType type() const
82 return (EntryType)(data & 0x3);
85 /** Is the page a Supersection (16MB)?*/
86 bool supersection() const
88 return bits(data, 18);
91 /** Return the physcal address of the entry, bits in position*/
95 panic("Super sections not implemented\n");
96 return mbits(data, 31,20);
99 /** Return the physical frame, bits shifted right */
103 panic("Super sections not implemented\n");
104 return bits(data, 31,20);
107 /** Is the translation global (no asid used)? */
110 return bits(data, 4);
113 /** Is the translation not allow execution? */
116 return bits(data, 17);
119 /** Three bit access protection flags */
122 return (bits(data, 15) << 2) | bits(data,11,10);
125 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
126 uint8_t domain() const
128 return bits(data,8,5);
131 /** Address of L2 descriptor if it exists */
134 return mbits(data, 31,10);
137 /** Memory region attributes: ARM DDI 0406B: B3-32.
138 * These bits are largly ignored by M5 and only used to
139 * provide the illusion that the memory system cares about
140 * anything but cachable vs. uncachable.
142 uint8_t texcb() const
144 return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2;
147 /** If the section is shareable. See texcb() comment. */
148 bool shareable() const
150 return bits(data, 16);
153 /** Set access flag that this entry has been touched. Mark
154 * the entry as requiring a writeback, in the future.
162 /** This entry needs to be written back to memory */
169 /** Level 2 page table descriptor */
170 struct L2Descriptor {
172 /** The raw bits of the entry. */
175 /** This entry has been modified (access flag set) and needs to be
176 * written back to memory */
179 /** Is the entry invalid */
182 return bits(data, 1,0) == 0;;
185 /** What is the size of the mapping? */
188 return bits(data, 1) == 0;
191 /** Is execution allowed on this mapping? */
194 return large() ? bits(data, 15) : bits(data, 0);
197 /** Is the translation global (no asid used)? */
200 return !bits(data, 11);
203 /** Three bit access protection flags */
206 return bits(data, 5, 4) | (bits(data, 9) << 2);
209 /** Memory region attributes: ARM DDI 0406B: B3-32 */
210 uint8_t texcb() const
213 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) :
214 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2));
217 /** Return the physical frame, bits shifted right */
220 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
223 /** If the section is shareable. See texcb() comment. */
224 bool shareable() const
226 return bits(data, 10);
229 /** Set access flag that this entry has been touched. Mark
230 * the entry as requiring a writeback, in the future.
238 /** This entry needs to be written back to memory */
246 struct WalkerState //: public SimObject
248 /** Thread context that we're doing the walk for */
251 /** Request that is currently being serviced */
254 /** Context ID that we're servicing the request under */
257 /** Translation state for delayed requests */
258 TLB::Translation *transState;
260 /** The fault that we are going to return */
263 /** The virtual address that is being translated */
266 /** Cached copy of the sctlr as it existed when translation began */
269 /** Cached copy of the cpsr as it existed when the translation began */
272 /** Width of the base address held in TTRB0 */
275 /** If the access is a write */
278 /** If the access is not from user mode */
281 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
284 /** If the mode is timing or atomic */
287 /** Save mode for use in delayed response */
293 /** Whether L1/L2 descriptor response is delayed in timing mode */
296 TableWalker *tableWalker;
298 void doL1Descriptor();
299 void doL2Descriptor();
301 std::string name() const {return tableWalker->name();}
305 std::list<WalkerState *> stateQueue;
307 /** Port to issue translation requests from */
310 /** TLB that is initiating these table walks */
313 /** Cached copy of the sctlr as it existed when translation began */
316 WalkerState *currState;
319 typedef ArmTableWalkerParams Params;
320 TableWalker(const Params *p);
321 virtual ~TableWalker();
326 return dynamic_cast<const Params *>(_params);
329 virtual unsigned int drain(Event *de) { panic("write me\n"); }
330 virtual Port *getPort(const std::string &if_name, int idx = -1);
332 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
333 TLB::Translation *_trans, bool timing);
335 void setTlb(TLB *_tlb) { tlb = _tlb; }
336 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
337 uint8_t texcb, bool s);
341 void doL1Descriptor();
342 void doL1DescriptorWrapper();
343 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent;
345 void doL2Descriptor();
346 void doL2DescriptorWrapper();
347 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent;
353 } // namespace ArmISA
355 #endif //__ARCH_ARM_TABLE_WALKER_HH__