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41 #ifndef __ARCH_ARM_TABLE_WALKER_HH__
42 #define __ARCH_ARM_TABLE_WALKER_HH__
46 #include "arch/arm/miscregs.hh"
47 #include "arch/arm/system.hh"
48 #include "arch/arm/tlb.hh"
49 #include "mem/request.hh"
50 #include "params/ArmTableWalker.hh"
51 #include "sim/eventq.hh"
62 class TableWalker : public MemObject
67 class DescriptorBase {
69 /** Current lookup level for this descriptor */
70 LookupLevel lookupLevel;
72 virtual Addr pfn() const = 0;
73 virtual TlbEntry::DomainType domain() const = 0;
74 virtual bool xn() const = 0;
75 virtual uint8_t ap() const = 0;
76 virtual bool global(WalkerState *currState) const = 0;
77 virtual uint8_t offsetBits() const = 0;
78 virtual bool secure(bool have_security, WalkerState *currState) const = 0;
79 virtual std::string dbgHeader() const = 0;
80 virtual uint64_t getRawData() const = 0;
81 virtual uint8_t texcb() const
83 panic("texcb() not implemented for this class\n");
85 virtual bool shareable() const
87 panic("shareable() not implemented for this class\n");
91 class L1Descriptor : public DescriptorBase {
93 /** Type of page table entry ARM DDI 0406B: B3-8*/
101 /** The raw bits of the entry */
104 /** This entry has been modified (access flag set) and needs to be
105 * written back to memory */
109 L1Descriptor() : data(0), _dirty(false)
114 virtual uint64_t getRawData() const
119 virtual std::string dbgHeader() const
121 return "Inserting Section Descriptor into TLB\n";
124 virtual uint8_t offsetBits() const
129 EntryType type() const
131 return (EntryType)(data & 0x3);
134 /** Is the page a Supersection (16MB)?*/
135 bool supersection() const
137 return bits(data, 18);
140 /** Return the physcal address of the entry, bits in position*/
144 panic("Super sections not implemented\n");
145 return mbits(data, 31, 20);
147 /** Return the physcal address of the entry, bits in position*/
148 Addr paddr(Addr va) const
151 panic("Super sections not implemented\n");
152 return mbits(data, 31, 20) | mbits(va, 19, 0);
156 /** Return the physical frame, bits shifted right */
160 panic("Super sections not implemented\n");
161 return bits(data, 31, 20);
164 /** Is the translation global (no asid used)? */
165 bool global(WalkerState *currState) const
167 return !bits(data, 17);
170 /** Is the translation not allow execution? */
173 return bits(data, 4);
176 /** Three bit access protection flags */
179 return (bits(data, 15) << 2) | bits(data, 11, 10);
182 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
183 TlbEntry::DomainType domain() const
185 return static_cast<TlbEntry::DomainType>(bits(data, 8, 5));
188 /** Address of L2 descriptor if it exists */
191 return mbits(data, 31, 10);
194 /** Memory region attributes: ARM DDI 0406B: B3-32.
195 * These bits are largly ignored by M5 and only used to
196 * provide the illusion that the memory system cares about
197 * anything but cachable vs. uncachable.
199 uint8_t texcb() const
201 return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
204 /** If the section is shareable. See texcb() comment. */
205 bool shareable() const
207 return bits(data, 16);
210 /** Set access flag that this entry has been touched. Mark
211 * the entry as requiring a writeback, in the future.
219 /** This entry needs to be written back to memory */
226 * Returns true if this entry targets the secure physical address
229 bool secure(bool have_security, WalkerState *currState) const
232 if (type() == PageTable)
233 return !bits(data, 3);
235 return !bits(data, 19);
241 /** Level 2 page table descriptor */
242 class L2Descriptor : public DescriptorBase {
244 /** The raw bits of the entry. */
246 L1Descriptor *l1Parent;
248 /** This entry has been modified (access flag set) and needs to be
249 * written back to memory */
253 L2Descriptor() : data(0), l1Parent(nullptr), _dirty(false)
258 L2Descriptor(L1Descriptor &parent) : data(0), l1Parent(&parent),
264 virtual uint64_t getRawData() const
269 virtual std::string dbgHeader() const
271 return "Inserting L2 Descriptor into TLB\n";
274 virtual TlbEntry::DomainType domain() const
276 return l1Parent->domain();
279 bool secure(bool have_security, WalkerState *currState) const
281 return l1Parent->secure(have_security, currState);
284 virtual uint8_t offsetBits() const
286 return large() ? 16 : 12;
289 /** Is the entry invalid */
292 return bits(data, 1, 0) == 0;
295 /** What is the size of the mapping? */
298 return bits(data, 1) == 0;
301 /** Is execution allowed on this mapping? */
304 return large() ? bits(data, 15) : bits(data, 0);
307 /** Is the translation global (no asid used)? */
308 bool global(WalkerState *currState) const
310 return !bits(data, 11);
313 /** Three bit access protection flags */
316 return bits(data, 5, 4) | (bits(data, 9) << 2);
319 /** Memory region attributes: ARM DDI 0406B: B3-32 */
320 uint8_t texcb() const
323 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
324 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
327 /** Return the physical frame, bits shifted right */
330 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
333 /** Return complete physical address given a VA */
334 Addr paddr(Addr va) const
337 return mbits(data, 31, 16) | mbits(va, 15, 0);
339 return mbits(data, 31, 12) | mbits(va, 11, 0);
342 /** If the section is shareable. See texcb() comment. */
343 bool shareable() const
345 return bits(data, 10);
348 /** Set access flag that this entry has been touched. Mark
349 * the entry as requiring a writeback, in the future.
357 /** This entry needs to be written back to memory */
365 // Granule sizes for AArch64 long descriptors
373 /** Long-descriptor format (LPAE) */
374 class LongDescriptor : public DescriptorBase {
376 /** Descriptor type */
384 /** The raw bits of the entry */
387 /** This entry has been modified (access flag set) and needs to be
388 * written back to memory */
391 virtual uint64_t getRawData() const
396 virtual std::string dbgHeader() const
398 if (type() == LongDescriptor::Page) {
399 assert(lookupLevel == L3);
400 return "Inserting Page descriptor into TLB\n";
402 assert(lookupLevel < L3);
403 return "Inserting Block descriptor into TLB\n";
408 * Returns true if this entry targets the secure physical address
411 bool secure(bool have_security, WalkerState *currState) const
413 assert(type() == Block || type() == Page);
414 return have_security && (currState->secureLookup && !bits(data, 5));
417 /** True if the current lookup is performed in AArch64 state */
420 /** Width of the granule size in bits */
423 /** Return the descriptor type */
424 EntryType type() const
426 switch (bits(data, 1, 0)) {
428 // In AArch64 blocks are not allowed at L0 for the 4 KB granule
429 // and at L1 for 16/64 KB granules
430 if (grainSize > Grain4KB)
431 return lookupLevel == L2 ? Block : Invalid;
432 return lookupLevel == L0 || lookupLevel == L3 ? Invalid : Block;
434 return lookupLevel == L3 ? Page : Table;
440 /** Return the bit width of the page/block offset */
441 uint8_t offsetBits() const
443 if (type() == Block) {
446 return lookupLevel == L1 ? 30 /* 1 GB */
449 return 25 /* 32 MB */;
451 return 29 /* 512 MB */;
453 panic("Invalid AArch64 VM granule size\n");
455 } else if (type() == Page) {
460 return grainSize; /* enum -> uint okay */
462 panic("Invalid AArch64 VM granule size\n");
465 panic("AArch64 page table entry must be block or page\n");
469 /** Return the physical frame, bits shifted right */
473 return bits(data, 47, offsetBits());
474 return bits(data, 39, offsetBits());
477 /** Return the complete physical address given a VA */
478 Addr paddr(Addr va) const
480 int n = offsetBits();
482 return mbits(data, 47, n) | mbits(va, n - 1, 0);
483 return mbits(data, 39, n) | mbits(va, n - 1, 0);
486 /** Return the physical address of the entry */
490 return mbits(data, 47, offsetBits());
491 return mbits(data, 39, offsetBits());
494 /** Return the address of the next page table */
495 Addr nextTableAddr() const
497 assert(type() == Table);
499 return mbits(data, 47, grainSize);
501 return mbits(data, 39, 12);
504 /** Return the address of the next descriptor */
505 Addr nextDescAddr(Addr va) const
507 assert(type() == Table);
510 int stride = grainSize - 3;
511 int va_lo = stride * (3 - (lookupLevel + 1)) + grainSize;
512 int va_hi = va_lo + stride - 1;
513 pa = nextTableAddr() | (bits(va, va_hi, va_lo) << 3);
515 if (lookupLevel == L1)
516 pa = nextTableAddr() | (bits(va, 29, 21) << 3);
517 else // lookupLevel == L2
518 pa = nextTableAddr() | (bits(va, 20, 12) << 3);
523 /** Is execution allowed on this mapping? */
526 assert(type() == Block || type() == Page);
527 return bits(data, 54);
530 /** Is privileged execution allowed on this mapping? (LPAE only) */
533 assert(type() == Block || type() == Page);
534 return bits(data, 53);
537 /** Contiguous hint bit. */
538 bool contiguousHint() const
540 assert(type() == Block || type() == Page);
541 return bits(data, 52);
544 /** Is the translation global (no asid used)? */
545 bool global(WalkerState *currState) const
547 assert(currState && (type() == Block || type() == Page));
548 if (!currState->aarch64 && (currState->isSecure &&
549 !currState->secureLookup)) {
550 return false; // ARM ARM issue C B3.6.3
551 } else if (currState->aarch64) {
552 if (currState->el == EL2 || currState->el == EL3) {
553 return true; // By default translations are treated as global
554 // in AArch64 EL2 and EL3
555 } else if (currState->isSecure && !currState->secureLookup) {
559 return !bits(data, 11);
562 /** Returns true if the access flag (AF) is set. */
565 assert(type() == Block || type() == Page);
566 return bits(data, 10);
569 /** 2-bit shareability field */
572 assert(type() == Block || type() == Page);
573 return bits(data, 9, 8);
576 /** 2-bit access protection flags */
579 assert(type() == Block || type() == Page);
580 // Long descriptors only support the AP[2:1] scheme
581 return bits(data, 7, 6);
584 /** Read/write access protection flag */
587 assert(type() == Block || type() == Page);
588 return !bits(data, 7);
591 /** User/privileged level access protection flag */
594 assert(type() == Block || type() == Page);
595 return bits(data, 6);
598 /** Return the AP bits as compatible with the AP[2:0] format. Utility
599 * function used to simplify the code in the TLB for performing
600 * permission checks. */
601 static uint8_t ap(bool rw, bool user)
603 return ((!rw) << 2) | (user << 1);
606 TlbEntry::DomainType domain() const
608 // Long-desc. format only supports Client domain
609 assert(type() == Block || type() == Page);
610 return TlbEntry::DomainType::Client;
613 /** Attribute index */
614 uint8_t attrIndx() const
616 assert(type() == Block || type() == Page);
617 return bits(data, 4, 2);
620 /** Memory attributes, only used by stage 2 translations */
621 uint8_t memAttr() const
623 assert(type() == Block || type() == Page);
624 return bits(data, 5, 2);
627 /** Set access flag that this entry has been touched. Mark the entry as
628 * requiring a writeback, in the future. */
635 /** This entry needs to be written back to memory */
641 /** Whether the subsequent levels of lookup are secure */
642 bool secureTable() const
644 assert(type() == Table);
645 return !bits(data, 63);
648 /** Two bit access protection flags for subsequent levels of lookup */
649 uint8_t apTable() const
651 assert(type() == Table);
652 return bits(data, 62, 61);
655 /** R/W protection flag for subsequent levels of lookup */
656 uint8_t rwTable() const
658 assert(type() == Table);
659 return !bits(data, 62);
662 /** User/privileged mode protection flag for subsequent levels of
664 uint8_t userTable() const
666 assert(type() == Table);
667 return !bits(data, 61);
670 /** Is execution allowed on subsequent lookup levels? */
673 assert(type() == Table);
674 return bits(data, 60);
677 /** Is privileged execution allowed on subsequent lookup levels? */
678 bool pxnTable() const
680 assert(type() == Table);
681 return bits(data, 59);
688 /** Thread context that we're doing the walk for */
691 /** If the access is performed in AArch64 state */
694 /** Current exception level */
697 /** Current physical address range in bits */
700 /** Request that is currently being serviced */
703 /** ASID that we're servicing the request under */
708 /** Translation state for delayed requests */
709 TLB::Translation *transState;
711 /** The fault that we are going to return */
714 /** The virtual address that is being translated with tagging removed.*/
717 /** The virtual address that is being translated */
720 /** Cached copy of the sctlr as it existed when translation began */
723 /** Cached copy of the scr as it existed when translation began */
726 /** Cached copy of the cpsr as it existed when translation began */
729 /** Cached copy of ttbcr/tcr as it existed when translation began */
731 TTBCR ttbcr; // AArch32 translations
732 TCR tcr; // AArch64 translations
735 /** Cached copy of the htcr as it existed when translation began. */
738 /** Cached copy of the htcr as it existed when translation began. */
741 /** Cached copy of the vtcr as it existed when translation began. */
744 /** If the access is a write */
747 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
750 /** If the access comes from the secure state. */
753 /** Helper variables used to implement hierarchical access permissions
754 * when the long-desc. format is used (LPAE only) */
761 /** Flag indicating if a second stage of lookup is required */
764 /** A pointer to the stage 2 translation that's in progress */
765 TLB::Translation *stage2Tran;
767 /** If the mode is timing or atomic */
770 /** If the atomic mode should be functional */
773 /** Save mode for use in delayed response */
776 /** The translation type that has been requested */
777 TLB::ArmTranslationType tranType;
779 /** Short-format descriptors */
783 /** Long-format descriptor (LPAE and AArch64) */
784 LongDescriptor longDesc;
786 /** Whether the response is delayed in timing mode due to additional
790 TableWalker *tableWalker;
792 /** Timestamp for calculating elapsed time in service (for stats) */
795 /** Page entries walked during service (for stats) */
798 void doL1Descriptor();
799 void doL2Descriptor();
801 void doLongDescriptor();
805 std::string name() const { return tableWalker->name(); }
810 /** Queues of requests for all the different lookup levels */
811 std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS];
813 /** Queue of requests that have passed are waiting because the walker is
815 std::list<WalkerState *> pendingQueue;
817 /** The MMU to forward second stage look upts to */
818 Stage2MMU *stage2Mmu;
820 /** Port shared by the two table walkers. */
823 /** Master id assigned by the MMU. */
826 /** Indicates whether this table walker is part of the stage 2 mmu */
829 /** TLB that is initiating these table walks */
832 /** Cached copy of the sctlr as it existed when translation began */
835 WalkerState *currState;
837 /** If a timing translation is currently in progress */
840 /** The number of walks belonging to squashed instructions that can be
841 * removed from the pendingQueue per cycle. */
842 unsigned numSquashable;
844 /** Cached copies of system-level properties */
847 bool _haveVirtualization;
848 uint8_t physAddrRange;
849 bool _haveLargeAsid64;
852 Stats::Scalar statWalks;
853 Stats::Scalar statWalksShortDescriptor;
854 Stats::Scalar statWalksLongDescriptor;
855 Stats::Vector statWalksShortTerminatedAtLevel;
856 Stats::Vector statWalksLongTerminatedAtLevel;
857 Stats::Scalar statSquashedBefore;
858 Stats::Scalar statSquashedAfter;
859 Stats::Histogram statWalkWaitTime;
860 Stats::Histogram statWalkServiceTime;
861 Stats::Histogram statPendingWalks; // essentially "L" of queueing theory
862 Stats::Vector statPageSizes;
863 Stats::Vector2d statRequestOrigin;
865 mutable unsigned pendingReqs;
866 mutable Tick pendingChangeTick;
868 static const unsigned REQUESTED = 0;
869 static const unsigned COMPLETED = 1;
872 typedef ArmTableWalkerParams Params;
873 TableWalker(const Params *p);
874 virtual ~TableWalker();
879 return dynamic_cast<const Params *>(_params);
882 void init() override;
884 bool haveLPAE() const { return _haveLPAE; }
885 bool haveVirtualization() const { return _haveVirtualization; }
886 bool haveLargeAsid64() const { return _haveLargeAsid64; }
887 /** Checks if all state is cleared and if so, completes drain */
888 void completeDrain();
889 DrainState drain() override;
890 void drainResume() override;
892 BaseMasterPort& getMasterPort(const std::string &if_name,
893 PortID idx = InvalidPortID) override;
895 void regStats() override;
897 Fault walk(RequestPtr req, ThreadContext *tc, uint16_t asid, uint8_t _vmid,
898 bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
899 bool timing, bool functional, bool secure,
900 TLB::ArmTranslationType tranType, bool _stage2Req);
902 void setTlb(TLB *_tlb) { tlb = _tlb; }
903 TLB* getTlb() { return tlb; }
904 void setMMU(Stage2MMU *m, MasterID master_id);
905 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
906 uint8_t texcb, bool s);
907 void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
908 LongDescriptor &lDescriptor);
909 void memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
910 LongDescriptor &lDescriptor);
912 static LookupLevel toLookupLevel(uint8_t lookup_level_as_int);
916 void doL1Descriptor();
917 void doL1DescriptorWrapper();
918 EventFunctionWrapper doL1DescEvent;
920 void doL2Descriptor();
921 void doL2DescriptorWrapper();
922 EventFunctionWrapper doL2DescEvent;
924 void doLongDescriptor();
926 void doL0LongDescriptorWrapper();
927 EventFunctionWrapper doL0LongDescEvent;
928 void doL1LongDescriptorWrapper();
929 EventFunctionWrapper doL1LongDescEvent;
930 void doL2LongDescriptorWrapper();
931 EventFunctionWrapper doL2LongDescEvent;
932 void doL3LongDescriptorWrapper();
933 EventFunctionWrapper doL3LongDescEvent;
935 void doLongDescriptorWrapper(LookupLevel curr_lookup_level);
936 Event* LongDescEventByLevel[4];
938 bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
939 Request::Flags flags, int queueIndex, Event *event,
940 void (TableWalker::*doDescriptor)());
942 void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor);
945 Fault processWalkLPAE();
946 static unsigned adjustTableSizeAArch64(unsigned tsz);
947 /// Returns true if the address exceeds the range permitted by the
948 /// system-wide setting or by the TCR_ELx IPS/PS setting
949 static bool checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange);
950 Fault processWalkAArch64();
951 void processWalkWrapper();
952 EventFunctionWrapper doProcessEvent;
954 void nextWalk(ThreadContext *tc);
956 void pendingChange();
958 static uint8_t pageSizeNtoStatBin(uint8_t N);
960 Fault testWalk(Addr pa, Addr size, TlbEntry::DomainType domain,
961 LookupLevel lookup_level);
964 } // namespace ArmISA
966 #endif //__ARCH_ARM_TABLE_WALKER_HH__