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40 #ifndef __ARCH_ARM_TABLE_WALKER_HH__
41 #define __ARCH_ARM_TABLE_WALKER_HH__
45 #include "arch/arm/miscregs.hh"
46 #include "arch/arm/tlb.hh"
47 #include "dev/io_device.hh"
48 #include "mem/mem_object.hh"
49 #include "mem/request.hh"
50 #include "params/ArmTableWalker.hh"
51 #include "sim/eventq.hh"
52 #include "sim/fault_fwd.hh"
61 class TableWalker : public MemObject
65 /** Type of page table entry ARM DDI 0406B: B3-8*/
73 /** The raw bits of the entry */
76 /** This entry has been modified (access flag set) and needs to be
77 * written back to memory */
80 EntryType type() const
82 return (EntryType)(data & 0x3);
85 /** Is the page a Supersection (16MB)?*/
86 bool supersection() const
88 return bits(data, 18);
91 /** Return the physcal address of the entry, bits in position*/
95 panic("Super sections not implemented\n");
96 return mbits(data, 31, 20);
98 /** Return the physcal address of the entry, bits in position*/
99 Addr paddr(Addr va) const
102 panic("Super sections not implemented\n");
103 return mbits(data, 31, 20) | mbits(va, 19, 0);
107 /** Return the physical frame, bits shifted right */
111 panic("Super sections not implemented\n");
112 return bits(data, 31, 20);
115 /** Is the translation global (no asid used)? */
118 return bits(data, 17);
121 /** Is the translation not allow execution? */
124 return bits(data, 4);
127 /** Three bit access protection flags */
130 return (bits(data, 15) << 2) | bits(data, 11, 10);
133 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
134 uint8_t domain() const
136 return bits(data, 8, 5);
139 /** Address of L2 descriptor if it exists */
142 return mbits(data, 31, 10);
145 /** Memory region attributes: ARM DDI 0406B: B3-32.
146 * These bits are largly ignored by M5 and only used to
147 * provide the illusion that the memory system cares about
148 * anything but cachable vs. uncachable.
150 uint8_t texcb() const
152 return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
155 /** If the section is shareable. See texcb() comment. */
156 bool shareable() const
158 return bits(data, 16);
161 /** Set access flag that this entry has been touched. Mark
162 * the entry as requiring a writeback, in the future.
170 /** This entry needs to be written back to memory */
177 /** Level 2 page table descriptor */
178 struct L2Descriptor {
180 /** The raw bits of the entry. */
183 /** This entry has been modified (access flag set) and needs to be
184 * written back to memory */
187 /** Is the entry invalid */
190 return bits(data, 1, 0) == 0;
193 /** What is the size of the mapping? */
196 return bits(data, 1) == 0;
199 /** Is execution allowed on this mapping? */
202 return large() ? bits(data, 15) : bits(data, 0);
205 /** Is the translation global (no asid used)? */
208 return !bits(data, 11);
211 /** Three bit access protection flags */
214 return bits(data, 5, 4) | (bits(data, 9) << 2);
217 /** Memory region attributes: ARM DDI 0406B: B3-32 */
218 uint8_t texcb() const
221 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
222 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
225 /** Return the physical frame, bits shifted right */
228 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
231 /** Return complete physical address given a VA */
232 Addr paddr(Addr va) const
235 return mbits(data, 31, 16) | mbits(va, 15, 0);
237 return mbits(data, 31, 12) | mbits(va, 11, 0);
240 /** If the section is shareable. See texcb() comment. */
241 bool shareable() const
243 return bits(data, 10);
246 /** Set access flag that this entry has been touched. Mark
247 * the entry as requiring a writeback, in the future.
255 /** This entry needs to be written back to memory */
263 struct WalkerState //: public SimObject
265 /** Thread context that we're doing the walk for */
268 /** Request that is currently being serviced */
271 /** Context ID that we're servicing the request under */
274 /** Translation state for delayed requests */
275 TLB::Translation *transState;
277 /** The fault that we are going to return */
280 /** The virtual address that is being translated */
283 /** Cached copy of the sctlr as it existed when translation began */
286 /** Width of the base address held in TTRB0 */
289 /** If the access is a write */
292 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
295 /** If the mode is timing or atomic */
298 /** If the atomic mode should be functional */
301 /** Save mode for use in delayed response */
307 /** Whether L1/L2 descriptor response is delayed in timing mode */
310 TableWalker *tableWalker;
312 void doL1Descriptor();
313 void doL2Descriptor();
315 std::string name() const {return tableWalker->name();}
319 /** Queue of requests that need processing first level translation */
320 std::list<WalkerState *> stateQueueL1;
322 /** Queue of requests that have passed first level translation and
323 * require an additional level. */
324 std::list<WalkerState *> stateQueueL2;
326 /** Queue of requests that have passed are waiting because the walker is
328 std::list<WalkerState *> pendingQueue;;
331 /** Port to issue translation requests from */
334 /** TLB that is initiating these table walks */
337 /** Cached copy of the sctlr as it existed when translation began */
340 WalkerState *currState;
342 /** If a timing translation is currently in progress */
345 /** Request id for requests generated by this walker */
349 typedef ArmTableWalkerParams Params;
350 TableWalker(const Params *p);
351 virtual ~TableWalker();
356 return dynamic_cast<const Params *>(_params);
359 virtual unsigned int drain(Event *de);
360 virtual void resume();
361 virtual Port *getPort(const std::string &if_name, int idx = -1);
363 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
364 TLB::Translation *_trans, bool timing, bool functional = false);
366 void setTlb(TLB *_tlb) { tlb = _tlb; }
367 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
368 uint8_t texcb, bool s);
372 void doL1Descriptor();
373 void doL1DescriptorWrapper();
374 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent;
376 void doL2Descriptor();
377 void doL2DescriptorWrapper();
378 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent;
381 void processWalkWrapper();
382 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent;
384 void nextWalk(ThreadContext *tc);
388 } // namespace ArmISA
390 #endif //__ARCH_ARM_TABLE_WALKER_HH__