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40 #ifndef __ARCH_ARM_TABLE_WALKER_HH__
41 #define __ARCH_ARM_TABLE_WALKER_HH__
43 #include "arch/arm/miscregs.hh"
44 #include "arch/arm/tlb.hh"
45 #include "mem/mem_object.hh"
46 #include "mem/request.hh"
47 #include "mem/request.hh"
48 #include "params/ArmTableWalker.hh"
49 #include "sim/faults.hh"
50 #include "sim/eventq.hh"
59 class TableWalker : public MemObject
63 /** Type of page table entry ARM DDI 0406B: B3-8*/
73 EntryType type() const
75 return (EntryType)(data & 0x3);
78 /** Is the page a Supersection (16MB)?*/
79 bool supersection() const
81 return bits(data, 18);
84 /** Return the physcal address of the entry, bits in position*/
88 panic("Super sections not implemented\n");
89 return mbits(data, 31,20);
92 /** Return the physical frame, bits shifted right */
96 panic("Super sections not implemented\n");
97 return bits(data, 31,20);
100 /** Is the translation global (no asid used)? */
103 return bits(data, 17);
106 /** Is the translation not allow execution? */
109 return bits(data, 17);
112 /** Three bit access protection flags */
115 return (bits(data, 15) << 2) | bits(data,11,10);
118 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
119 uint8_t domain() const
121 return bits(data,8,5);
124 /** Address of L2 descriptor if it exists */
127 return mbits(data, 31,10);
130 /** Memory region attributes: ARM DDI 0406B: B3-32 */
131 uint8_t texcb() const
133 return bits(data, 2) | bits(data,3) << 1 | bits(data, 12, 14) << 2;
138 /** Level 2 page table descriptor */
139 struct L2Descriptor {
143 /** Is the entry invalid */
146 return bits(data, 1,0) == 0;;
149 /** What is the size of the mapping? */
152 return bits(data, 1) == 0;
155 /** Is execution allowed on this mapping? */
158 return large() ? bits(data, 15) : bits(data, 0);
161 /** Is the translation global (no asid used)? */
164 return !bits(data, 11);
167 /** Three bit access protection flags */
170 return bits(data, 5, 4) | (bits(data, 9) << 2);
173 /** Memory region attributes: ARM DDI 0406B: B3-32 */
174 uint8_t texcb() const
177 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 12, 14) << 2)) :
178 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 6, 8) << 2));
181 /** Return the physical frame, bits shifted right */
184 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
189 /** Port to issue translation requests from */
192 /** TLB that is initiating these table walks */
195 /** Thread context that we're doing the walk for */
198 /** Request that is currently being serviced */
201 /** Context ID that we're servicing the request under */
204 /** Translation state for delayed requests */
205 TLB::Translation *transState;
207 /** The fault that we are going to return */
210 /** The virtual address that is being translated */
213 /** Cached copy of the sctlr as it existed when translation began */
216 /** Cached copy of the cpsr as it existed when the translation began */
219 /** Width of the base address held in TTRB0 */
222 /** If the access is a write */
225 /** If the access is not from user mode */
228 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
231 /** If the mode is timing or atomic */
238 typedef ArmTableWalkerParams Params;
239 TableWalker(const Params *p);
240 virtual ~TableWalker();
245 return dynamic_cast<const Params *>(_params);
248 virtual unsigned int drain(Event *de) { panic("write me\n"); }
249 virtual Port *getPort(const std::string &if_name, int idx = -1);
251 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
252 TLB::Translation *_trans, bool timing);
254 void setTlb(TLB *_tlb) { tlb = _tlb; }
257 void memAttrs(TlbEntry &te, uint8_t texcb);
259 void doL1Descriptor();
260 EventWrapper<TableWalker, &TableWalker::doL1Descriptor> doL1DescEvent;
262 void doL2Descriptor();
263 EventWrapper<TableWalker, &TableWalker::doL2Descriptor> doL2DescEvent;
269 } // namespace ArmISA
271 #endif //__ARCH_ARM_TABLE_WALKER_HH__