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41 #ifndef __ARCH_ARM_TABLE_WALKER_HH__
42 #define __ARCH_ARM_TABLE_WALKER_HH__
46 #include "arch/arm/faults.hh"
47 #include "arch/arm/miscregs.hh"
48 #include "arch/arm/system.hh"
49 #include "arch/arm/tlb.hh"
50 #include "mem/request.hh"
51 #include "params/ArmTableWalker.hh"
52 #include "sim/clocked_object.hh"
53 #include "sim/eventq.hh"
64 class TableWalker : public ClockedObject
69 class DescriptorBase {
71 DescriptorBase() : lookupLevel(L0) {}
73 /** Current lookup level for this descriptor */
74 LookupLevel lookupLevel;
76 virtual Addr pfn() const = 0;
77 virtual TlbEntry::DomainType domain() const = 0;
78 virtual bool xn() const = 0;
79 virtual uint8_t ap() const = 0;
80 virtual bool global(WalkerState *currState) const = 0;
81 virtual uint8_t offsetBits() const = 0;
82 virtual bool secure(bool have_security, WalkerState *currState) const = 0;
83 virtual std::string dbgHeader() const = 0;
84 virtual uint64_t getRawData() const = 0;
85 virtual uint8_t texcb() const
87 panic("texcb() not implemented for this class\n");
89 virtual bool shareable() const
91 panic("shareable() not implemented for this class\n");
95 class L1Descriptor : public DescriptorBase {
97 /** Type of page table entry ARM DDI 0406B: B3-8*/
105 /** The raw bits of the entry */
108 /** This entry has been modified (access flag set) and needs to be
109 * written back to memory */
113 L1Descriptor() : data(0), _dirty(false)
118 virtual uint64_t getRawData() const
123 virtual std::string dbgHeader() const
125 return "Inserting Section Descriptor into TLB\n";
128 virtual uint8_t offsetBits() const
133 EntryType type() const
135 return (EntryType)(data & 0x3);
138 /** Is the page a Supersection (16MB)?*/
139 bool supersection() const
141 return bits(data, 18);
144 /** Return the physcal address of the entry, bits in position*/
148 panic("Super sections not implemented\n");
149 return mbits(data, 31, 20);
151 /** Return the physcal address of the entry, bits in position*/
152 Addr paddr(Addr va) const
155 panic("Super sections not implemented\n");
156 return mbits(data, 31, 20) | mbits(va, 19, 0);
160 /** Return the physical frame, bits shifted right */
164 panic("Super sections not implemented\n");
165 return bits(data, 31, 20);
168 /** Is the translation global (no asid used)? */
169 bool global(WalkerState *currState) const
171 return !bits(data, 17);
174 /** Is the translation not allow execution? */
177 return bits(data, 4);
180 /** Three bit access protection flags */
183 return (bits(data, 15) << 2) | bits(data, 11, 10);
186 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
187 TlbEntry::DomainType domain() const
189 return static_cast<TlbEntry::DomainType>(bits(data, 8, 5));
192 /** Address of L2 descriptor if it exists */
195 return mbits(data, 31, 10);
198 /** Memory region attributes: ARM DDI 0406B: B3-32.
199 * These bits are largly ignored by M5 and only used to
200 * provide the illusion that the memory system cares about
201 * anything but cachable vs. uncachable.
203 uint8_t texcb() const
205 return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
208 /** If the section is shareable. See texcb() comment. */
209 bool shareable() const
211 return bits(data, 16);
214 /** Set access flag that this entry has been touched. Mark
215 * the entry as requiring a writeback, in the future.
223 /** This entry needs to be written back to memory */
230 * Returns true if this entry targets the secure physical address
233 bool secure(bool have_security, WalkerState *currState) const
236 if (type() == PageTable)
237 return !bits(data, 3);
239 return !bits(data, 19);
245 /** Level 2 page table descriptor */
246 class L2Descriptor : public DescriptorBase {
248 /** The raw bits of the entry. */
250 L1Descriptor *l1Parent;
252 /** This entry has been modified (access flag set) and needs to be
253 * written back to memory */
257 L2Descriptor() : data(0), l1Parent(nullptr), _dirty(false)
262 L2Descriptor(L1Descriptor &parent) : data(0), l1Parent(&parent),
268 virtual uint64_t getRawData() const
273 virtual std::string dbgHeader() const
275 return "Inserting L2 Descriptor into TLB\n";
278 virtual TlbEntry::DomainType domain() const
280 return l1Parent->domain();
283 bool secure(bool have_security, WalkerState *currState) const
285 return l1Parent->secure(have_security, currState);
288 virtual uint8_t offsetBits() const
290 return large() ? 16 : 12;
293 /** Is the entry invalid */
296 return bits(data, 1, 0) == 0;
299 /** What is the size of the mapping? */
302 return bits(data, 1) == 0;
305 /** Is execution allowed on this mapping? */
308 return large() ? bits(data, 15) : bits(data, 0);
311 /** Is the translation global (no asid used)? */
312 bool global(WalkerState *currState) const
314 return !bits(data, 11);
317 /** Three bit access protection flags */
320 return bits(data, 5, 4) | (bits(data, 9) << 2);
323 /** Memory region attributes: ARM DDI 0406B: B3-32 */
324 uint8_t texcb() const
327 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
328 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
331 /** Return the physical frame, bits shifted right */
334 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
337 /** Return complete physical address given a VA */
338 Addr paddr(Addr va) const
341 return mbits(data, 31, 16) | mbits(va, 15, 0);
343 return mbits(data, 31, 12) | mbits(va, 11, 0);
346 /** If the section is shareable. See texcb() comment. */
347 bool shareable() const
349 return bits(data, 10);
352 /** Set access flag that this entry has been touched. Mark
353 * the entry as requiring a writeback, in the future.
361 /** This entry needs to be written back to memory */
369 // Granule sizes for AArch64 long descriptors
377 /** Long-descriptor format (LPAE) */
378 class LongDescriptor : public DescriptorBase {
380 /** Descriptor type */
388 LongDescriptor() : data(0), _dirty(false) {}
390 /** The raw bits of the entry */
393 /** This entry has been modified (access flag set) and needs to be
394 * written back to memory */
397 virtual uint64_t getRawData() const
402 virtual std::string dbgHeader() const
404 if (type() == LongDescriptor::Page) {
405 assert(lookupLevel == L3);
406 return "Inserting Page descriptor into TLB\n";
408 assert(lookupLevel < L3);
409 return "Inserting Block descriptor into TLB\n";
414 * Returns true if this entry targets the secure physical address
417 bool secure(bool have_security, WalkerState *currState) const
419 assert(type() == Block || type() == Page);
420 return have_security && (currState->secureLookup && !bits(data, 5));
423 /** True if the current lookup is performed in AArch64 state */
426 /** Width of the granule size in bits */
429 /** Return the descriptor type */
430 EntryType type() const
432 switch (bits(data, 1, 0)) {
434 // In AArch64 blocks are not allowed at L0 for the 4 KB granule
435 // and at L1 for 16/64 KB granules
436 if (grainSize > Grain4KB)
437 return lookupLevel == L2 ? Block : Invalid;
438 return lookupLevel == L0 || lookupLevel == L3 ? Invalid : Block;
440 return lookupLevel == L3 ? Page : Table;
446 /** Return the bit width of the page/block offset */
447 uint8_t offsetBits() const
449 if (type() == Block) {
452 return lookupLevel == L1 ? 30 /* 1 GB */
455 return 25 /* 32 MB */;
457 return 29 /* 512 MB */;
459 panic("Invalid AArch64 VM granule size\n");
461 } else if (type() == Page) {
466 return grainSize; /* enum -> uint okay */
468 panic("Invalid AArch64 VM granule size\n");
471 panic("AArch64 page table entry must be block or page\n");
475 /** Return the physical frame, bits shifted right */
479 return bits(data, 47, offsetBits());
480 return bits(data, 39, offsetBits());
483 /** Return the complete physical address given a VA */
484 Addr paddr(Addr va) const
486 int n = offsetBits();
488 return mbits(data, 47, n) | mbits(va, n - 1, 0);
489 return mbits(data, 39, n) | mbits(va, n - 1, 0);
492 /** Return the physical address of the entry */
496 return mbits(data, 47, offsetBits());
497 return mbits(data, 39, offsetBits());
500 /** Return the address of the next page table */
501 Addr nextTableAddr() const
503 assert(type() == Table);
505 return mbits(data, 47, grainSize);
507 return mbits(data, 39, 12);
510 /** Return the address of the next descriptor */
511 Addr nextDescAddr(Addr va) const
513 assert(type() == Table);
516 int stride = grainSize - 3;
517 int va_lo = stride * (3 - (lookupLevel + 1)) + grainSize;
518 int va_hi = va_lo + stride - 1;
519 pa = nextTableAddr() | (bits(va, va_hi, va_lo) << 3);
521 if (lookupLevel == L1)
522 pa = nextTableAddr() | (bits(va, 29, 21) << 3);
523 else // lookupLevel == L2
524 pa = nextTableAddr() | (bits(va, 20, 12) << 3);
529 /** Is execution allowed on this mapping? */
532 assert(type() == Block || type() == Page);
533 return bits(data, 54);
536 /** Is privileged execution allowed on this mapping? (LPAE only) */
539 assert(type() == Block || type() == Page);
540 return bits(data, 53);
543 /** Contiguous hint bit. */
544 bool contiguousHint() const
546 assert(type() == Block || type() == Page);
547 return bits(data, 52);
550 /** Is the translation global (no asid used)? */
551 bool global(WalkerState *currState) const
553 assert(currState && (type() == Block || type() == Page));
554 if (!currState->aarch64 && (currState->isSecure &&
555 !currState->secureLookup)) {
556 return false; // ARM ARM issue C B3.6.3
557 } else if (currState->aarch64) {
558 if (currState->el == EL2 || currState->el == EL3) {
559 return true; // By default translations are treated as global
560 // in AArch64 EL2 and EL3
561 } else if (currState->isSecure && !currState->secureLookup) {
565 return !bits(data, 11);
568 /** Returns true if the access flag (AF) is set. */
571 assert(type() == Block || type() == Page);
572 return bits(data, 10);
575 /** 2-bit shareability field */
578 assert(type() == Block || type() == Page);
579 return bits(data, 9, 8);
582 /** 2-bit access protection flags */
585 assert(type() == Block || type() == Page);
586 // Long descriptors only support the AP[2:1] scheme
587 return bits(data, 7, 6);
590 /** Read/write access protection flag */
593 assert(type() == Block || type() == Page);
594 return !bits(data, 7);
597 /** User/privileged level access protection flag */
600 assert(type() == Block || type() == Page);
601 return bits(data, 6);
604 /** Return the AP bits as compatible with the AP[2:0] format. Utility
605 * function used to simplify the code in the TLB for performing
606 * permission checks. */
607 static uint8_t ap(bool rw, bool user)
609 return ((!rw) << 2) | (user << 1);
612 TlbEntry::DomainType domain() const
614 // Long-desc. format only supports Client domain
615 assert(type() == Block || type() == Page);
616 return TlbEntry::DomainType::Client;
619 /** Attribute index */
620 uint8_t attrIndx() const
622 assert(type() == Block || type() == Page);
623 return bits(data, 4, 2);
626 /** Memory attributes, only used by stage 2 translations */
627 uint8_t memAttr() const
629 assert(type() == Block || type() == Page);
630 return bits(data, 5, 2);
633 /** Set access flag that this entry has been touched. Mark the entry as
634 * requiring a writeback, in the future. */
641 /** This entry needs to be written back to memory */
647 /** Whether the subsequent levels of lookup are secure */
648 bool secureTable() const
650 assert(type() == Table);
651 return !bits(data, 63);
654 /** Two bit access protection flags for subsequent levels of lookup */
655 uint8_t apTable() const
657 assert(type() == Table);
658 return bits(data, 62, 61);
661 /** R/W protection flag for subsequent levels of lookup */
662 uint8_t rwTable() const
664 assert(type() == Table);
665 return !bits(data, 62);
668 /** User/privileged mode protection flag for subsequent levels of
670 uint8_t userTable() const
672 assert(type() == Table);
673 return !bits(data, 61);
676 /** Is execution allowed on subsequent lookup levels? */
679 assert(type() == Table);
680 return bits(data, 60);
683 /** Is privileged execution allowed on subsequent lookup levels? */
684 bool pxnTable() const
686 assert(type() == Table);
687 return bits(data, 59);
694 /** Thread context that we're doing the walk for */
697 /** If the access is performed in AArch64 state */
700 /** Current exception level */
703 /** Current physical address range in bits */
706 /** Request that is currently being serviced */
709 /** ASID that we're servicing the request under */
714 /** Translation state for delayed requests */
715 TLB::Translation *transState;
717 /** The fault that we are going to return */
720 /** The virtual address that is being translated with tagging removed.*/
723 /** The virtual address that is being translated */
726 /** Cached copy of the sctlr as it existed when translation began */
729 /** Cached copy of the scr as it existed when translation began */
732 /** Cached copy of the cpsr as it existed when translation began */
735 /** Cached copy of ttbcr/tcr as it existed when translation began */
737 TTBCR ttbcr; // AArch32 translations
738 TCR tcr; // AArch64 translations
741 /** Cached copy of the htcr as it existed when translation began. */
744 /** Cached copy of the htcr as it existed when translation began. */
747 /** Cached copy of the vtcr as it existed when translation began. */
750 /** If the access is a write */
753 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
756 /** If the access comes from the secure state. */
759 /** True if table walks are uncacheable (for table descriptors) */
762 /** Helper variables used to implement hierarchical access permissions
763 * when the long-desc. format is used (LPAE only) */
770 /** Hierarchical access permission disable */
773 /** Flag indicating if a second stage of lookup is required */
776 /** A pointer to the stage 2 translation that's in progress */
777 TLB::Translation *stage2Tran;
779 /** If the mode is timing or atomic */
782 /** If the atomic mode should be functional */
785 /** Save mode for use in delayed response */
788 /** The translation type that has been requested */
789 TLB::ArmTranslationType tranType;
791 /** Short-format descriptors */
795 /** Long-format descriptor (LPAE and AArch64) */
796 LongDescriptor longDesc;
798 /** Whether the response is delayed in timing mode due to additional
802 TableWalker *tableWalker;
804 /** Timestamp for calculating elapsed time in service (for stats) */
807 /** Page entries walked during service (for stats) */
810 void doL1Descriptor();
811 void doL2Descriptor();
813 void doLongDescriptor();
817 std::string name() const { return tableWalker->name(); }
822 /** Queues of requests for all the different lookup levels */
823 std::list<WalkerState *> stateQueues[MAX_LOOKUP_LEVELS];
825 /** Queue of requests that have passed are waiting because the walker is
827 std::list<WalkerState *> pendingQueue;
829 /** The MMU to forward second stage look upts to */
830 Stage2MMU *stage2Mmu;
832 /** Port shared by the two table walkers. */
835 /** Master id assigned by the MMU. */
838 /** Indicates whether this table walker is part of the stage 2 mmu */
841 /** TLB that is initiating these table walks */
844 /** Cached copy of the sctlr as it existed when translation began */
847 WalkerState *currState;
849 /** If a timing translation is currently in progress */
852 /** The number of walks belonging to squashed instructions that can be
853 * removed from the pendingQueue per cycle. */
854 unsigned numSquashable;
856 /** Cached copies of system-level properties */
859 bool _haveVirtualization;
860 uint8_t physAddrRange;
861 bool _haveLargeAsid64;
864 Stats::Scalar statWalks;
865 Stats::Scalar statWalksShortDescriptor;
866 Stats::Scalar statWalksLongDescriptor;
867 Stats::Vector statWalksShortTerminatedAtLevel;
868 Stats::Vector statWalksLongTerminatedAtLevel;
869 Stats::Scalar statSquashedBefore;
870 Stats::Scalar statSquashedAfter;
871 Stats::Histogram statWalkWaitTime;
872 Stats::Histogram statWalkServiceTime;
873 Stats::Histogram statPendingWalks; // essentially "L" of queueing theory
874 Stats::Vector statPageSizes;
875 Stats::Vector2d statRequestOrigin;
877 mutable unsigned pendingReqs;
878 mutable Tick pendingChangeTick;
880 static const unsigned REQUESTED = 0;
881 static const unsigned COMPLETED = 1;
884 typedef ArmTableWalkerParams Params;
885 TableWalker(const Params *p);
886 virtual ~TableWalker();
891 return dynamic_cast<const Params *>(_params);
894 void init() override;
896 bool haveLPAE() const { return _haveLPAE; }
897 bool haveVirtualization() const { return _haveVirtualization; }
898 bool haveLargeAsid64() const { return _haveLargeAsid64; }
899 /** Checks if all state is cleared and if so, completes drain */
900 void completeDrain();
901 DrainState drain() override;
902 void drainResume() override;
904 Port &getPort(const std::string &if_name,
905 PortID idx=InvalidPortID) override;
907 void regStats() override;
909 Fault walk(const RequestPtr &req, ThreadContext *tc,
910 uint16_t asid, uint8_t _vmid,
911 bool _isHyp, TLB::Mode mode, TLB::Translation *_trans,
912 bool timing, bool functional, bool secure,
913 TLB::ArmTranslationType tranType, bool _stage2Req);
915 void setTlb(TLB *_tlb) { tlb = _tlb; }
916 TLB* getTlb() { return tlb; }
917 void setMMU(Stage2MMU *m, MasterID master_id);
918 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
919 uint8_t texcb, bool s);
920 void memAttrsLPAE(ThreadContext *tc, TlbEntry &te,
921 LongDescriptor &lDescriptor);
922 void memAttrsAArch64(ThreadContext *tc, TlbEntry &te,
923 LongDescriptor &lDescriptor);
925 static LookupLevel toLookupLevel(uint8_t lookup_level_as_int);
929 void doL1Descriptor();
930 void doL1DescriptorWrapper();
931 EventFunctionWrapper doL1DescEvent;
933 void doL2Descriptor();
934 void doL2DescriptorWrapper();
935 EventFunctionWrapper doL2DescEvent;
937 void doLongDescriptor();
939 void doL0LongDescriptorWrapper();
940 EventFunctionWrapper doL0LongDescEvent;
941 void doL1LongDescriptorWrapper();
942 EventFunctionWrapper doL1LongDescEvent;
943 void doL2LongDescriptorWrapper();
944 EventFunctionWrapper doL2LongDescEvent;
945 void doL3LongDescriptorWrapper();
946 EventFunctionWrapper doL3LongDescEvent;
948 void doLongDescriptorWrapper(LookupLevel curr_lookup_level);
949 Event* LongDescEventByLevel[4];
951 bool fetchDescriptor(Addr descAddr, uint8_t *data, int numBytes,
952 Request::Flags flags, int queueIndex, Event *event,
953 void (TableWalker::*doDescriptor)());
955 Fault generateLongDescFault(ArmFault::FaultSource src);
957 void insertTableEntry(DescriptorBase &descriptor, bool longDescriptor);
960 Fault processWalkLPAE();
961 static unsigned adjustTableSizeAArch64(unsigned tsz);
962 /// Returns true if the address exceeds the range permitted by the
963 /// system-wide setting or by the TCR_ELx IPS/PS setting
964 static bool checkAddrSizeFaultAArch64(Addr addr, int currPhysAddrRange);
965 Fault processWalkAArch64();
966 void processWalkWrapper();
967 EventFunctionWrapper doProcessEvent;
969 void nextWalk(ThreadContext *tc);
971 void pendingChange();
973 static uint8_t pageSizeNtoStatBin(uint8_t N);
975 Fault testWalk(Addr pa, Addr size, TlbEntry::DomainType domain,
976 LookupLevel lookup_level);
979 } // namespace ArmISA
981 #endif //__ARCH_ARM_TABLE_WALKER_HH__