src/arch/arm/table_walker.hh

   1 /*
   2  * Copyright (c) 2010 ARM Limited
   3  * All rights reserved
   4  *
   5  * The license below extends only to copyright in the software and shall
   6  * not be construed as granting a license to any other intellectual
   7  * property including but not limited to intellectual property relating
   8  * to a hardware implementation of the functionality of the software
   9  * licensed hereunder.  You may use the software subject to the license
  10  * terms below provided that you ensure that this notice is replicated
  11  * unmodified and in its entirety in all distributions of the software,
  12  * modified or unmodified, in source code or in binary form.
  13  *
  14  * Redistribution and use in source and binary forms, with or without
  15  * modification, are permitted provided that the following conditions are
  16  * met: redistributions of source code must retain the above copyright
  17  * notice, this list of conditions and the following disclaimer;
  18  * redistributions in binary form must reproduce the above copyright
  19  * notice, this list of conditions and the following disclaimer in the
  20  * documentation and/or other materials provided with the distribution;
  21  * neither the name of the copyright holders nor the names of its
  22  * contributors may be used to endorse or promote products derived from
  23  * this software without specific prior written permission.
  24  *
  25  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  26  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  27  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  28  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  29  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  30  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  31  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  32  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  33  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  34  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  35  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  36  *
  37  * Authors: Ali Saidi
  38  */
  39
  40 #ifndef __ARCH_ARM_TABLE_WALKER_HH__
  41 #define __ARCH_ARM_TABLE_WALKER_HH__
  42
  43 #include "arch/arm/miscregs.hh"
  44 #include "arch/arm/tlb.hh"
  45 #include "mem/mem_object.hh"
  46 #include "mem/request.hh"
  47 #include "mem/request.hh"
  48 #include "params/ArmTableWalker.hh"
  49 #include "sim/faults.hh"
  50 #include "sim/eventq.hh"
  51 #include "base/fifo_buffer.hh"
  52
  53 class DmaPort;
  54 class ThreadContext;
  55
  56 namespace ArmISA {
  57 class Translation;
  58 class TLB;
  59
  60 class TableWalker : public MemObject
  61 {
  62   protected:
  63     struct L1Descriptor {
  64         /** Type of page table entry ARM DDI 0406B: B3-8*/
  65         enum EntryType {
  66             Ignore,
  67             PageTable,
  68             Section,
  69             Reserved
  70         };
  71
  72         /** The raw bits of the entry */
  73         uint32_t data;
  74
  75         /** This entry has been modified (access flag set) and needs to be
  76          * written back to memory */
  77         bool _dirty;
  78
  79         EntryType type() const
  80         {
  81             return (EntryType)(data & 0x3);
  82         }
  83
  84         /** Is the page a Supersection (16MB)?*/
  85         bool supersection() const
  86         {
  87             return bits(data, 18);
  88         }
  89
  90         /** Return the physcal address of the entry, bits in position*/
  91         Addr paddr() const
  92         {
  93             if (supersection())
  94                 panic("Super sections not implemented\n");
  95             return mbits(data, 31,20);
  96         }
  97
  98         /** Return the physical frame, bits shifted right */
  99         Addr pfn() const
 100         {
 101             if (supersection())
 102                 panic("Super sections not implemented\n");
 103             return bits(data, 31,20);
 104         }
 105
 106         /** Is the translation global (no asid used)? */
 107         bool global() const
 108         {
 109             return bits(data, 4);
 110         }
 111
 112         /** Is the translation not allow execution? */
 113         bool xn() const
 114         {
 115             return bits(data, 17);
 116         }
 117
 118         /** Three bit access protection flags */
 119         uint8_t ap() const
 120         {
 121             return (bits(data, 15) << 2) | bits(data,11,10);
 122         }
 123
 124         /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
 125         uint8_t domain() const
 126         {
 127             return bits(data,8,5);
 128         }
 129
 130         /** Address of L2 descriptor if it exists */
 131         Addr l2Addr() const
 132         {
 133             return mbits(data, 31,10);
 134         }
 135
 136         /** Memory region attributes: ARM DDI 0406B: B3-32.
 137          * These bits are largly ignored by M5 and only used to
 138          * provide the illusion that the memory system cares about
 139          * anything but cachable vs. uncachable.
 140          */
 141         uint8_t texcb() const
 142         {
 143             return bits(data, 2) | bits(data,3) << 1 | bits(data, 14, 12) << 2;
 144         }
 145
 146         /** If the section is shareable. See texcb() comment. */
 147         bool shareable() const
 148         {
 149             return bits(data, 16);
 150         }
 151
 152         /** Set access flag that this entry has been touched. Mark
 153          * the entry as requiring a writeback, in the future.
 154          */
 155         void setAp0()
 156         {
 157             data |= 1 << 10;
 158             _dirty = true;
 159         }
 160
 161         /** This entry needs to be written back to memory */
 162         bool dirty() const
 163         {
 164             return _dirty;
 165         }
 166     };
 167
 168     /** Level 2 page table descriptor */
 169     struct L2Descriptor {
 170
 171         /** The raw bits of the entry. */
 172         uint32_t data;
 173
 174         /** This entry has been modified (access flag set) and needs to be
 175          * written back to memory */
 176         bool _dirty;
 177
 178         /** Is the entry invalid */
 179         bool invalid() const
 180         {
 181             return bits(data, 1,0) == 0;;
 182         }
 183
 184         /** What is the size of the mapping? */
 185         bool large() const
 186         {
 187             return bits(data, 1) == 0;
 188         }
 189
 190         /** Is execution allowed on this mapping? */
 191         bool xn() const
 192         {
 193             return large() ? bits(data, 15) : bits(data, 0);
 194         }
 195
 196         /** Is the translation global (no asid used)? */
 197         bool global() const
 198         {
 199             return !bits(data, 11);
 200         }
 201
 202         /** Three bit access protection flags */
 203         uint8_t ap() const
 204         {
 205            return bits(data, 5, 4) | (bits(data, 9) << 2);
 206         }
 207
 208         /** Memory region attributes: ARM DDI 0406B: B3-32 */
 209         uint8_t texcb() const
 210         {
 211             return large() ?
 212                 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 14, 12) << 2)) :
 213                 (bits(data, 2) | (bits(data,3) << 1) | (bits(data, 8, 6) << 2));
 214         }
 215
 216         /** Return the physical frame, bits shifted right */
 217         Addr pfn() const
 218         {
 219             return large() ? bits(data, 31, 16) : bits(data, 31, 12);
 220         }
 221
 222         /** If the section is shareable. See texcb() comment. */
 223         bool shareable() const
 224         {
 225             return bits(data, 10);
 226         }
 227
 228         /** Set access flag that this entry has been touched. Mark
 229          * the entry as requiring a writeback, in the future.
 230          */
 231         void setAp0()
 232         {
 233             data |= 1 << 4;
 234             _dirty = true;
 235         }
 236
 237         /** This entry needs to be written back to memory */
 238         bool dirty() const
 239         {
 240             return _dirty;
 241         }
 242
 243     };
 244
 245     struct WalkerState //: public SimObject
 246     {
 247         /** Thread context that we're doing the walk for */
 248         ThreadContext *tc;
 249
 250         /** Request that is currently being serviced */
 251         RequestPtr req;
 252
 253         /** Context ID that we're servicing the request under */
 254         uint8_t contextId;
 255
 256         /** Translation state for delayed requests */
 257         TLB::Translation *transState;
 258
 259         /** The fault that we are going to return */
 260         Fault fault;
 261
 262         /** The virtual address that is being translated */
 263         Addr vaddr;
 264
 265         /** Cached copy of the sctlr as it existed when translation began */
 266         SCTLR sctlr;
 267
 268         /** Cached copy of the cpsr as it existed when the translation began */
 269         CPSR cpsr;
 270
 271         /** Width of the base address held in TTRB0 */
 272         uint32_t N;
 273
 274         /** If the access is a write */
 275         bool isWrite;
 276
 277         /** If the access is not from user mode */
 278         bool isPriv;
 279
 280         /** If the access is a fetch (for execution, and no-exec) must be checked?*/
 281         bool isFetch;
 282
 283         /** If the mode is timing or atomic */
 284         bool timing;
 285
 286         /** Save mode for use in delayed response */
 287         BaseTLB::Mode mode;
 288
 289         L1Descriptor l1Desc;
 290         L2Descriptor l2Desc;
 291
 292         /** Whether L1/L2 descriptor response is delayed in timing mode */
 293         bool delayed;
 294
 295         TableWalker *tableWalker;
 296
 297         void doL1Descriptor();
 298         void doL2Descriptor();
 299
 300         std::string name() const {return tableWalker->name();}
 301     };
 302
 303
 304     FifoBuffer<WalkerState> stateQueue;
 305
 306     /** Port to issue translation requests from */
 307     DmaPort *port;
 308
 309     /** TLB that is initiating these table walks */
 310     TLB *tlb;
 311
 312     /** Cached copy of the sctlr as it existed when translation began */
 313     SCTLR sctlr;
 314
 315     WalkerState *currState;
 316
 317   public:
 318     typedef ArmTableWalkerParams Params;
 319     TableWalker(const Params *p);
 320     virtual ~TableWalker();
 321
 322     const Params *
 323     params() const
 324     {
 325         return dynamic_cast<const Params *>(_params);
 326     }
 327
 328     virtual unsigned int drain(Event *de) { panic("write me\n"); }
 329     virtual Port *getPort(const std::string &if_name, int idx = -1);
 330
 331     Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
 332             TLB::Translation *_trans, bool timing);
 333
 334     void setTlb(TLB *_tlb) { tlb = _tlb; }
 335     void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
 336                   uint8_t texcb, bool s);
 337
 338   private:
 339
 340     void doL1Descriptor();
 341     void doL1DescriptorWrapper();
 342     EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent;
 343
 344     void doL2Descriptor();
 345     void doL2DescriptorWrapper();
 346     EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent;
 347
 348
 349 };
 350
 351
 352 } // namespace ArmISA
 353
 354 #endif //__ARCH_ARM_TABLE_WALKER_HH__
 355