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40 #ifndef __ARCH_ARM_TABLE_WALKER_HH__
41 #define __ARCH_ARM_TABLE_WALKER_HH__
45 #include "arch/arm/miscregs.hh"
46 #include "arch/arm/tlb.hh"
47 #include "mem/mem_object.hh"
48 #include "mem/request.hh"
49 #include "params/ArmTableWalker.hh"
50 #include "sim/eventq.hh"
51 #include "sim/fault_fwd.hh"
60 class TableWalker : public MemObject
64 /** Type of page table entry ARM DDI 0406B: B3-8*/
72 /** The raw bits of the entry */
75 /** This entry has been modified (access flag set) and needs to be
76 * written back to memory */
79 EntryType type() const
81 return (EntryType)(data & 0x3);
84 /** Is the page a Supersection (16MB)?*/
85 bool supersection() const
87 return bits(data, 18);
90 /** Return the physcal address of the entry, bits in position*/
94 panic("Super sections not implemented\n");
95 return mbits(data, 31, 20);
97 /** Return the physcal address of the entry, bits in position*/
98 Addr paddr(Addr va) const
101 panic("Super sections not implemented\n");
102 return mbits(data, 31, 20) | mbits(va, 19, 0);
106 /** Return the physical frame, bits shifted right */
110 panic("Super sections not implemented\n");
111 return bits(data, 31, 20);
114 /** Is the translation global (no asid used)? */
117 return bits(data, 17);
120 /** Is the translation not allow execution? */
123 return bits(data, 4);
126 /** Three bit access protection flags */
129 return (bits(data, 15) << 2) | bits(data, 11, 10);
132 /** Domain Client/Manager: ARM DDI 0406B: B3-31 */
133 uint8_t domain() const
135 return bits(data, 8, 5);
138 /** Address of L2 descriptor if it exists */
141 return mbits(data, 31, 10);
144 /** Memory region attributes: ARM DDI 0406B: B3-32.
145 * These bits are largly ignored by M5 and only used to
146 * provide the illusion that the memory system cares about
147 * anything but cachable vs. uncachable.
149 uint8_t texcb() const
151 return bits(data, 2) | bits(data, 3) << 1 | bits(data, 14, 12) << 2;
154 /** If the section is shareable. See texcb() comment. */
155 bool shareable() const
157 return bits(data, 16);
160 /** Set access flag that this entry has been touched. Mark
161 * the entry as requiring a writeback, in the future.
169 /** This entry needs to be written back to memory */
176 /** Level 2 page table descriptor */
177 struct L2Descriptor {
179 /** The raw bits of the entry. */
182 /** This entry has been modified (access flag set) and needs to be
183 * written back to memory */
186 /** Is the entry invalid */
189 return bits(data, 1, 0) == 0;
192 /** What is the size of the mapping? */
195 return bits(data, 1) == 0;
198 /** Is execution allowed on this mapping? */
201 return large() ? bits(data, 15) : bits(data, 0);
204 /** Is the translation global (no asid used)? */
207 return !bits(data, 11);
210 /** Three bit access protection flags */
213 return bits(data, 5, 4) | (bits(data, 9) << 2);
216 /** Memory region attributes: ARM DDI 0406B: B3-32 */
217 uint8_t texcb() const
220 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 14, 12) << 2)) :
221 (bits(data, 2) | (bits(data, 3) << 1) | (bits(data, 8, 6) << 2));
224 /** Return the physical frame, bits shifted right */
227 return large() ? bits(data, 31, 16) : bits(data, 31, 12);
230 /** Return complete physical address given a VA */
231 Addr paddr(Addr va) const
234 return mbits(data, 31, 16) | mbits(va, 15, 0);
236 return mbits(data, 31, 12) | mbits(va, 11, 0);
239 /** If the section is shareable. See texcb() comment. */
240 bool shareable() const
242 return bits(data, 10);
245 /** Set access flag that this entry has been touched. Mark
246 * the entry as requiring a writeback, in the future.
254 /** This entry needs to be written back to memory */
262 struct WalkerState //: public SimObject
264 /** Thread context that we're doing the walk for */
267 /** Request that is currently being serviced */
270 /** Context ID that we're servicing the request under */
273 /** Translation state for delayed requests */
274 TLB::Translation *transState;
276 /** The fault that we are going to return */
279 /** The virtual address that is being translated */
282 /** Cached copy of the sctlr as it existed when translation began */
285 /** Width of the base address held in TTRB0 */
288 /** If the access is a write */
291 /** If the access is a fetch (for execution, and no-exec) must be checked?*/
294 /** If the mode is timing or atomic */
297 /** If the atomic mode should be functional */
300 /** Save mode for use in delayed response */
306 /** Whether L1/L2 descriptor response is delayed in timing mode */
309 TableWalker *tableWalker;
311 void doL1Descriptor();
312 void doL2Descriptor();
314 std::string name() const {return tableWalker->name();}
318 /** Queue of requests that need processing first level translation */
319 std::list<WalkerState *> stateQueueL1;
321 /** Queue of requests that have passed first level translation and
322 * require an additional level. */
323 std::list<WalkerState *> stateQueueL2;
325 /** Queue of requests that have passed are waiting because the walker is
327 std::list<WalkerState *> pendingQueue;;
330 /** Port to issue translation requests from */
333 /** TLB that is initiating these table walks */
336 /** Cached copy of the sctlr as it existed when translation began */
339 WalkerState *currState;
341 /** If a timing translation is currently in progress */
345 typedef ArmTableWalkerParams Params;
346 TableWalker(const Params *p);
347 virtual ~TableWalker();
352 return dynamic_cast<const Params *>(_params);
355 virtual unsigned int drain(Event *de);
356 virtual void resume();
357 virtual Port *getPort(const std::string &if_name, int idx = -1);
359 Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode,
360 TLB::Translation *_trans, bool timing, bool functional = false);
362 void setTlb(TLB *_tlb) { tlb = _tlb; }
363 void memAttrs(ThreadContext *tc, TlbEntry &te, SCTLR sctlr,
364 uint8_t texcb, bool s);
368 void doL1Descriptor();
369 void doL1DescriptorWrapper();
370 EventWrapper<TableWalker, &TableWalker::doL1DescriptorWrapper> doL1DescEvent;
372 void doL2Descriptor();
373 void doL2DescriptorWrapper();
374 EventWrapper<TableWalker, &TableWalker::doL2DescriptorWrapper> doL2DescEvent;
377 void processWalkWrapper();
378 EventWrapper<TableWalker, &TableWalker::processWalkWrapper> doProcessEvent;
380 void nextWalk(ThreadContext *tc);
384 } // namespace ArmISA
386 #endif //__ARCH_ARM_TABLE_WALKER_HH__